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i2c-imx.c
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linux-6.19.14/drivers/i2c/busses/i2c-imx.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020, 2024 NXP 21 * 22 */ 23 24#include <linux/acpi.h> 25#include <linux/clk.h> 26#include <linux/cleanup.h> 27#include <linux/completion.h> 28#include <linux/delay.h> 29#include <linux/dma-mapping.h> 30#include <linux/dmaengine.h> 31#include <linux/dmapool.h> 32#include <linux/err.h> 33#include <linux/errno.h> 34#include <linux/gpio/consumer.h> 35#include <linux/i2c.h> 36#include <linux/init.h> 37#include <linux/interrupt.h> 38#include <linux/io.h> 39#include <linux/iopoll.h> 40#include <linux/kernel.h> 41#include <linux/spinlock.h> 42#include <linux/hrtimer.h> 43#include <linux/module.h> 44#include <linux/of.h> 45#include <linux/of_dma.h> 46#include <linux/pinctrl/consumer.h> 47#include <linux/platform_data/i2c-imx.h> 48#include <linux/platform_device.h> 49#include <linux/pm_runtime.h> 50#include <linux/sched.h> 51#include <linux/slab.h> 52 53/* This will be the driver name the kernel reports */ 54#define DRIVER_NAME "imx-i2c" 55 56#define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 57 58/* 59 * Enable DMA if transfer byte size is bigger than this threshold. 60 * As the hardware request, it must bigger than 4 bytes.\ 61 * I have set '16' here, maybe it's not the best but I think it's 62 * the appropriate. 63 */ 64#define DMA_THRESHOLD 16 65#define DMA_TIMEOUT 1000 66 67/* IMX I2C registers: 68 * the I2C register offset is different between SoCs, 69 * to provide support for all these chips, split the 70 * register offset into a fixed base address and a 71 * variable shift value, then the full register offset 72 * will be calculated by 73 * reg_off = ( reg_base_addr << reg_shift) 74 */ 75#define IMX_I2C_IADR 0x00 /* i2c slave address */ 76#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 77#define IMX_I2C_I2CR 0x02 /* i2c control */ 78#define IMX_I2C_I2SR 0x03 /* i2c status */ 79#define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 80 81/* 82 * All of the layerscape series SoCs support IBIC register. 83 */ 84#define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 85 86#define IMX_I2C_REGSHIFT 2 87#define VF610_I2C_REGSHIFT 0 88#define S32G_I2C_REGSHIFT 0 89 90/* Bits of IMX I2C registers */ 91#define I2SR_RXAK 0x01 92#define I2SR_IIF 0x02 93#define I2SR_SRW 0x04 94#define I2SR_IAL 0x10 95#define I2SR_IBB 0x20 96#define I2SR_IAAS 0x40 97#define I2SR_ICF 0x80 98#define I2CR_DMAEN 0x02 99#define I2CR_RSTA 0x04 100#define I2CR_TXAK 0x08 101#define I2CR_MTX 0x10 102#define I2CR_MSTA 0x20 103#define I2CR_IIEN 0x40 104#define I2CR_IEN 0x80 105#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 106 107/* register bits different operating codes definition: 108 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 109 * - write zero to clear(w0c) INT flag on i.MX, 110 * - but write one to clear(w1c) INT flag on Vybrid. 111 * 2) I2CR: I2C module enable operation also differ between SoCs: 112 * - set I2CR_IEN bit enable the module on i.MX, 113 * - but clear I2CR_IEN bit enable the module on Vybrid. 114 */ 115#define I2SR_CLR_OPCODE_W0C 0x0 116#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 117#define I2CR_IEN_OPCODE_0 0x0 118#define I2CR_IEN_OPCODE_1 I2CR_IEN 119 120#define I2C_PM_TIMEOUT 10 /* ms */ 121 122/* 123 * sorted list of clock divider, register value pairs 124 * taken from table 26-5, p.26-9, Freescale i.MX 125 * Integrated Portable System Processor Reference Manual 126 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 127 * 128 * Duplicated divider values removed from list 129 */ 130struct imx_i2c_clk_pair { 131 u16 div; 132 u16 val; 133}; 134 135static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 136 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 137 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 138 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 139 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 140 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 141 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 142 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 143 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 144 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 145 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 146 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 147 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 148 { 3072, 0x1E }, { 3840, 0x1F } 149}; 150 151/* Vybrid VF610 clock divider, register value pairs */ 152static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 153 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 154 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 155 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 156 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 157 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 158 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 159 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 160 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 161 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 162 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 163 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 164 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 165 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 166 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 167 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 168}; 169 170/* S32G2/S32G3 clock divider, register value pairs */ 171static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { 172 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, 173 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, 174 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, 175 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, 176 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, 177 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, 178 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, 179 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, 180 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, 181 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, 182 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, 183 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 184 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, 185 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, 186 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, 187 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, 188 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, 189 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, 190 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, 191 { 12288, 0xBE }, { 15360, 0xBF }, 192}; 193 194enum imx_i2c_type { 195 IMX1_I2C, 196 IMX21_I2C, 197 S32G_I2C, 198 VF610_I2C, 199}; 200 201struct imx_i2c_hwdata { 202 enum imx_i2c_type devtype; 203 unsigned int regshift; 204 struct imx_i2c_clk_pair *clk_div; 205 unsigned int ndivs; 206 unsigned int i2sr_clr_opcode; 207 unsigned int i2cr_ien_opcode; 208 /* 209 * Errata ERR007805 or e7805: 210 * I2C: When the I2C clock speed is configured for 400 kHz, 211 * the SCL low period violates the I2C spec of 1.3 uS min. 212 */ 213 bool has_err007805; 214}; 215 216struct imx_i2c_dma { 217 struct dma_chan *chan_tx; 218 struct dma_chan *chan_rx; 219 struct dma_chan *chan_using; 220 struct completion cmd_complete; 221 dma_addr_t dma_buf; 222 unsigned int dma_len; 223 enum dma_transfer_direction dma_transfer_dir; 224 enum dma_data_direction dma_data_dir; 225}; 226 227enum imx_i2c_state { 228 IMX_I2C_STATE_DONE, 229 IMX_I2C_STATE_FAILED, 230 IMX_I2C_STATE_WRITE, 231 IMX_I2C_STATE_DMA, 232 IMX_I2C_STATE_READ, 233 IMX_I2C_STATE_READ_CONTINUE, 234 IMX_I2C_STATE_READ_BLOCK_DATA, 235 IMX_I2C_STATE_READ_BLOCK_DATA_LEN, 236}; 237 238struct imx_i2c_struct { 239 struct i2c_adapter adapter; 240 struct clk *clk; 241 struct notifier_block clk_change_nb; 242 void __iomem *base; 243 wait_queue_head_t queue; 244 unsigned long i2csr; 245 unsigned int disable_delay; 246 int stopped; 247 unsigned int ifdr; /* IMX_I2C_IFDR */ 248 unsigned int cur_clk; 249 unsigned int bitrate; 250 const struct imx_i2c_hwdata *hwdata; 251 struct i2c_bus_recovery_info rinfo; 252 253 struct imx_i2c_dma *dma; 254 struct i2c_client *slave; 255 enum i2c_slave_event last_slave_event; 256 257 struct i2c_msg *msg; 258 unsigned int msg_buf_idx; 259 int isr_result; 260 bool is_lastmsg; 261 enum imx_i2c_state state; 262 263 bool multi_master; 264 265 /* For checking slave events. */ 266 spinlock_t slave_lock; 267 struct hrtimer slave_timer; 268}; 269 270static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 271 .devtype = IMX1_I2C, 272 .regshift = IMX_I2C_REGSHIFT, 273 .clk_div = imx_i2c_clk_div, 274 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 275 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 276 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 277 278}; 279 280static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 281 .devtype = IMX21_I2C, 282 .regshift = IMX_I2C_REGSHIFT, 283 .clk_div = imx_i2c_clk_div, 284 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 285 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 286 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 287 288}; 289 290static const struct imx_i2c_hwdata imx6_i2c_hwdata = { 291 .devtype = IMX21_I2C, 292 .regshift = IMX_I2C_REGSHIFT, 293 .clk_div = imx_i2c_clk_div, 294 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 295 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 296 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 297 .has_err007805 = true, 298}; 299 300static struct imx_i2c_hwdata vf610_i2c_hwdata = { 301 .devtype = VF610_I2C, 302 .regshift = VF610_I2C_REGSHIFT, 303 .clk_div = vf610_i2c_clk_div, 304 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 305 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 306 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 307}; 308 309static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { 310 .devtype = S32G_I2C, 311 .regshift = S32G_I2C_REGSHIFT, 312 .clk_div = s32g2_i2c_clk_div, 313 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), 314 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 315 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 316}; 317 318static const struct platform_device_id imx_i2c_devtype[] = { 319 { 320 .name = "imx1-i2c", 321 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 322 }, { 323 .name = "imx21-i2c", 324 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 325 }, { 326 /* sentinel */ 327 } 328}; 329MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 330 331static const struct of_device_id i2c_imx_dt_ids[] = { 332 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 333 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 334 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, }, 335 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, }, 336 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, }, 337 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, }, 338 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, }, 339 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, }, 340 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, }, 341 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, }, 342 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, }, 343 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, }, 344 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, }, 345 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 346 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, 347 { /* sentinel */ } 348}; 349MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 350 351static const struct acpi_device_id i2c_imx_acpi_ids[] = { 352 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 353 { } 354}; 355MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 356 357static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 358{ 359 return i2c_imx->hwdata->devtype == IMX1_I2C; 360} 361 362static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 363{ 364 return i2c_imx->hwdata->devtype == VF610_I2C; 365} 366 367static inline void imx_i2c_write_reg(unsigned int val, 368 struct imx_i2c_struct *i2c_imx, unsigned int reg) 369{ 370 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 371} 372 373static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 374 unsigned int reg) 375{ 376 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 377} 378 379static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 380{ 381 unsigned int temp; 382 383 /* 384 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 385 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 386 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 387 */ 388 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 389 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 390} 391 392/* Set up i2c controller register and i2c status register to default value. */ 393static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 394{ 395 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 396 i2c_imx, IMX_I2C_I2CR); 397 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 398} 399 400/* Functions for DMA support */ 401static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr) 402{ 403 struct imx_i2c_dma *dma; 404 struct dma_slave_config dma_sconfig = {}; 405 struct device *dev = i2c_imx->adapter.dev.parent; 406 int ret; 407 408 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 409 if (!dma) 410 return -ENOMEM; 411 412 dma->chan_tx = dma_request_chan(dev, "tx"); 413 if (IS_ERR(dma->chan_tx)) { 414 ret = PTR_ERR(dma->chan_tx); 415 if (ret != -ENODEV && ret != -EPROBE_DEFER) 416 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 417 goto fail_al; 418 } 419 420 dma_sconfig.dst_addr = phy_addr + 421 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 422 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 423 dma_sconfig.dst_maxburst = 1; 424 dma_sconfig.direction = DMA_MEM_TO_DEV; 425 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 426 if (ret < 0) { 427 dev_err(dev, "can't configure tx channel (%d)\n", ret); 428 goto fail_tx; 429 } 430 431 dma->chan_rx = dma_request_chan(dev, "rx"); 432 if (IS_ERR(dma->chan_rx)) { 433 ret = PTR_ERR(dma->chan_rx); 434 if (ret != -ENODEV && ret != -EPROBE_DEFER) 435 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 436 goto fail_tx; 437 } 438 439 dma_sconfig.src_addr = phy_addr + 440 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 441 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 442 dma_sconfig.src_maxburst = 1; 443 dma_sconfig.direction = DMA_DEV_TO_MEM; 444 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 445 if (ret < 0) { 446 dev_err(dev, "can't configure rx channel (%d)\n", ret); 447 goto fail_rx; 448 } 449 450 i2c_imx->dma = dma; 451 init_completion(&dma->cmd_complete); 452 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 453 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 454 455 return 0; 456 457fail_rx: 458 dma_release_channel(dma->chan_rx); 459fail_tx: 460 dma_release_channel(dma->chan_tx); 461fail_al: 462 devm_kfree(dev, dma); 463 464 return ret; 465} 466 467static void i2c_imx_dma_callback(void *arg) 468{ 469 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 470 struct imx_i2c_dma *dma = i2c_imx->dma; 471 472 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 473 dma->dma_len, dma->dma_data_dir); 474 complete(&dma->cmd_complete); 475} 476 477static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 478 struct i2c_msg *msgs) 479{ 480 struct imx_i2c_dma *dma = i2c_imx->dma; 481 struct dma_async_tx_descriptor *txdesc; 482 struct device *dev = &i2c_imx->adapter.dev; 483 struct device *chan_dev = dma->chan_using->device->dev; 484 485 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 486 dma->dma_len, dma->dma_data_dir); 487 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 488 dev_err(dev, "DMA mapping failed\n"); 489 goto err_map; 490 } 491 492 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 493 dma->dma_len, dma->dma_transfer_dir, 494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 495 if (!txdesc) { 496 dev_err(dev, "Not able to get desc for DMA xfer\n"); 497 goto err_desc; 498 } 499 500 reinit_completion(&dma->cmd_complete); 501 txdesc->callback = i2c_imx_dma_callback; 502 txdesc->callback_param = i2c_imx; 503 if (dma_submit_error(dmaengine_submit(txdesc))) { 504 dev_err(dev, "DMA submit failed\n"); 505 goto err_submit; 506 } 507 508 dma_async_issue_pending(dma->chan_using); 509 return 0; 510 511err_submit: 512 dmaengine_terminate_sync(dma->chan_using); 513err_desc: 514 dma_unmap_single(chan_dev, dma->dma_buf, 515 dma->dma_len, dma->dma_data_dir); 516err_map: 517 return -EINVAL; 518} 519 520static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 521{ 522 struct imx_i2c_dma *dma = i2c_imx->dma; 523 524 dma->dma_buf = 0; 525 dma->dma_len = 0; 526 527 dma_release_channel(dma->chan_tx); 528 dma->chan_tx = NULL; 529 530 dma_release_channel(dma->chan_rx); 531 dma->chan_rx = NULL; 532 533 dma->chan_using = NULL; 534} 535 536static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 537{ 538 bool multi_master = i2c_imx->multi_master; 539 unsigned long orig_jiffies = jiffies; 540 unsigned int temp; 541 542 while (1) { 543 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 544 545 /* check for arbitration lost */ 546 if (multi_master && (temp & I2SR_IAL)) { 547 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 548 return -EAGAIN; 549 } 550 551 if (for_busy && (!multi_master || (temp & I2SR_IBB))) { 552 i2c_imx->stopped = 0; 553 break; 554 } 555 if (!for_busy && !(temp & I2SR_IBB)) { 556 i2c_imx->stopped = 1; 557 break; 558 } 559 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 560 dev_dbg(&i2c_imx->adapter.dev, 561 "<%s> I2C bus is busy\n", __func__); 562 return -ETIMEDOUT; 563 } 564 if (atomic) 565 udelay(100); 566 else 567 schedule(); 568 } 569 570 return 0; 571} 572 573static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 574{ 575 if (atomic) { 576 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 577 unsigned int regval; 578 579 /* 580 * The formula for the poll timeout is documented in the RM 581 * Rev.5 on page 1878: 582 * T_min = 10/F_scl 583 * Set the value hard as it is done for the non-atomic use-case. 584 * Use 10 kHz for the calculation since this is the minimum 585 * allowed SMBus frequency. Also add an offset of 100us since it 586 * turned out that the I2SR_IIF bit isn't set correctly within 587 * the minimum timeout in polling mode. 588 */ 589 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 590 i2c_imx->i2csr = regval; 591 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 592 } else { 593 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 594 } 595 596 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 597 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 598 return -ETIMEDOUT; 599 } 600 601 /* In multi-master mode check for arbitration lost */ 602 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { 603 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 604 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 605 606 i2c_imx->i2csr = 0; 607 return -EAGAIN; 608 } 609 610 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 611 i2c_imx->i2csr = 0; 612 return 0; 613} 614 615static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 616{ 617 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 618 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 619 return -ENXIO; /* No ACK */ 620 } 621 622 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 623 return 0; 624} 625 626static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 627 unsigned int i2c_clk_rate) 628{ 629 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 630 unsigned int div; 631 int i; 632 633 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { 634 dev_dbg(&i2c_imx->adapter.dev, 635 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n", 636 i2c_imx->bitrate); 637 i2c_imx->bitrate = 384000; 638 } 639 640 /* Divider value calculation */ 641 if (i2c_imx->cur_clk == i2c_clk_rate) 642 return 0; 643 644 /* Keep the denominator of the following program always NOT equal to 0. */ 645 if (!(i2c_clk_rate / 2)) 646 return -EINVAL; 647 648 i2c_imx->cur_clk = i2c_clk_rate; 649 650 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 651 if (div < i2c_clk_div[0].div) 652 i = 0; 653 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 654 i = i2c_imx->hwdata->ndivs - 1; 655 else 656 for (i = 0; i2c_clk_div[i].div < div; i++) 657 ; 658 659 /* Store divider value */ 660 i2c_imx->ifdr = i2c_clk_div[i].val; 661 662 /* 663 * There dummy delay is calculated. 664 * It should be about one I2C clock period long. 665 * This delay is used in I2C bus disable function 666 * to fix chip hardware bug. 667 */ 668 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 669 i2c_clk_rate / 2); 670 671#ifdef CONFIG_I2C_DEBUG_BUS 672 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 673 i2c_clk_rate, div); 674 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 675 i2c_clk_div[i].val, i2c_clk_div[i].div); 676#endif 677 678 return 0; 679} 680 681static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 682 unsigned long action, void *data) 683{ 684 struct clk_notifier_data *ndata = data; 685 struct imx_i2c_struct *i2c_imx = container_of(nb, 686 struct imx_i2c_struct, 687 clk_change_nb); 688 int ret = 0; 689 690 if (action & POST_RATE_CHANGE) 691 ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate); 692 693 return notifier_from_errno(ret); 694} 695 696static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 697{ 698 unsigned int temp = 0; 699 int result; 700 701 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 702 /* Enable I2C controller */ 703 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 704 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 705 706 /* Wait controller to be stable */ 707 if (atomic) 708 udelay(50); 709 else 710 usleep_range(50, 150); 711 712 /* Start I2C transaction */ 713 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 714 temp |= I2CR_MSTA; 715 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 716 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 717 if (result) 718 return result; 719 720 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 721 if (atomic) 722 temp &= ~I2CR_IIEN; /* Disable interrupt */ 723 724 temp &= ~I2CR_DMAEN; 725 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 726 return result; 727} 728 729static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 730{ 731 unsigned int temp = 0; 732 733 if (!i2c_imx->stopped) { 734 /* Stop I2C transaction */ 735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 736 if (!(temp & I2CR_MSTA)) 737 i2c_imx->stopped = 1; 738 temp &= ~(I2CR_MSTA | I2CR_MTX); 739 if (i2c_imx->dma) 740 temp &= ~I2CR_DMAEN; 741 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 742 } 743 if (is_imx1_i2c(i2c_imx)) { 744 /* 745 * This delay caused by an i.MXL hardware bug. 746 * If no (or too short) delay, no "STOP" bit will be generated. 747 */ 748 udelay(i2c_imx->disable_delay); 749 } 750 751 if (!i2c_imx->stopped) 752 i2c_imx_bus_busy(i2c_imx, 0, atomic); 753 754 /* Disable I2C controller */ 755 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN; 756 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 757} 758 759/* 760 * Enable bus idle interrupts 761 * Note: IBIC register will be cleared after disabled i2c module. 762 * All of layerscape series SoCs support IBIC register. 763 */ 764static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 765{ 766 if (is_vf610_i2c(i2c_imx)) { 767 unsigned int temp; 768 769 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 770 temp |= IBIC_BIIE; 771 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 772 } 773} 774 775static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 776 enum i2c_slave_event event, u8 *val) 777{ 778 i2c_slave_event(i2c_imx->slave, event, val); 779 i2c_imx->last_slave_event = event; 780} 781 782static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 783{ 784 u8 val = 0; 785 786 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 787 switch (i2c_imx->last_slave_event) { 788 case I2C_SLAVE_READ_REQUESTED: 789 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 790 &val); 791 break; 792 793 case I2C_SLAVE_WRITE_REQUESTED: 794 case I2C_SLAVE_READ_PROCESSED: 795 case I2C_SLAVE_WRITE_RECEIVED: 796 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 797 break; 798 799 case I2C_SLAVE_STOP: 800 break; 801 } 802 } 803} 804 805/* Returns true if the timer should be restarted, false if not. */ 806static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 807 unsigned int status, unsigned int ctl) 808{ 809 u8 value = 0; 810 811 if (status & I2SR_IAL) { /* Arbitration lost */ 812 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 813 if (!(status & I2SR_IAAS)) 814 return IRQ_HANDLED; 815 } 816 817 if (!(status & I2SR_IBB)) { 818 /* No master on the bus, that could mean a stop condition. */ 819 i2c_imx_slave_finish_op(i2c_imx); 820 return IRQ_HANDLED; 821 } 822 823 if (!(status & I2SR_ICF)) 824 /* Data transfer still in progress, ignore this. */ 825 goto out; 826 827 if (status & I2SR_IAAS) { /* Addressed as a slave */ 828 i2c_imx_slave_finish_op(i2c_imx); 829 if (status & I2SR_SRW) { /* Master wants to read from us*/ 830 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 831 i2c_imx_slave_event(i2c_imx, 832 I2C_SLAVE_READ_REQUESTED, &value); 833 834 /* Slave transmit */ 835 ctl |= I2CR_MTX; 836 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 837 838 /* Send data */ 839 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 840 } else { /* Master wants to write to us */ 841 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 842 i2c_imx_slave_event(i2c_imx, 843 I2C_SLAVE_WRITE_REQUESTED, &value); 844 845 /* Slave receive */ 846 ctl &= ~I2CR_MTX; 847 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 848 /* Dummy read */ 849 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 850 } 851 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 852 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 853 i2c_imx_slave_event(i2c_imx, 854 I2C_SLAVE_WRITE_RECEIVED, &value); 855 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 856 ctl |= I2CR_MTX; 857 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 858 859 i2c_imx_slave_event(i2c_imx, 860 I2C_SLAVE_READ_PROCESSED, &value); 861 862 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 863 } else { /* Transmit mode received NAK, operation is done */ 864 ctl &= ~I2CR_MTX; 865 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 866 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 867 868 /* flag the last byte as processed */ 869 i2c_imx_slave_event(i2c_imx, 870 I2C_SLAVE_READ_PROCESSED, &value); 871 872 i2c_imx_slave_finish_op(i2c_imx); 873 return IRQ_HANDLED; 874 } 875 876out: 877 /* 878 * No need to check the return value here. If it returns 0 or 879 * 1, then everything is fine. If it returns -1, then the 880 * timer is running in the handler. This will still work, 881 * though it may be redone (or already have been done) by the 882 * timer function. 883 */ 884 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 885 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 886 hrtimer_restart(&i2c_imx->slave_timer); 887 return IRQ_HANDLED; 888} 889 890static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 891{ 892 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 893 slave_timer); 894 unsigned int ctl, status; 895 896 guard(spinlock_irqsave)(&i2c_imx->slave_lock); 897 898 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 899 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 900 i2c_imx_slave_handle(i2c_imx, status, ctl); 901 902 return HRTIMER_NORESTART; 903} 904 905static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 906{ 907 int temp; 908 909 /* Set slave addr. */ 910 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 911 912 i2c_imx_reset_regs(i2c_imx); 913 914 /* Enable module */ 915 temp = i2c_imx->hwdata->i2cr_ien_opcode; 916 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 917 918 /* Enable interrupt from i2c module */ 919 temp |= I2CR_IIEN; 920 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 921 922 i2c_imx_enable_bus_idle(i2c_imx); 923} 924 925static int i2c_imx_reg_slave(struct i2c_client *client) 926{ 927 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 928 int ret; 929 930 if (i2c_imx->slave) 931 return -EBUSY; 932 933 i2c_imx->slave = client; 934 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 935 936 /* Resume */ 937 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 938 if (ret < 0) { 939 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 940 return ret; 941 } 942 943 i2c_imx_slave_init(i2c_imx); 944 945 return 0; 946} 947 948static int i2c_imx_unreg_slave(struct i2c_client *client) 949{ 950 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 951 int ret; 952 953 if (!i2c_imx->slave) 954 return -EINVAL; 955 956 /* Reset slave address. */ 957 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 958 959 i2c_imx_reset_regs(i2c_imx); 960 961 i2c_imx->slave = NULL; 962 963 /* Suspend */ 964 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 965 if (ret < 0) 966 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 967 968 return ret; 969} 970 971static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) 972{ 973 i2c_imx->isr_result = 0; 974 975 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 976 i2c_imx->state = IMX_I2C_STATE_FAILED; 977 i2c_imx->isr_result = -ENXIO; 978 wake_up(&i2c_imx->queue); 979 } 980 981 return i2c_imx->isr_result; 982} 983 984static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) 985{ 986 int result; 987 988 result = i2c_imx_isr_acked(i2c_imx); 989 if (result) 990 return result; 991 992 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx) 993 return 0; 994 995 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR); 996 997 return 1; 998} 999 1000static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) 1001{ 1002 int result; 1003 unsigned int temp; 1004 1005 result = i2c_imx_isr_acked(i2c_imx); 1006 if (result) 1007 return result; 1008 1009 /* setup bus to read data */ 1010 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1011 temp &= ~I2CR_MTX; 1012 if ((i2c_imx->msg->len - 1) || (i2c_imx->msg->flags & I2C_M_RECV_LEN)) 1013 temp &= ~I2CR_TXAK; 1014 1015 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1016 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1017 1018 return 0; 1019} 1020 1021static inline enum imx_i2c_state i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx) 1022{ 1023 enum imx_i2c_state next_state = IMX_I2C_STATE_READ_CONTINUE; 1024 unsigned int temp; 1025 1026 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) { 1027 if (i2c_imx->is_lastmsg) { 1028 /* 1029 * It must generate STOP before read I2DR to prevent 1030 * controller from generating another clock cycle 1031 */ 1032 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1033 if (!(temp & I2CR_MSTA)) 1034 i2c_imx->stopped = 1; 1035 temp &= ~(I2CR_MSTA | I2CR_MTX); 1036 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1037 1038 return IMX_I2C_STATE_DONE; 1039 } 1040 /* 1041 * For i2c master receiver repeat restart operation like: 1042 * read -> repeat MSTA -> read/write 1043 * The controller must set MTX before read the last byte in 1044 * the first read operation, otherwise the first read cost 1045 * one extra clock cycle. 1046 */ 1047 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1048 temp |= I2CR_MTX; 1049 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1050 next_state = IMX_I2C_STATE_DONE; 1051 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) { 1052 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1053 temp |= I2CR_TXAK; 1054 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1055 } 1056 1057 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1058 return next_state; 1059} 1060 1061static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx) 1062{ 1063 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1064 1065 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) { 1066 i2c_imx->isr_result = -EPROTO; 1067 i2c_imx->state = IMX_I2C_STATE_FAILED; 1068 wake_up(&i2c_imx->queue); 1069 } 1070 i2c_imx->msg->len += len; 1071 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = len; 1072} 1073 1074static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 1075{ 1076 /* 1077 * This state machine handles I2C reception and transmission in non-DMA 1078 * mode. We must process all the data in the ISR to reduce the delay 1079 * between two consecutive messages. If the data is not processed in 1080 * the ISR, SMBus devices may timeout, leading to a bus error. 1081 */ 1082 switch (i2c_imx->state) { 1083 case IMX_I2C_STATE_DMA: 1084 i2c_imx->i2csr = status; 1085 wake_up(&i2c_imx->queue); 1086 break; 1087 1088 case IMX_I2C_STATE_READ: 1089 if (i2c_imx_isr_read(i2c_imx)) 1090 break; 1091 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1092 break; 1093 1094 case IMX_I2C_STATE_READ_CONTINUE: 1095 i2c_imx->state = i2c_imx_isr_read_continue(i2c_imx); 1096 if (i2c_imx->state == IMX_I2C_STATE_DONE) 1097 wake_up(&i2c_imx->queue); 1098 break; 1099 1100 case IMX_I2C_STATE_READ_BLOCK_DATA: 1101 if (i2c_imx_isr_read(i2c_imx)) 1102 break; 1103 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN; 1104 break; 1105 1106 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: 1107 i2c_imx_isr_read_block_data_len(i2c_imx); 1108 if (i2c_imx->state == IMX_I2C_STATE_READ_BLOCK_DATA_LEN) 1109 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1110 break; 1111 1112 case IMX_I2C_STATE_WRITE: 1113 if (i2c_imx_isr_write(i2c_imx)) 1114 break; 1115 i2c_imx->state = IMX_I2C_STATE_DONE; 1116 wake_up(&i2c_imx->queue); 1117 break; 1118 1119 default: 1120 i2c_imx->i2csr = status; 1121 i2c_imx->state = IMX_I2C_STATE_FAILED; 1122 i2c_imx->isr_result = -EINVAL; 1123 wake_up(&i2c_imx->queue); 1124 } 1125 1126 return IRQ_HANDLED; 1127} 1128 1129static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 1130{ 1131 struct imx_i2c_struct *i2c_imx = dev_id; 1132 unsigned int ctl, status; 1133 1134 scoped_guard(spinlock_irqsave, &i2c_imx->slave_lock) { 1135 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1136 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1137 1138 if (!(status & I2SR_IIF)) 1139 return IRQ_NONE; 1140 1141 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 1142 1143 if (i2c_imx->slave) { 1144 if (!(ctl & I2CR_MSTA)) 1145 return i2c_imx_slave_handle(i2c_imx, 1146 status, ctl); 1147 1148 i2c_imx_slave_finish_op(i2c_imx); 1149 } 1150 } 1151 1152 return i2c_imx_master_isr(i2c_imx, status); 1153} 1154 1155static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 1156 struct i2c_msg *msgs) 1157{ 1158 int result; 1159 unsigned long time_left; 1160 unsigned int temp = 0; 1161 unsigned long orig_jiffies = jiffies; 1162 struct imx_i2c_dma *dma = i2c_imx->dma; 1163 struct device *dev = &i2c_imx->adapter.dev; 1164 1165 i2c_imx->state = IMX_I2C_STATE_DMA; 1166 1167 dma->chan_using = dma->chan_tx; 1168 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 1169 dma->dma_data_dir = DMA_TO_DEVICE; 1170 dma->dma_len = msgs->len - 1; 1171 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1172 if (result) 1173 return result; 1174 1175 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1176 temp |= I2CR_DMAEN; 1177 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1178 1179 /* 1180 * Write slave address. 1181 * The first byte must be transmitted by the CPU. 1182 */ 1183 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1184 time_left = wait_for_completion_timeout( 1185 &i2c_imx->dma->cmd_complete, 1186 msecs_to_jiffies(DMA_TIMEOUT)); 1187 if (time_left == 0) { 1188 dmaengine_terminate_sync(dma->chan_using); 1189 return -ETIMEDOUT; 1190 } 1191 1192 /* Waiting for transfer complete. */ 1193 while (1) { 1194 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1195 if (temp & I2SR_ICF) 1196 break; 1197 if (time_after(jiffies, orig_jiffies + 1198 msecs_to_jiffies(DMA_TIMEOUT))) { 1199 dev_dbg(dev, "<%s> Timeout\n", __func__); 1200 return -ETIMEDOUT; 1201 } 1202 schedule(); 1203 } 1204 1205 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1206 temp &= ~I2CR_DMAEN; 1207 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1208 1209 /* The last data byte must be transferred by the CPU. */ 1210 imx_i2c_write_reg(msgs->buf[msgs->len-1], 1211 i2c_imx, IMX_I2C_I2DR); 1212 result = i2c_imx_trx_complete(i2c_imx, false); 1213 if (result) 1214 return result; 1215 1216 return i2c_imx_acked(i2c_imx); 1217} 1218 1219static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, 1220 struct i2c_msg *msgs, bool use_dma) 1221{ 1222 int result; 1223 unsigned int temp = 0; 1224 1225 /* write slave address */ 1226 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1227 result = i2c_imx_trx_complete(i2c_imx, !use_dma); 1228 if (result) 1229 return result; 1230 result = i2c_imx_acked(i2c_imx); 1231 if (result) 1232 return result; 1233 1234 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1235 1236 /* setup bus to read data */ 1237 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1238 temp &= ~I2CR_MTX; 1239 1240 /* 1241 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1242 * length is unknown 1243 */ 1244 if (msgs->len - 1) 1245 temp &= ~I2CR_TXAK; 1246 if (use_dma) 1247 temp |= I2CR_DMAEN; 1248 1249 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1250 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1251 1252 return 0; 1253} 1254 1255static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 1256 struct i2c_msg *msgs, bool is_lastmsg) 1257{ 1258 int result; 1259 unsigned long time_left; 1260 unsigned int temp; 1261 unsigned long orig_jiffies = jiffies; 1262 struct imx_i2c_dma *dma = i2c_imx->dma; 1263 struct device *dev = &i2c_imx->adapter.dev; 1264 1265 i2c_imx->state = IMX_I2C_STATE_DMA; 1266 1267 result = i2c_imx_prepare_read(i2c_imx, msgs, true); 1268 if (result) 1269 return result; 1270 1271 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1272 1273 dma->chan_using = dma->chan_rx; 1274 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 1275 dma->dma_data_dir = DMA_FROM_DEVICE; 1276 /* The last two data bytes must be transferred by the CPU. */ 1277 dma->dma_len = msgs->len - 2; 1278 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1279 if (result) 1280 return result; 1281 1282 time_left = wait_for_completion_timeout( 1283 &i2c_imx->dma->cmd_complete, 1284 msecs_to_jiffies(DMA_TIMEOUT)); 1285 if (time_left == 0) { 1286 dmaengine_terminate_sync(dma->chan_using); 1287 return -ETIMEDOUT; 1288 } 1289 1290 /* waiting for transfer complete. */ 1291 while (1) { 1292 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1293 if (temp & I2SR_ICF) 1294 break; 1295 if (time_after(jiffies, orig_jiffies + 1296 msecs_to_jiffies(DMA_TIMEOUT))) { 1297 dev_dbg(dev, "<%s> Timeout\n", __func__); 1298 return -ETIMEDOUT; 1299 } 1300 schedule(); 1301 } 1302 1303 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1304 temp &= ~I2CR_DMAEN; 1305 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1306 1307 /* read n-1 byte data */ 1308 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1309 temp |= I2CR_TXAK; 1310 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1311 1312 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1313 /* read n byte data */ 1314 result = i2c_imx_trx_complete(i2c_imx, false); 1315 if (result) 1316 return result; 1317 1318 if (is_lastmsg) { 1319 /* 1320 * It must generate STOP before read I2DR to prevent 1321 * controller from generating another clock cycle 1322 */ 1323 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1324 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1325 if (!(temp & I2CR_MSTA)) 1326 i2c_imx->stopped = 1; 1327 temp &= ~(I2CR_MSTA | I2CR_MTX); 1328 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1329 if (!i2c_imx->stopped) 1330 i2c_imx_bus_busy(i2c_imx, 0, false); 1331 } else { 1332 /* 1333 * For i2c master receiver repeat restart operation like: 1334 * read -> repeat MSTA -> read/write 1335 * The controller must set MTX before read the last byte in 1336 * the first read operation, otherwise the first read cost 1337 * one extra clock cycle. 1338 */ 1339 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1340 temp |= I2CR_MTX; 1341 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1342 } 1343 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1344 1345 return 0; 1346} 1347 1348static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, 1349 struct i2c_msg *msgs) 1350{ 1351 int i, result; 1352 1353 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1354 __func__, i2c_8bit_addr_from_msg(msgs)); 1355 1356 /* write slave address */ 1357 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1358 result = i2c_imx_trx_complete(i2c_imx, true); 1359 if (result) 1360 return result; 1361 result = i2c_imx_acked(i2c_imx); 1362 if (result) 1363 return result; 1364 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1365 1366 /* write data */ 1367 for (i = 0; i < msgs->len; i++) { 1368 dev_dbg(&i2c_imx->adapter.dev, 1369 "<%s> write byte: B%d=0x%X\n", 1370 __func__, i, msgs->buf[i]); 1371 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1372 result = i2c_imx_trx_complete(i2c_imx, true); 1373 if (result) 1374 return result; 1375 result = i2c_imx_acked(i2c_imx); 1376 if (result) 1377 return result; 1378 } 1379 return 0; 1380} 1381 1382static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 1383{ 1384 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1385 __func__, i2c_8bit_addr_from_msg(msgs)); 1386 1387 i2c_imx->state = IMX_I2C_STATE_WRITE; 1388 i2c_imx->msg = msgs; 1389 i2c_imx->msg_buf_idx = 0; 1390 1391 /* 1392 * By writing the device address we start the state machine in the ISR. 1393 * The ISR will report when it is done or when it fails. 1394 */ 1395 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1396 wait_event_timeout(i2c_imx->queue, 1397 i2c_imx->state == IMX_I2C_STATE_DONE || 1398 i2c_imx->state == IMX_I2C_STATE_FAILED, 1399 (msgs->len + 1) * HZ / 10); 1400 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1401 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", 1402 __func__, i2c_imx->isr_result); 1403 return i2c_imx->isr_result; 1404 } 1405 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1406 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); 1407 return -ETIMEDOUT; 1408 } 1409 return 0; 1410} 1411 1412static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, 1413 struct i2c_msg *msgs, bool is_lastmsg) 1414{ 1415 int i, result; 1416 unsigned int temp; 1417 int block_data = msgs->flags & I2C_M_RECV_LEN; 1418 1419 result = i2c_imx_prepare_read(i2c_imx, msgs, false); 1420 if (result) 1421 return result; 1422 1423 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1424 1425 /* read data */ 1426 for (i = 0; i < msgs->len; i++) { 1427 u8 len = 0; 1428 1429 result = i2c_imx_trx_complete(i2c_imx, true); 1430 if (result) 1431 return result; 1432 /* 1433 * First byte is the length of remaining packet 1434 * in the SMBus block data read. Add it to 1435 * msgs->len. 1436 */ 1437 if ((!i) && block_data) { 1438 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1439 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1440 return -EPROTO; 1441 dev_dbg(&i2c_imx->adapter.dev, 1442 "<%s> read length: 0x%X\n", 1443 __func__, len); 1444 msgs->len += len; 1445 } 1446 if (i == (msgs->len - 1)) { 1447 if (is_lastmsg) { 1448 /* 1449 * It must generate STOP before read I2DR to prevent 1450 * controller from generating another clock cycle 1451 */ 1452 dev_dbg(&i2c_imx->adapter.dev, 1453 "<%s> clear MSTA\n", __func__); 1454 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1455 if (!(temp & I2CR_MSTA)) 1456 i2c_imx->stopped = 1; 1457 temp &= ~(I2CR_MSTA | I2CR_MTX); 1458 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1459 if (!i2c_imx->stopped) 1460 i2c_imx_bus_busy(i2c_imx, 0, true); 1461 } else { 1462 /* 1463 * For i2c master receiver repeat restart operation like: 1464 * read -> repeat MSTA -> read/write 1465 * The controller must set MTX before read the last byte in 1466 * the first read operation, otherwise the first read cost 1467 * one extra clock cycle. 1468 */ 1469 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1470 temp |= I2CR_MTX; 1471 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1472 } 1473 } else if (i == (msgs->len - 2)) { 1474 dev_dbg(&i2c_imx->adapter.dev, 1475 "<%s> set TXAK\n", __func__); 1476 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1477 temp |= I2CR_TXAK; 1478 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1479 } 1480 if ((!i) && block_data) 1481 msgs->buf[0] = len; 1482 else 1483 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1484 dev_dbg(&i2c_imx->adapter.dev, 1485 "<%s> read byte: B%d=0x%X\n", 1486 __func__, i, msgs->buf[i]); 1487 } 1488 return 0; 1489} 1490 1491static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1492 bool is_lastmsg) 1493{ 1494 int block_data = msgs->flags & I2C_M_RECV_LEN; 1495 int ret = 0; 1496 1497 dev_dbg(&i2c_imx->adapter.dev, 1498 "<%s> write slave address: addr=0x%x\n", 1499 __func__, i2c_8bit_addr_from_msg(msgs)); 1500 1501 i2c_imx->is_lastmsg = is_lastmsg; 1502 1503 if (block_data) 1504 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA; 1505 else 1506 i2c_imx->state = IMX_I2C_STATE_READ; 1507 i2c_imx->msg = msgs; 1508 i2c_imx->msg_buf_idx = 0; 1509 1510 /* 1511 * By writing the device address we start the state machine in the ISR. 1512 * The ISR will report when it is done or when it fails. 1513 */ 1514 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1515 wait_event_timeout(i2c_imx->queue, 1516 i2c_imx->state == IMX_I2C_STATE_DONE || 1517 i2c_imx->state == IMX_I2C_STATE_FAILED, 1518 (msgs->len + 1) * HZ / 10); 1519 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1520 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", 1521 __func__, i2c_imx->isr_result); 1522 return i2c_imx->isr_result; 1523 } 1524 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1525 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); 1526 return -ETIMEDOUT; 1527 } 1528 if (i2c_imx->is_lastmsg) { 1529 if (!i2c_imx->stopped) 1530 ret = i2c_imx_bus_busy(i2c_imx, 0, false); 1531 /* 1532 * Only read the last byte of the last message after the bus is 1533 * not busy. Else the controller generates another clock which 1534 * might confuse devices. 1535 */ 1536 if (!ret) 1537 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, 1538 IMX_I2C_I2DR); 1539 } 1540 1541 return ret; 1542} 1543 1544static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1545 struct i2c_msg *msgs, int num, bool atomic) 1546{ 1547 unsigned int i, temp; 1548 int result; 1549 bool is_lastmsg = false; 1550 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1551 int use_dma = 0; 1552 1553 /* Start I2C transfer */ 1554 result = i2c_imx_start(i2c_imx, atomic); 1555 if (result) { 1556 /* 1557 * Bus recovery uses gpiod_get_value_cansleep() which is not 1558 * allowed within atomic context. 1559 */ 1560 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1561 i2c_recover_bus(&i2c_imx->adapter); 1562 result = i2c_imx_start(i2c_imx, atomic); 1563 } 1564 } 1565 1566 if (result) 1567 goto fail0; 1568 1569 /* read/write data */ 1570 for (i = 0; i < num; i++) { 1571 if (i == num - 1) 1572 is_lastmsg = true; 1573 1574 if (i) { 1575 dev_dbg(&i2c_imx->adapter.dev, 1576 "<%s> repeated start\n", __func__); 1577 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1578 temp |= I2CR_RSTA; 1579 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1580 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1581 if (result) 1582 goto fail0; 1583 } 1584 dev_dbg(&i2c_imx->adapter.dev, 1585 "<%s> transfer message: %d\n", __func__, i); 1586 /* write/read data */ 1587#ifdef CONFIG_I2C_DEBUG_BUS 1588 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1589 dev_dbg(&i2c_imx->adapter.dev, 1590 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1591 __func__, 1592 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1593 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1594 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1595 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1596 dev_dbg(&i2c_imx->adapter.dev, 1597 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1598 __func__, 1599 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1600 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1601 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1602 (temp & I2SR_RXAK ? 1 : 0)); 1603#endif 1604 1605 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1606 msgs[i].flags & I2C_M_DMA_SAFE; 1607 if (msgs[i].flags & I2C_M_RD) { 1608 int block_data = msgs->flags & I2C_M_RECV_LEN; 1609 1610 if (atomic) 1611 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); 1612 else if (use_dma && !block_data) 1613 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); 1614 else 1615 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 1616 } else { 1617 if (atomic) 1618 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]); 1619 else if (use_dma) 1620 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1621 else 1622 result = i2c_imx_write(i2c_imx, &msgs[i]); 1623 } 1624 if (result) 1625 goto fail0; 1626 } 1627 1628fail0: 1629 /* Stop I2C transfer */ 1630 i2c_imx_stop(i2c_imx, atomic); 1631 1632 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1633 (result < 0) ? "error" : "success msg", 1634 (result < 0) ? result : num); 1635 /* After data is transferred, switch to slave mode(as a receiver) */ 1636 if (i2c_imx->slave) 1637 i2c_imx_slave_init(i2c_imx); 1638 1639 return (result < 0) ? result : num; 1640} 1641 1642static int i2c_imx_xfer(struct i2c_adapter *adapter, 1643 struct i2c_msg *msgs, int num) 1644{ 1645 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1646 int result; 1647 1648 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1649 if (result < 0) 1650 return result; 1651 1652 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1653 1654 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1655 1656 return result; 1657} 1658 1659static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1660 struct i2c_msg *msgs, int num) 1661{ 1662 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1663 int result; 1664 1665 result = clk_enable(i2c_imx->clk); 1666 if (result) 1667 return result; 1668 1669 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1670 1671 clk_disable(i2c_imx->clk); 1672 1673 return result; 1674} 1675 1676/* 1677 * We switch SCL and SDA to their GPIO function and do some bitbanging 1678 * for bus recovery. These alternative pinmux settings can be 1679 * described in the device tree by a separate pinctrl state "gpio". If 1680 * this is missing this is not a big problem, the only implication is 1681 * that we can't do bus recovery. 1682 */ 1683static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1684 struct platform_device *pdev) 1685{ 1686 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo; 1687 1688 bri->pinctrl = devm_pinctrl_get(&pdev->dev); 1689 if (IS_ERR(bri->pinctrl)) 1690 return PTR_ERR(bri->pinctrl); 1691 1692 i2c_imx->adapter.bus_recovery_info = bri; 1693 1694 return 0; 1695} 1696 1697static u32 i2c_imx_func(struct i2c_adapter *adapter) 1698{ 1699 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1700 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1701} 1702 1703static const struct i2c_algorithm i2c_imx_algo = { 1704 .xfer = i2c_imx_xfer, 1705 .xfer_atomic = i2c_imx_xfer_atomic, 1706 .functionality = i2c_imx_func, 1707 .reg_slave = i2c_imx_reg_slave, 1708 .unreg_slave = i2c_imx_unreg_slave, 1709}; 1710 1711static int i2c_imx_probe(struct platform_device *pdev) 1712{ 1713 struct imx_i2c_struct *i2c_imx; 1714 struct resource *res; 1715 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1716 void __iomem *base; 1717 int irq, ret; 1718 dma_addr_t phy_addr; 1719 const struct imx_i2c_hwdata *match; 1720 1721 irq = platform_get_irq(pdev, 0); 1722 if (irq < 0) 1723 return dev_err_probe(&pdev->dev, irq, "can't get IRQ\n"); 1724 1725 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1726 if (IS_ERR(base)) 1727 return dev_err_probe(&pdev->dev, PTR_ERR(base), "can't get IO memory\n"); 1728 1729 phy_addr = (dma_addr_t)res->start; 1730 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1731 if (!i2c_imx) 1732 return -ENOMEM; 1733 1734 spin_lock_init(&i2c_imx->slave_lock); 1735 hrtimer_setup(&i2c_imx->slave_timer, i2c_imx_slave_timeout, CLOCK_MONOTONIC, 1736 HRTIMER_MODE_ABS); 1737 1738 match = device_get_match_data(&pdev->dev); 1739 if (match) 1740 i2c_imx->hwdata = match; 1741 else 1742 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1743 platform_get_device_id(pdev)->driver_data; 1744 1745 /* Setup i2c_imx driver structure */ 1746 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1747 i2c_imx->adapter.owner = THIS_MODULE; 1748 i2c_imx->adapter.algo = &i2c_imx_algo; 1749 i2c_imx->adapter.dev.parent = &pdev->dev; 1750 i2c_imx->adapter.nr = pdev->id; 1751 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1752 i2c_imx->base = base; 1753 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1754 1755 /* Get I2C clock */ 1756 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1757 if (IS_ERR(i2c_imx->clk)) 1758 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1759 "can't get I2C clock\n"); 1760 1761 /* Init queue */ 1762 init_waitqueue_head(&i2c_imx->queue); 1763 1764 /* Set up adapter data */ 1765 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1766 1767 /* Set up platform driver data */ 1768 platform_set_drvdata(pdev, i2c_imx); 1769 1770 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1771 pm_runtime_use_autosuspend(&pdev->dev); 1772 pm_runtime_set_active(&pdev->dev); 1773 pm_runtime_enable(&pdev->dev); 1774 1775 ret = pm_runtime_get_sync(&pdev->dev); 1776 if (ret < 0) 1777 goto rpm_disable; 1778 1779 /* Request IRQ */ 1780 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED | IRQF_NO_SUSPEND, 1781 pdev->name, i2c_imx); 1782 if (ret) { 1783 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1784 goto rpm_disable; 1785 } 1786 1787 /* 1788 * We use the single-master property for backward compatibility. 1789 * By default multi master mode is enabled. 1790 */ 1791 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master"); 1792 1793 /* Set up clock divider */ 1794 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1795 ret = of_property_read_u32(pdev->dev.of_node, 1796 "clock-frequency", &i2c_imx->bitrate); 1797 if (ret < 0 && pdata && pdata->bitrate) 1798 i2c_imx->bitrate = pdata->bitrate; 1799 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1800 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1801 ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1802 if (ret < 0) { 1803 dev_err(&pdev->dev, "can't get I2C clock\n"); 1804 goto clk_notifier_unregister; 1805 } 1806 1807 i2c_imx_reset_regs(i2c_imx); 1808 1809 /* Init optional bus recovery function */ 1810 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1811 /* Give it another chance if pinctrl used is not ready yet */ 1812 if (ret == -EPROBE_DEFER) 1813 goto clk_notifier_unregister; 1814 1815 /* 1816 * DMA mode should be optional for I2C, when encountering DMA errors, 1817 * no need to exit I2C probe. Only print warning to show DMA error and 1818 * use PIO mode directly to ensure I2C bus available as much as possible. 1819 */ 1820 ret = i2c_imx_dma_request(i2c_imx, phy_addr); 1821 if (ret) { 1822 if (ret == -EPROBE_DEFER) { 1823 dev_err_probe(&pdev->dev, ret, "can't get DMA channels\n"); 1824 goto clk_notifier_unregister; 1825 } else if (ret == -ENODEV) { 1826 dev_dbg(&pdev->dev, "Only use PIO mode\n"); 1827 } else { 1828 dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n", 1829 ERR_PTR(ret)); 1830 } 1831 } 1832 1833 /* Add I2C adapter */ 1834 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1835 if (ret < 0) 1836 goto clk_notifier_unregister; 1837 1838 pm_runtime_put_autosuspend(&pdev->dev); 1839 1840 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1841 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1842 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1843 i2c_imx->adapter.name); 1844 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1845 1846 return 0; /* Return OK */ 1847 1848clk_notifier_unregister: 1849 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1850 free_irq(irq, i2c_imx); 1851rpm_disable: 1852 pm_runtime_put_noidle(&pdev->dev); 1853 pm_runtime_disable(&pdev->dev); 1854 pm_runtime_set_suspended(&pdev->dev); 1855 pm_runtime_dont_use_autosuspend(&pdev->dev); 1856 return ret; 1857} 1858 1859static void i2c_imx_remove(struct platform_device *pdev) 1860{ 1861 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1862 int irq, ret; 1863 1864 ret = pm_runtime_get_sync(&pdev->dev); 1865 1866 hrtimer_cancel(&i2c_imx->slave_timer); 1867 1868 /* remove adapter */ 1869 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1870 i2c_del_adapter(&i2c_imx->adapter); 1871 1872 if (i2c_imx->dma) 1873 i2c_imx_dma_free(i2c_imx); 1874 1875 if (ret >= 0) { 1876 /* setup chip registers to defaults */ 1877 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1878 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1879 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1880 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1881 } 1882 1883 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1884 irq = platform_get_irq(pdev, 0); 1885 if (irq >= 0) 1886 free_irq(irq, i2c_imx); 1887 1888 pm_runtime_put_noidle(&pdev->dev); 1889 pm_runtime_disable(&pdev->dev); 1890} 1891 1892static int i2c_imx_runtime_suspend(struct device *dev) 1893{ 1894 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1895 1896 clk_disable(i2c_imx->clk); 1897 return pinctrl_pm_select_sleep_state(dev); 1898} 1899 1900static int i2c_imx_runtime_resume(struct device *dev) 1901{ 1902 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1903 int ret; 1904 1905 ret = pinctrl_pm_select_default_state(dev); 1906 if (ret) 1907 return ret; 1908 1909 ret = clk_enable(i2c_imx->clk); 1910 if (ret) 1911 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1912 1913 return ret; 1914} 1915 1916static int i2c_imx_suspend(struct device *dev) 1917{ 1918 /* 1919 * Some I2C devices may need the I2C controller to remain active 1920 * during resume_noirq() or suspend_noirq(). If the controller is 1921 * autosuspended, there is no way to wake it up once runtime PM is 1922 * disabled (in suspend_late()). 1923 * 1924 * During system resume, the I2C controller will be available only 1925 * after runtime PM is re-enabled (in resume_early()). However, this 1926 * may be too late for some devices. 1927 * 1928 * Wake up the controller in the suspend() callback while runtime PM 1929 * is still enabled. The I2C controller will remain available until 1930 * the suspend_noirq() callback (pm_runtime_force_suspend()) is 1931 * called. During resume, the I2C controller can be restored by the 1932 * resume_noirq() callback (pm_runtime_force_resume()). 1933 * 1934 * Finally, the resume() callback re-enables autosuspend, ensuring 1935 * the I2C controller remains available until the system enters 1936 * suspend_noirq() and from resume_noirq(). 1937 */ 1938 return pm_runtime_resume_and_get(dev); 1939} 1940 1941static int i2c_imx_resume(struct device *dev) 1942{ 1943 pm_runtime_put_autosuspend(dev); 1944 1945 return 0; 1946} 1947 1948static const struct dev_pm_ops i2c_imx_pm_ops = { 1949 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1950 pm_runtime_force_resume) 1951 SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume) 1952 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 1953}; 1954 1955static struct platform_driver i2c_imx_driver = { 1956 .probe = i2c_imx_probe, 1957 .remove = i2c_imx_remove, 1958 .driver = { 1959 .name = DRIVER_NAME, 1960 .pm = pm_ptr(&i2c_imx_pm_ops), 1961 .of_match_table = i2c_imx_dt_ids, 1962 .acpi_match_table = i2c_imx_acpi_ids, 1963 }, 1964 .id_table = imx_i2c_devtype, 1965}; 1966 1967static int __init i2c_adap_imx_init(void) 1968{ 1969 return platform_driver_register(&i2c_imx_driver); 1970} 1971subsys_initcall(i2c_adap_imx_init); 1972 1973static void __exit i2c_adap_imx_exit(void) 1974{ 1975 platform_driver_unregister(&i2c_imx_driver); 1976} 1977module_exit(i2c_adap_imx_exit); 1978 1979MODULE_LICENSE("GPL"); 1980MODULE_AUTHOR("Darius Augulis"); 1981MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1982MODULE_ALIAS("platform:" DRIVER_NAME);
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