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i2c-i801.c
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linux-6.19.14/drivers/i2c/busses/i2c-i801.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10*/ 11 12/* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes 84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes 85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes 86 * Wildcat Lake-U (SOC) 0x4d22 32 hard yes yes yes 87 * Diamond Rapids (SOC) 0x5827 32 hard yes yes yes 88 * Nova Lake-S (PCH) 0x6e23 32 hard yes yes yes 89 * 90 * Features supported by this driver: 91 * Software PEC no 92 * Hardware PEC yes 93 * Block buffer yes 94 * Block process call transaction yes 95 * I2C block read transaction yes (doesn't use the block buffer) 96 * Target mode no 97 * SMBus Host Notify yes 98 * Interrupt processing yes 99 * 100 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 101 */ 102 103#define DRV_NAME "i801_smbus" 104 105#include <linux/interrupt.h> 106#include <linux/module.h> 107#include <linux/pci.h> 108#include <linux/kernel.h> 109#include <linux/stddef.h> 110#include <linux/delay.h> 111#include <linux/ioport.h> 112#include <linux/init.h> 113#include <linux/i2c.h> 114#include <linux/i2c-mux.h> 115#include <linux/i2c-smbus.h> 116#include <linux/acpi.h> 117#include <linux/io.h> 118#include <linux/dmi.h> 119#include <linux/slab.h> 120#include <linux/string.h> 121#include <linux/completion.h> 122#include <linux/err.h> 123#include <linux/platform_device.h> 124#include <linux/platform_data/itco_wdt.h> 125#include <linux/platform_data/x86/p2sb.h> 126#include <linux/pm_runtime.h> 127#include <linux/mutex.h> 128 129#ifdef CONFIG_I2C_I801_MUX 130#include <linux/gpio/machine.h> 131#include <linux/platform_data/i2c-mux-gpio.h> 132#endif 133 134/* I801 SMBus address offsets */ 135#define SMBHSTSTS(p) (0 + (p)->smba) 136#define SMBHSTCNT(p) (2 + (p)->smba) 137#define SMBHSTCMD(p) (3 + (p)->smba) 138#define SMBHSTADD(p) (4 + (p)->smba) 139#define SMBHSTDAT0(p) (5 + (p)->smba) 140#define SMBHSTDAT1(p) (6 + (p)->smba) 141#define SMBBLKDAT(p) (7 + (p)->smba) 142#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 143#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 144#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 145#define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 146#define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 147#define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 148 149/* PCI Address Constants */ 150#define SMBBAR_MMIO 0 151#define SMBBAR 4 152#define SMBHSTCFG 0x040 153#define TCOBASE 0x050 154#define TCOCTL 0x054 155 156#define SBREG_SMBCTRL 0xc6000c 157#define SBREG_SMBCTRL_DNV 0xcf000c 158 159/* Host configuration bits for SMBHSTCFG */ 160#define SMBHSTCFG_HST_EN BIT(0) 161#define SMBHSTCFG_SMB_SMI_EN BIT(1) 162#define SMBHSTCFG_I2C_EN BIT(2) 163#define SMBHSTCFG_SPD_WD BIT(4) 164 165/* TCO configuration bits for TCOCTL */ 166#define TCOCTL_EN BIT(8) 167 168/* Auxiliary status register bits, ICH4+ only */ 169#define SMBAUXSTS_CRCE BIT(0) 170#define SMBAUXSTS_STCO BIT(1) 171 172/* Auxiliary control register bits, ICH4+ only */ 173#define SMBAUXCTL_CRC BIT(0) 174#define SMBAUXCTL_E32B BIT(1) 175 176/* I801 command constants */ 177#define I801_QUICK 0x00 178#define I801_BYTE 0x04 179#define I801_BYTE_DATA 0x08 180#define I801_WORD_DATA 0x0C 181#define I801_PROC_CALL 0x10 182#define I801_BLOCK_DATA 0x14 183#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 184#define I801_BLOCK_PROC_CALL 0x1C 185 186/* I801 Host Control register bits */ 187#define SMBHSTCNT_INTREN BIT(0) 188#define SMBHSTCNT_KILL BIT(1) 189#define SMBHSTCNT_LAST_BYTE BIT(5) 190#define SMBHSTCNT_START BIT(6) 191#define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 192 193/* I801 Hosts Status register bits */ 194#define SMBHSTSTS_BYTE_DONE BIT(7) 195#define SMBHSTSTS_INUSE_STS BIT(6) 196#define SMBHSTSTS_SMBALERT_STS BIT(5) 197#define SMBHSTSTS_FAILED BIT(4) 198#define SMBHSTSTS_BUS_ERR BIT(3) 199#define SMBHSTSTS_DEV_ERR BIT(2) 200#define SMBHSTSTS_INTR BIT(1) 201#define SMBHSTSTS_HOST_BUSY BIT(0) 202 203/* Host Notify Status register bits */ 204#define SMBSLVSTS_HST_NTFY_STS BIT(0) 205 206/* Host Notify Command register bits */ 207#define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 208#define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 209 210#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 211 SMBHSTSTS_DEV_ERR) 212 213#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 214 STATUS_ERROR_FLAGS) 215 216#define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1) 217 218/* Older devices have their ID defined in <linux/pci_ids.h> */ 219#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 220#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 221#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 222#define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 223#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 224#define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 225#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 226#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 227/* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 228#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 229#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 230#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 231#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 232#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 233#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 234#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 235#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 236#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 237#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 238#define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 239#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 240#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 241#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 242#define PCI_DEVICE_ID_INTEL_WILDCAT_LAKE_U_SMBUS 0x4d22 243#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 244#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 245#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 246#define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 247#define PCI_DEVICE_ID_INTEL_DIAMOND_RAPIDS_SMBUS 0x5827 248#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 249#define PCI_DEVICE_ID_INTEL_NOVA_LAKE_S_SMBUS 0x6e23 250#define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722 251#define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 252#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 253#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 254#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 255#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 256#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 257#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 258#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 259#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 260#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 261#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 262#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 263#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 264#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 265#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 266#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 267#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 268#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 269#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 270#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 271#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 272#define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 273#define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322 274#define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422 275 276struct i801_mux_config { 277 char *gpio_chip; 278 unsigned values[3]; 279 int n_values; 280 unsigned gpios[2]; /* Relative to gpio_chip->base */ 281 int n_gpios; 282}; 283 284struct i801_priv { 285 struct i2c_adapter adapter; 286 void __iomem *smba; 287 unsigned char original_hstcfg; 288 unsigned char original_hstcnt; 289 unsigned char original_slvcmd; 290 struct pci_dev *pci_dev; 291 unsigned int features; 292 293 /* isr processing */ 294 struct completion done; 295 u8 status; 296 297 /* Command state used by isr for byte-by-byte block transactions */ 298 u8 cmd; 299 bool is_read; 300 int count; 301 int len; 302 u8 *data; 303 304#ifdef CONFIG_I2C_I801_MUX 305 struct platform_device *mux_pdev; 306 struct gpiod_lookup_table *lookup; 307 struct notifier_block mux_notifier_block; 308#endif 309 struct platform_device *tco_pdev; 310 311 /* 312 * If set to true the host controller registers are reserved for 313 * ACPI AML use. Needs extra protection by acpi_lock. 314 */ 315 bool acpi_reserved; 316 struct mutex acpi_lock; 317}; 318 319#define FEATURE_SMBUS_PEC BIT(0) 320#define FEATURE_BLOCK_BUFFER BIT(1) 321#define FEATURE_BLOCK_PROC BIT(2) 322#define FEATURE_I2C_BLOCK_READ BIT(3) 323#define FEATURE_IRQ BIT(4) 324#define FEATURE_HOST_NOTIFY BIT(5) 325/* Not really a feature, but it's convenient to handle it as such */ 326#define FEATURE_IDF BIT(15) 327#define FEATURE_TCO_SPT BIT(16) 328#define FEATURE_TCO_CNL BIT(17) 329 330static const char *i801_feature_names[] = { 331 "SMBus PEC", 332 "Block buffer", 333 "Block process call", 334 "I2C block read", 335 "Interrupt", 336 "SMBus Host Notify", 337}; 338 339static unsigned int disable_features; 340module_param(disable_features, uint, S_IRUGO | S_IWUSR); 341MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 342 "\t\t 0x01 disable SMBus PEC\n" 343 "\t\t 0x02 disable the block buffer\n" 344 "\t\t 0x08 disable the I2C block read functionality\n" 345 "\t\t 0x10 don't use interrupts\n" 346 "\t\t 0x20 disable SMBus Host Notify "); 347 348/* Wait for BUSY being cleared and either INTR or an error flag being set */ 349static int i801_wait_intr(struct i801_priv *priv) 350{ 351 unsigned long timeout = jiffies + priv->adapter.timeout; 352 int status, busy; 353 354 do { 355 usleep_range(250, 500); 356 status = ioread8(SMBHSTSTS(priv)); 357 busy = status & SMBHSTSTS_HOST_BUSY; 358 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 359 if (!busy && status) 360 return status & STATUS_ERROR_FLAGS; 361 } while (time_is_after_eq_jiffies(timeout)); 362 363 return -ETIMEDOUT; 364} 365 366/* Wait for either BYTE_DONE or an error flag being set */ 367static int i801_wait_byte_done(struct i801_priv *priv) 368{ 369 unsigned long timeout = jiffies + priv->adapter.timeout; 370 int status; 371 372 do { 373 usleep_range(250, 500); 374 status = ioread8(SMBHSTSTS(priv)); 375 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 376 return status & STATUS_ERROR_FLAGS; 377 } while (time_is_after_eq_jiffies(timeout)); 378 379 return -ETIMEDOUT; 380} 381 382static int i801_get_block_len(struct i801_priv *priv) 383{ 384 u8 len = ioread8(SMBHSTDAT0(priv)); 385 386 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 387 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len); 388 return -EPROTO; 389 } 390 391 return len; 392} 393 394static int i801_check_and_clear_pec_error(struct i801_priv *priv) 395{ 396 u8 status; 397 398 if (!(priv->features & FEATURE_SMBUS_PEC)) 399 return 0; 400 401 status = ioread8(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 402 if (status) { 403 iowrite8(status, SMBAUXSTS(priv)); 404 return -EBADMSG; 405 } 406 407 return 0; 408} 409 410/* Make sure the SMBus host is ready to start transmitting. 411 Return 0 if it is, -EBUSY if it is not. */ 412static int i801_check_pre(struct i801_priv *priv) 413{ 414 int status, result; 415 416 status = ioread8(SMBHSTSTS(priv)); 417 if (status & SMBHSTSTS_HOST_BUSY) { 418 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 419 return -EBUSY; 420 } 421 422 status &= STATUS_FLAGS; 423 if (status) { 424 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 425 iowrite8(status, SMBHSTSTS(priv)); 426 } 427 428 /* 429 * Clear CRC status if needed. 430 * During normal operation, i801_check_post() takes care 431 * of it after every operation. We do it here only in case 432 * the hardware was already in this state when the driver 433 * started. 434 */ 435 result = i801_check_and_clear_pec_error(priv); 436 if (result) 437 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n"); 438 439 return 0; 440} 441 442static int i801_check_post(struct i801_priv *priv, int status) 443{ 444 int result = 0; 445 446 /* 447 * If the SMBus is still busy, we give up 448 */ 449 if (unlikely(status < 0)) { 450 /* try to stop the current command */ 451 iowrite8(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 452 status = i801_wait_intr(priv); 453 iowrite8(0, SMBHSTCNT(priv)); 454 455 /* Check if it worked */ 456 if (status < 0 || !(status & SMBHSTSTS_FAILED)) 457 pci_dbg(priv->pci_dev, "Failed terminating the transaction\n"); 458 return -ETIMEDOUT; 459 } 460 461 if (status & SMBHSTSTS_FAILED) { 462 result = -EIO; 463 pci_err(priv->pci_dev, "Transaction failed\n"); 464 } 465 if (status & SMBHSTSTS_DEV_ERR) { 466 /* 467 * This may be a PEC error, check and clear it. 468 * 469 * AUXSTS is handled differently from HSTSTS. 470 * For HSTSTS, i801_isr() or i801_wait_intr() 471 * has already cleared the error bits in hardware, 472 * and we are passed a copy of the original value 473 * in "status". 474 * For AUXSTS, the hardware register is left 475 * for us to handle here. 476 * This is asymmetric, slightly iffy, but safe, 477 * since all this code is serialized and the CRCE 478 * bit is harmless as long as it's cleared before 479 * the next operation. 480 */ 481 result = i801_check_and_clear_pec_error(priv); 482 if (result) { 483 pci_dbg(priv->pci_dev, "PEC error\n"); 484 } else { 485 result = -ENXIO; 486 pci_dbg(priv->pci_dev, "No response\n"); 487 } 488 } 489 if (status & SMBHSTSTS_BUS_ERR) { 490 result = -EAGAIN; 491 pci_dbg(priv->pci_dev, "Lost arbitration\n"); 492 } 493 494 return result; 495} 496 497static int i801_transaction(struct i801_priv *priv, int xact) 498{ 499 unsigned long result; 500 const struct i2c_adapter *adap = &priv->adapter; 501 502 if (priv->features & FEATURE_IRQ) { 503 reinit_completion(&priv->done); 504 iowrite8(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 505 SMBHSTCNT(priv)); 506 result = wait_for_completion_timeout(&priv->done, adap->timeout); 507 return result ? priv->status : -ETIMEDOUT; 508 } 509 510 iowrite8(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 511 512 return i801_wait_intr(priv); 513} 514 515static int i801_block_transaction_by_block(struct i801_priv *priv, 516 union i2c_smbus_data *data, 517 char read_write, int command) 518{ 519 int len, status, xact; 520 521 switch (command) { 522 case I2C_SMBUS_BLOCK_PROC_CALL: 523 xact = I801_BLOCK_PROC_CALL; 524 break; 525 case I2C_SMBUS_BLOCK_DATA: 526 xact = I801_BLOCK_DATA; 527 break; 528 default: 529 return -EOPNOTSUPP; 530 } 531 532 /* Set block buffer mode */ 533 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 534 535 if (read_write == I2C_SMBUS_WRITE) { 536 len = data->block[0]; 537 iowrite8(len, SMBHSTDAT0(priv)); 538 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */ 539 iowrite8_rep(SMBBLKDAT(priv), data->block + 1, len); 540 } 541 542 status = i801_transaction(priv, xact); 543 if (status) 544 goto out; 545 546 if (read_write == I2C_SMBUS_READ || 547 command == I2C_SMBUS_BLOCK_PROC_CALL) { 548 len = i801_get_block_len(priv); 549 if (len < 0) { 550 status = len; 551 goto out; 552 } 553 554 data->block[0] = len; 555 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */ 556 ioread8_rep(SMBBLKDAT(priv), data->block + 1, len); 557 } 558out: 559 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 560 return status; 561} 562 563static void i801_isr_byte_done(struct i801_priv *priv) 564{ 565 if (priv->is_read) { 566 /* 567 * At transfer start i801_smbus_block_transaction() marks 568 * the block length as invalid. Check for this sentinel value 569 * and read the block length from SMBHSTDAT0. 570 */ 571 if (priv->len == SMBUS_LEN_SENTINEL) { 572 priv->len = i801_get_block_len(priv); 573 if (priv->len < 0) 574 /* FIXME: Recover */ 575 priv->len = I2C_SMBUS_BLOCK_MAX; 576 577 priv->data[-1] = priv->len; 578 } 579 580 /* Read next byte */ 581 if (priv->count < priv->len) 582 priv->data[priv->count++] = ioread8(SMBBLKDAT(priv)); 583 else 584 pci_dbg(priv->pci_dev, "Discarding extra byte on block read\n"); 585 586 /* Set LAST_BYTE for last byte of read transaction */ 587 if (priv->count == priv->len - 1) 588 iowrite8(priv->cmd | SMBHSTCNT_LAST_BYTE, 589 SMBHSTCNT(priv)); 590 } else if (priv->count < priv->len - 1) { 591 /* Write next byte, except for IRQ after last byte */ 592 iowrite8(priv->data[++priv->count], SMBBLKDAT(priv)); 593 } 594} 595 596static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 597{ 598 unsigned short addr; 599 600 addr = ioread8(SMBNTFDADD(priv)) >> 1; 601 602 /* 603 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 604 * always returns 0. Our current implementation doesn't provide 605 * data, so we just ignore it. 606 */ 607 i2c_handle_smbus_host_notify(&priv->adapter, addr); 608 609 /* clear Host Notify bit and return */ 610 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 611 return IRQ_HANDLED; 612} 613 614/* 615 * There are three kinds of interrupts: 616 * 617 * 1) i801 signals transaction completion with one of these interrupts: 618 * INTR - Success 619 * DEV_ERR - Invalid command, NAK or communication timeout 620 * BUS_ERR - SMI# transaction collision 621 * FAILED - transaction was canceled due to a KILL request 622 * When any of these occur, update ->status and signal completion. 623 * 624 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 625 * occurs for each byte of a byte-by-byte to prepare the next byte. 626 * 627 * 3) Host Notify interrupts 628 */ 629static irqreturn_t i801_isr(int irq, void *dev_id) 630{ 631 struct i801_priv *priv = dev_id; 632 u16 pcists; 633 u8 status; 634 635 /* Confirm this is our interrupt */ 636 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 637 if (!(pcists & PCI_STATUS_INTERRUPT)) 638 return IRQ_NONE; 639 640 if (priv->features & FEATURE_HOST_NOTIFY) { 641 status = ioread8(SMBSLVSTS(priv)); 642 if (status & SMBSLVSTS_HST_NTFY_STS) 643 return i801_host_notify_isr(priv); 644 } 645 646 status = ioread8(SMBHSTSTS(priv)); 647 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 648 i801_isr_byte_done(priv); 649 650 /* 651 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 652 * independently of the interrupt generation being blocked or not 653 * so clear it always when the status is set. 654 */ 655 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 656 iowrite8(status, SMBHSTSTS(priv)); 657 658 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 659 if (status) { 660 priv->status = status & STATUS_ERROR_FLAGS; 661 complete(&priv->done); 662 } 663 664 return IRQ_HANDLED; 665} 666 667/* 668 * For "byte-by-byte" block transactions: 669 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 670 * I2C read uses cmd=I801_I2C_BLOCK_DATA 671 */ 672static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 673 union i2c_smbus_data *data, 674 char read_write, int command) 675{ 676 int i, len; 677 int smbcmd; 678 int status; 679 unsigned long result; 680 const struct i2c_adapter *adap = &priv->adapter; 681 682 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 683 return -EOPNOTSUPP; 684 685 len = data->block[0]; 686 687 if (read_write == I2C_SMBUS_WRITE) { 688 iowrite8(len, SMBHSTDAT0(priv)); 689 iowrite8(data->block[1], SMBBLKDAT(priv)); 690 } 691 692 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 693 read_write == I2C_SMBUS_READ) 694 smbcmd = I801_I2C_BLOCK_DATA; 695 else 696 smbcmd = I801_BLOCK_DATA; 697 698 if (priv->features & FEATURE_IRQ) { 699 priv->is_read = (read_write == I2C_SMBUS_READ); 700 if (len == 1 && priv->is_read) 701 smbcmd |= SMBHSTCNT_LAST_BYTE; 702 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 703 priv->len = len; 704 priv->count = 0; 705 priv->data = &data->block[1]; 706 707 reinit_completion(&priv->done); 708 iowrite8(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 709 result = wait_for_completion_timeout(&priv->done, adap->timeout); 710 return result ? priv->status : -ETIMEDOUT; 711 } 712 713 if (len == 1 && read_write == I2C_SMBUS_READ) 714 smbcmd |= SMBHSTCNT_LAST_BYTE; 715 iowrite8(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 716 717 for (i = 1; i <= len; i++) { 718 status = i801_wait_byte_done(priv); 719 if (status) 720 return status; 721 722 /* 723 * At transfer start i801_smbus_block_transaction() marks 724 * the block length as invalid. Check for this sentinel value 725 * and read the block length from SMBHSTDAT0. 726 */ 727 if (len == SMBUS_LEN_SENTINEL) { 728 len = i801_get_block_len(priv); 729 if (len < 0) { 730 /* Recover */ 731 while (ioread8(SMBHSTSTS(priv)) & 732 SMBHSTSTS_HOST_BUSY) 733 iowrite8(SMBHSTSTS_BYTE_DONE, 734 SMBHSTSTS(priv)); 735 iowrite8(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 736 return -EPROTO; 737 } 738 data->block[0] = len; 739 } 740 741 if (read_write == I2C_SMBUS_READ) { 742 data->block[i] = ioread8(SMBBLKDAT(priv)); 743 if (i == len - 1) 744 iowrite8(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 745 } 746 747 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 748 iowrite8(data->block[i+1], SMBBLKDAT(priv)); 749 750 /* signals SMBBLKDAT ready */ 751 iowrite8(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 752 } 753 754 return i801_wait_intr(priv); 755} 756 757static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 758{ 759 iowrite8((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 760} 761 762/* Single value transaction function */ 763static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 764 u8 addr, u8 hstcmd, char read_write, int command) 765{ 766 int xact, ret; 767 768 switch (command) { 769 case I2C_SMBUS_QUICK: 770 i801_set_hstadd(priv, addr, read_write); 771 xact = I801_QUICK; 772 break; 773 case I2C_SMBUS_BYTE: 774 i801_set_hstadd(priv, addr, read_write); 775 if (read_write == I2C_SMBUS_WRITE) 776 iowrite8(hstcmd, SMBHSTCMD(priv)); 777 xact = I801_BYTE; 778 break; 779 case I2C_SMBUS_BYTE_DATA: 780 i801_set_hstadd(priv, addr, read_write); 781 if (read_write == I2C_SMBUS_WRITE) 782 iowrite8(data->byte, SMBHSTDAT0(priv)); 783 iowrite8(hstcmd, SMBHSTCMD(priv)); 784 xact = I801_BYTE_DATA; 785 break; 786 case I2C_SMBUS_WORD_DATA: 787 i801_set_hstadd(priv, addr, read_write); 788 if (read_write == I2C_SMBUS_WRITE) { 789 iowrite8(data->word & 0xff, SMBHSTDAT0(priv)); 790 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 791 } 792 iowrite8(hstcmd, SMBHSTCMD(priv)); 793 xact = I801_WORD_DATA; 794 break; 795 case I2C_SMBUS_PROC_CALL: 796 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 797 iowrite8(data->word & 0xff, SMBHSTDAT0(priv)); 798 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 799 iowrite8(hstcmd, SMBHSTCMD(priv)); 800 read_write = I2C_SMBUS_READ; 801 xact = I801_PROC_CALL; 802 break; 803 default: 804 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 805 return -EOPNOTSUPP; 806 } 807 808 ret = i801_transaction(priv, xact); 809 if (ret || read_write == I2C_SMBUS_WRITE) 810 return ret; 811 812 switch (command) { 813 case I2C_SMBUS_BYTE: 814 case I2C_SMBUS_BYTE_DATA: 815 data->byte = ioread8(SMBHSTDAT0(priv)); 816 break; 817 case I2C_SMBUS_WORD_DATA: 818 case I2C_SMBUS_PROC_CALL: 819 data->word = ioread8(SMBHSTDAT0(priv)) + 820 (ioread8(SMBHSTDAT1(priv)) << 8); 821 break; 822 } 823 824 return 0; 825} 826 827static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 828 u8 addr, u8 hstcmd, char read_write, int command) 829{ 830 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 831 /* Mark block length as invalid */ 832 data->block[0] = SMBUS_LEN_SENTINEL; 833 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 834 return -EPROTO; 835 836 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 837 /* Needs to be flagged as write transaction */ 838 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 839 else 840 i801_set_hstadd(priv, addr, read_write); 841 iowrite8(hstcmd, SMBHSTCMD(priv)); 842 843 if (priv->features & FEATURE_BLOCK_BUFFER) 844 return i801_block_transaction_by_block(priv, data, read_write, command); 845 else 846 return i801_block_transaction_byte_by_byte(priv, data, read_write, command); 847} 848 849static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 850 u8 addr, u8 hstcmd, char read_write, int command) 851{ 852 int result; 853 u8 hostc; 854 855 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 856 return -EPROTO; 857 /* 858 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here, 859 * even when reading. However if SPD Write Disable is set (Lynx Point and later), 860 * the read will fail if we don't set the R/#W bit. 861 */ 862 i801_set_hstadd(priv, addr, 863 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE); 864 865 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */ 866 if (read_write == I2C_SMBUS_READ) 867 iowrite8(hstcmd, SMBHSTDAT1(priv)); 868 else 869 iowrite8(hstcmd, SMBHSTCMD(priv)); 870 871 if (read_write == I2C_SMBUS_WRITE) { 872 /* set I2C_EN bit in configuration register */ 873 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 874 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN); 875 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 876 pci_err(priv->pci_dev, "I2C block read is unsupported!\n"); 877 return -EOPNOTSUPP; 878 } 879 880 /* Block buffer isn't supported for I2C block transactions */ 881 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command); 882 883 /* restore saved configuration register value */ 884 if (read_write == I2C_SMBUS_WRITE) 885 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 886 887 return result; 888} 889 890/* Return negative errno on error. */ 891static s32 i801_access(struct i2c_adapter *adap, u16 addr, 892 unsigned short flags, char read_write, u8 command, 893 int size, union i2c_smbus_data *data) 894{ 895 int hwpec, ret; 896 struct i801_priv *priv = i2c_get_adapdata(adap); 897 898 mutex_lock(&priv->acpi_lock); 899 if (priv->acpi_reserved) { 900 mutex_unlock(&priv->acpi_lock); 901 return -EBUSY; 902 } 903 904 pm_runtime_get_sync(&priv->pci_dev->dev); 905 906 ret = i801_check_pre(priv); 907 if (ret) 908 goto out; 909 910 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 911 && size != I2C_SMBUS_QUICK 912 && size != I2C_SMBUS_I2C_BLOCK_DATA; 913 914 if (hwpec) /* enable/disable hardware PEC */ 915 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 916 else 917 iowrite8(ioread8(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 918 SMBAUXCTL(priv)); 919 920 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL) 921 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size); 922 else if (size == I2C_SMBUS_I2C_BLOCK_DATA) 923 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size); 924 else 925 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 926 927 ret = i801_check_post(priv, ret); 928 929 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 930 * time, so we forcibly disable it after every transaction. 931 */ 932 if (hwpec) 933 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 934out: 935 /* 936 * Unlock the SMBus device for use by BIOS/ACPI, 937 * and clear status flags if not done already. 938 */ 939 iowrite8(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 940 941 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 942 mutex_unlock(&priv->acpi_lock); 943 return ret; 944} 945 946 947static u32 i801_func(struct i2c_adapter *adapter) 948{ 949 struct i801_priv *priv = i2c_get_adapdata(adapter); 950 951 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 952 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 953 I2C_FUNC_SMBUS_PROC_CALL | 954 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 955 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 956 ((priv->features & FEATURE_BLOCK_PROC) ? 957 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 958 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 959 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 960 ((priv->features & FEATURE_HOST_NOTIFY) ? 961 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 962} 963 964static void i801_enable_host_notify(struct i2c_adapter *adapter) 965{ 966 struct i801_priv *priv = i2c_get_adapdata(adapter); 967 968 if (!(priv->features & FEATURE_HOST_NOTIFY)) 969 return; 970 971 /* 972 * Enable host notify interrupt and block the generation of interrupt 973 * from the SMB_ALERT signal because the driver does not support 974 * SMBus Alert. 975 */ 976 iowrite8(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 977 priv->original_slvcmd, SMBSLVCMD(priv)); 978 979 /* clear Host Notify bit to allow a new notification */ 980 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 981} 982 983static void i801_disable_host_notify(struct i801_priv *priv) 984{ 985 if (!(priv->features & FEATURE_HOST_NOTIFY)) 986 return; 987 988 iowrite8(priv->original_slvcmd, SMBSLVCMD(priv)); 989} 990 991static const struct i2c_algorithm smbus_algorithm = { 992 .smbus_xfer = i801_access, 993 .functionality = i801_func, 994}; 995 996#define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 997 FEATURE_HOST_NOTIFY) 998#define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \ 999 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ) 1000 1001static const struct pci_device_id i801_ids[] = { 1002 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 1003 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 1004 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 1005 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 1006 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 1007 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1011 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1012 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1013 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1020 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1021 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1022 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1023 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1024 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1028 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1029 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1030 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1031 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1032 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1033 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1034 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1035 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1036 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1037 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1038 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1039 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1040 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1042 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1044 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1045 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1046 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1047 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1053 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1054 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1055 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1056 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1057 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1058 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1059 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1060 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1061 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1062 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1063 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1064 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1065 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5) }, 1066 { PCI_DEVICE_DATA(INTEL, DIAMOND_RAPIDS_SMBUS, FEATURES_ICH5) }, 1067 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1068 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1069 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1070 { PCI_DEVICE_DATA(INTEL, WILDCAT_LAKE_U_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1071 { PCI_DEVICE_DATA(INTEL, NOVA_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1072 { 0, } 1073}; 1074 1075MODULE_DEVICE_TABLE(pci, i801_ids); 1076 1077#if defined CONFIG_X86 && defined CONFIG_DMI 1078static unsigned char apanel_addr __ro_after_init; 1079 1080/* Scan the system ROM for the signature "FJKEYINF" */ 1081static __init const void __iomem *bios_signature(const void __iomem *bios) 1082{ 1083 ssize_t offset; 1084 const unsigned char signature[] = "FJKEYINF"; 1085 1086 for (offset = 0; offset < 0x10000; offset += 0x10) { 1087 if (check_signature(bios + offset, signature, 1088 sizeof(signature)-1)) 1089 return bios + offset; 1090 } 1091 return NULL; 1092} 1093 1094static void __init input_apanel_init(void) 1095{ 1096 void __iomem *bios; 1097 const void __iomem *p; 1098 1099 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1100 p = bios_signature(bios); 1101 if (p) { 1102 /* just use the first address */ 1103 apanel_addr = readb(p + 8 + 3) >> 1; 1104 } 1105 iounmap(bios); 1106} 1107 1108struct dmi_onboard_device_info { 1109 const char *name; 1110 u8 type; 1111 unsigned short i2c_addr; 1112 const char *i2c_type; 1113}; 1114 1115static const struct dmi_onboard_device_info dmi_devices[] = { 1116 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1117 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1118 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1119}; 1120 1121static void dmi_check_onboard_device(u8 type, const char *name, 1122 struct i2c_adapter *adap) 1123{ 1124 int i; 1125 struct i2c_board_info info; 1126 1127 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1128 /* & ~0x80, ignore enabled/disabled bit */ 1129 if ((type & ~0x80) != dmi_devices[i].type) 1130 continue; 1131 if (strcasecmp(name, dmi_devices[i].name)) 1132 continue; 1133 1134 memset(&info, 0, sizeof(struct i2c_board_info)); 1135 info.addr = dmi_devices[i].i2c_addr; 1136 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1137 i2c_new_client_device(adap, &info); 1138 break; 1139 } 1140} 1141 1142/* We use our own function to check for onboard devices instead of 1143 dmi_find_device() as some buggy BIOS's have the devices we are interested 1144 in marked as disabled */ 1145static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1146{ 1147 int i, count; 1148 1149 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE) 1150 return; 1151 1152 count = (dm->length - sizeof(struct dmi_header)) / 2; 1153 for (i = 0; i < count; i++) { 1154 const u8 *d = (char *)(dm + 1) + (i * 2); 1155 const char *name = ((char *) dm) + dm->length; 1156 u8 type = d[0]; 1157 u8 s = d[1]; 1158 1159 if (!s) 1160 continue; 1161 s--; 1162 while (s > 0 && name[0]) { 1163 name += strlen(name) + 1; 1164 s--; 1165 } 1166 if (name[0] == 0) /* Bogus string reference */ 1167 continue; 1168 1169 dmi_check_onboard_device(type, name, adap); 1170 } 1171} 1172 1173/* Register optional targets */ 1174static void i801_probe_optional_targets(struct i801_priv *priv) 1175{ 1176 /* Only register targets on main SMBus channel */ 1177 if (priv->features & FEATURE_IDF) 1178 return; 1179 1180 if (apanel_addr) { 1181 struct i2c_board_info info = { 1182 .addr = apanel_addr, 1183 .type = "fujitsu_apanel", 1184 }; 1185 1186 i2c_new_client_device(&priv->adapter, &info); 1187 } 1188 1189 if (dmi_name_in_vendors("FUJITSU")) 1190 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1191 1192 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1193#ifdef CONFIG_I2C_I801_MUX 1194 if (!priv->mux_pdev) 1195#endif 1196 i2c_register_spd_write_enable(&priv->adapter); 1197} 1198#else 1199static void __init input_apanel_init(void) {} 1200static void i801_probe_optional_targets(struct i801_priv *priv) {} 1201#endif /* CONFIG_X86 && CONFIG_DMI */ 1202 1203#ifdef CONFIG_I2C_I801_MUX 1204static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1205 .gpio_chip = "gpio_ich", 1206 .values = { 0x02, 0x03 }, 1207 .n_values = 2, 1208 .gpios = { 52, 53 }, 1209 .n_gpios = 2, 1210}; 1211 1212static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1213 .gpio_chip = "gpio_ich", 1214 .values = { 0x02, 0x03, 0x01 }, 1215 .n_values = 3, 1216 .gpios = { 52, 53 }, 1217 .n_gpios = 2, 1218}; 1219 1220static const struct dmi_system_id mux_dmi_table[] = { 1221 { 1222 .matches = { 1223 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1224 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1225 }, 1226 .driver_data = &i801_mux_config_asus_z8_d12, 1227 }, 1228 { 1229 .matches = { 1230 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1231 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1232 }, 1233 .driver_data = &i801_mux_config_asus_z8_d12, 1234 }, 1235 { 1236 .matches = { 1237 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1238 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1239 }, 1240 .driver_data = &i801_mux_config_asus_z8_d12, 1241 }, 1242 { 1243 .matches = { 1244 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1245 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1246 }, 1247 .driver_data = &i801_mux_config_asus_z8_d12, 1248 }, 1249 { 1250 .matches = { 1251 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1252 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1253 }, 1254 .driver_data = &i801_mux_config_asus_z8_d12, 1255 }, 1256 { 1257 .matches = { 1258 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1259 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1260 }, 1261 .driver_data = &i801_mux_config_asus_z8_d12, 1262 }, 1263 { 1264 .matches = { 1265 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1266 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1267 }, 1268 .driver_data = &i801_mux_config_asus_z8_d18, 1269 }, 1270 { 1271 .matches = { 1272 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1273 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1274 }, 1275 .driver_data = &i801_mux_config_asus_z8_d18, 1276 }, 1277 { 1278 .matches = { 1279 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1280 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1281 }, 1282 .driver_data = &i801_mux_config_asus_z8_d12, 1283 }, 1284 { } 1285}; 1286 1287static int i801_notifier_call(struct notifier_block *nb, unsigned long action, 1288 void *data) 1289{ 1290 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block); 1291 struct device *dev = data; 1292 1293 if (action != BUS_NOTIFY_ADD_DEVICE || 1294 dev->type != &i2c_adapter_type || 1295 i2c_root_adapter(dev) != &priv->adapter) 1296 return NOTIFY_DONE; 1297 1298 /* Call i2c_register_spd for muxed child segments */ 1299 i2c_register_spd_write_enable(to_i2c_adapter(dev)); 1300 1301 return NOTIFY_OK; 1302} 1303 1304/* Setup multiplexing if needed */ 1305static void i801_add_mux(struct i801_priv *priv) 1306{ 1307 struct device *dev = &priv->adapter.dev; 1308 const struct i801_mux_config *mux_config; 1309 struct i2c_mux_gpio_platform_data gpio_data; 1310 struct gpiod_lookup_table *lookup; 1311 const struct dmi_system_id *id; 1312 int i; 1313 1314 id = dmi_first_match(mux_dmi_table); 1315 if (!id) 1316 return; 1317 1318 mux_config = id->driver_data; 1319 1320 /* Prepare the platform data */ 1321 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1322 gpio_data.parent = priv->adapter.nr; 1323 gpio_data.values = mux_config->values; 1324 gpio_data.n_values = mux_config->n_values; 1325 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1326 1327 /* Register GPIO descriptor lookup table */ 1328 lookup = devm_kzalloc(dev, 1329 struct_size(lookup, table, mux_config->n_gpios + 1), 1330 GFP_KERNEL); 1331 if (!lookup) 1332 return; 1333 lookup->dev_id = "i2c-mux-gpio"; 1334 for (i = 0; i < mux_config->n_gpios; i++) 1335 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1336 mux_config->gpios[i], "mux", 0); 1337 gpiod_add_lookup_table(lookup); 1338 1339 priv->mux_notifier_block.notifier_call = i801_notifier_call; 1340 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block)) 1341 return; 1342 /* 1343 * Register the mux device, we use PLATFORM_DEVID_NONE here 1344 * because since we are referring to the GPIO chip by name we are 1345 * anyways in deep trouble if there is more than one of these 1346 * devices, and there should likely only be one platform controller 1347 * hub. 1348 */ 1349 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1350 PLATFORM_DEVID_NONE, &gpio_data, 1351 sizeof(struct i2c_mux_gpio_platform_data)); 1352 if (IS_ERR(priv->mux_pdev)) { 1353 gpiod_remove_lookup_table(lookup); 1354 devm_kfree(dev, lookup); 1355 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1356 } else { 1357 priv->lookup = lookup; 1358 } 1359} 1360 1361static void i801_del_mux(struct i801_priv *priv) 1362{ 1363 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block); 1364 platform_device_unregister(priv->mux_pdev); 1365 gpiod_remove_lookup_table(priv->lookup); 1366} 1367#else 1368static inline void i801_add_mux(struct i801_priv *priv) { } 1369static inline void i801_del_mux(struct i801_priv *priv) { } 1370#endif 1371 1372static struct platform_device * 1373i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res) 1374{ 1375 static const struct itco_wdt_platform_data pldata = { 1376 .name = "Intel PCH", 1377 .version = 4, 1378 }; 1379 struct resource *res; 1380 int ret; 1381 1382 /* 1383 * We must access the NO_REBOOT bit over the Primary to Sideband 1384 * (P2SB) bridge. 1385 */ 1386 1387 res = &tco_res[1]; 1388 ret = p2sb_bar(pci_dev->bus, 0, res); 1389 if (ret) 1390 return ERR_PTR(ret); 1391 1392 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1393 res->start += SBREG_SMBCTRL_DNV; 1394 else 1395 res->start += SBREG_SMBCTRL; 1396 1397 res->end = res->start + 3; 1398 1399 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1400 tco_res, 2, &pldata, sizeof(pldata)); 1401} 1402 1403static struct platform_device * 1404i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res) 1405{ 1406 static const struct itco_wdt_platform_data pldata = { 1407 .name = "Intel PCH", 1408 .version = 6, 1409 }; 1410 1411 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1412 tco_res, 1, &pldata, sizeof(pldata)); 1413} 1414 1415static void i801_add_tco(struct i801_priv *priv) 1416{ 1417 struct pci_dev *pci_dev = priv->pci_dev; 1418 struct resource tco_res[2], *res; 1419 u32 tco_base, tco_ctl; 1420 1421 /* If we have ACPI based watchdog use that instead */ 1422 if (acpi_has_watchdog()) 1423 return; 1424 1425 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1426 return; 1427 1428 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1429 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1430 if (!(tco_ctl & TCOCTL_EN)) 1431 return; 1432 1433 memset(tco_res, 0, sizeof(tco_res)); 1434 /* 1435 * Always populate the main iTCO IO resource here. The second entry 1436 * for NO_REBOOT MMIO is filled by the SPT specific function. 1437 */ 1438 res = &tco_res[0]; 1439 res->start = tco_base & ~1; 1440 res->end = res->start + 32 - 1; 1441 res->flags = IORESOURCE_IO; 1442 1443 if (priv->features & FEATURE_TCO_CNL) 1444 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res); 1445 else 1446 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res); 1447 1448 if (IS_ERR(priv->tco_pdev)) 1449 pci_warn(pci_dev, "failed to create iTCO device\n"); 1450} 1451 1452#ifdef CONFIG_ACPI 1453static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1454 acpi_physical_address address) 1455{ 1456 return address >= pci_resource_start(priv->pci_dev, SMBBAR) && 1457 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1458} 1459 1460static acpi_status 1461i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1462 u64 *value, void *handler_context, void *region_context) 1463{ 1464 struct i801_priv *priv = handler_context; 1465 struct pci_dev *pdev = priv->pci_dev; 1466 acpi_status status; 1467 1468 /* 1469 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1470 * further access from the driver itself. This device is now owned 1471 * by the system firmware. 1472 */ 1473 mutex_lock(&priv->acpi_lock); 1474 1475 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1476 priv->acpi_reserved = true; 1477 1478 pci_warn(pdev, "BIOS is accessing SMBus registers\n"); 1479 pci_warn(pdev, "Driver SMBus register access inhibited\n"); 1480 1481 /* 1482 * BIOS is accessing the host controller so prevent it from 1483 * suspending automatically from now on. 1484 */ 1485 pm_runtime_get_sync(&pdev->dev); 1486 } 1487 1488 if ((function & ACPI_IO_MASK) == ACPI_READ) 1489 status = acpi_os_read_port(address, (u32 *)value, bits); 1490 else 1491 status = acpi_os_write_port(address, (u32)*value, bits); 1492 1493 mutex_unlock(&priv->acpi_lock); 1494 1495 return status; 1496} 1497 1498static int i801_acpi_probe(struct i801_priv *priv) 1499{ 1500 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1501 acpi_status status; 1502 1503 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1504 i801_acpi_io_handler, NULL, priv); 1505 if (ACPI_SUCCESS(status)) 1506 return 0; 1507 1508 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1509} 1510 1511static void i801_acpi_remove(struct i801_priv *priv) 1512{ 1513 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1514 1515 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1516} 1517#else 1518static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1519static inline void i801_acpi_remove(struct i801_priv *priv) { } 1520#endif 1521 1522static void i801_setup_hstcfg(struct i801_priv *priv) 1523{ 1524 unsigned char hstcfg = priv->original_hstcfg; 1525 1526 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1527 hstcfg |= SMBHSTCFG_HST_EN; 1528 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1529} 1530 1531static void i801_restore_regs(struct i801_priv *priv) 1532{ 1533 iowrite8(priv->original_hstcnt, SMBHSTCNT(priv)); 1534 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1535} 1536 1537static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1538{ 1539 int err, i, bar = SMBBAR; 1540 struct i801_priv *priv; 1541 1542 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1543 if (!priv) 1544 return -ENOMEM; 1545 1546 i2c_set_adapdata(&priv->adapter, priv); 1547 priv->adapter.owner = THIS_MODULE; 1548 priv->adapter.class = I2C_CLASS_HWMON; 1549 priv->adapter.algo = &smbus_algorithm; 1550 priv->adapter.dev.parent = &dev->dev; 1551 acpi_use_parent_companion(&priv->adapter.dev); 1552 priv->adapter.retries = 3; 1553 mutex_init(&priv->acpi_lock); 1554 1555 priv->pci_dev = dev; 1556 priv->features = id->driver_data; 1557 1558 /* Disable features on user request */ 1559 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1560 if (priv->features & disable_features & (1 << i)) 1561 pci_notice(dev, "%s disabled by user\n", i801_feature_names[i]); 1562 } 1563 priv->features &= ~disable_features; 1564 1565 /* The block process call uses block buffer mode */ 1566 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1567 priv->features &= ~FEATURE_BLOCK_PROC; 1568 1569 /* 1570 * Do not call pcim_enable_device(), because the device has to remain 1571 * enabled on driver detach. See i801_remove() for the reasoning. 1572 */ 1573 err = pci_enable_device(dev); 1574 if (err) { 1575 pci_err(dev, "Failed to enable SMBus PCI device (%d)\n", err); 1576 return err; 1577 } 1578 1579 /* Determine the address of the SMBus area */ 1580 if (!pci_resource_start(dev, SMBBAR)) { 1581 pci_err(dev, "SMBus base address uninitialized, upgrade BIOS\n"); 1582 return -ENODEV; 1583 } 1584 1585 if (i801_acpi_probe(priv)) 1586 return -ENODEV; 1587 1588 if (pci_resource_flags(dev, SMBBAR_MMIO) & IORESOURCE_MEM) 1589 bar = SMBBAR_MMIO; 1590 1591 priv->smba = pcim_iomap_region(dev, bar, DRV_NAME); 1592 if (IS_ERR(priv->smba)) { 1593 pci_err(dev, "Failed to request SMBus region %pr\n", 1594 pci_resource_n(dev, bar)); 1595 i801_acpi_remove(priv); 1596 return PTR_ERR(priv->smba); 1597 } 1598 1599 pci_read_config_byte(dev, SMBHSTCFG, &priv->original_hstcfg); 1600 i801_setup_hstcfg(priv); 1601 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1602 pci_info(dev, "Enabling SMBus device\n"); 1603 1604 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1605 pci_dbg(dev, "SMBus using interrupt SMI#\n"); 1606 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1607 priv->features &= ~FEATURE_IRQ; 1608 } 1609 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1610 pci_info(dev, "SPD Write Disable is set\n"); 1611 1612 /* Clear special mode bits */ 1613 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1614 iowrite8(ioread8(SMBAUXCTL(priv)) & 1615 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1616 1617 /* Default timeout in interrupt mode: 200 ms */ 1618 priv->adapter.timeout = HZ / 5; 1619 1620 if (dev->irq == IRQ_NOTCONNECTED) 1621 priv->features &= ~FEATURE_IRQ; 1622 1623 if (priv->features & FEATURE_IRQ) { 1624 u16 pcists; 1625 1626 /* Complain if an interrupt is already pending */ 1627 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1628 if (pcists & PCI_STATUS_INTERRUPT) 1629 pci_warn(dev, "An interrupt is pending!\n"); 1630 } 1631 1632 if (priv->features & FEATURE_IRQ) { 1633 init_completion(&priv->done); 1634 1635 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1636 IRQF_SHARED, DRV_NAME, priv); 1637 if (err) { 1638 pci_err(dev, "Failed to allocate irq %d: %d\n", dev->irq, err); 1639 priv->features &= ~FEATURE_IRQ; 1640 } 1641 } 1642 pci_info(dev, "SMBus using %s\n", 1643 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1644 1645 /* Host notification uses an interrupt */ 1646 if (!(priv->features & FEATURE_IRQ)) 1647 priv->features &= ~FEATURE_HOST_NOTIFY; 1648 1649 /* Remember original Interrupt and Host Notify settings */ 1650 priv->original_hstcnt = ioread8(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1651 if (priv->features & FEATURE_HOST_NOTIFY) 1652 priv->original_slvcmd = ioread8(SMBSLVCMD(priv)); 1653 1654 i801_add_tco(priv); 1655 1656 /* 1657 * adapter.name is used by platform code to find the main I801 adapter 1658 * to instantiante i2c_clients, do not change. 1659 */ 1660 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1661 "SMBus %s adapter at %s", 1662 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801", 1663 pci_name(dev)); 1664 1665 err = i2c_add_adapter(&priv->adapter); 1666 if (err) { 1667 platform_device_unregister(priv->tco_pdev); 1668 i801_acpi_remove(priv); 1669 i801_restore_regs(priv); 1670 return err; 1671 } 1672 1673 i801_enable_host_notify(&priv->adapter); 1674 1675 /* We ignore errors - multiplexing is optional */ 1676 i801_add_mux(priv); 1677 i801_probe_optional_targets(priv); 1678 1679 pci_set_drvdata(dev, priv); 1680 1681 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1682 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1683 pm_runtime_use_autosuspend(&dev->dev); 1684 pm_runtime_put_autosuspend(&dev->dev); 1685 pm_runtime_allow(&dev->dev); 1686 1687 return 0; 1688} 1689 1690static void i801_remove(struct pci_dev *dev) 1691{ 1692 struct i801_priv *priv = pci_get_drvdata(dev); 1693 1694 i801_disable_host_notify(priv); 1695 i801_del_mux(priv); 1696 i2c_del_adapter(&priv->adapter); 1697 i801_acpi_remove(priv); 1698 1699 platform_device_unregister(priv->tco_pdev); 1700 1701 /* if acpi_reserved is set then usage_count is incremented already */ 1702 if (!priv->acpi_reserved) 1703 pm_runtime_get_noresume(&dev->dev); 1704 1705 i801_restore_regs(priv); 1706 1707 /* 1708 * do not call pci_disable_device(dev) since it can cause hard hangs on 1709 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1710 */ 1711} 1712 1713static void i801_shutdown(struct pci_dev *dev) 1714{ 1715 struct i801_priv *priv = pci_get_drvdata(dev); 1716 1717 i801_disable_host_notify(priv); 1718 /* Restore config registers to avoid hard hang on some systems */ 1719 i801_restore_regs(priv); 1720} 1721 1722static int i801_suspend(struct device *dev) 1723{ 1724 struct i801_priv *priv = dev_get_drvdata(dev); 1725 1726 i2c_mark_adapter_suspended(&priv->adapter); 1727 i801_restore_regs(priv); 1728 1729 return 0; 1730} 1731 1732static int i801_resume(struct device *dev) 1733{ 1734 struct i801_priv *priv = dev_get_drvdata(dev); 1735 1736 i801_setup_hstcfg(priv); 1737 i801_enable_host_notify(&priv->adapter); 1738 i2c_mark_adapter_resumed(&priv->adapter); 1739 1740 return 0; 1741} 1742 1743static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1744 1745static struct pci_driver i801_driver = { 1746 .name = DRV_NAME, 1747 .id_table = i801_ids, 1748 .probe = i801_probe, 1749 .remove = i801_remove, 1750 .shutdown = i801_shutdown, 1751 .driver = { 1752 .pm = pm_sleep_ptr(&i801_pm_ops), 1753 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1754 }, 1755}; 1756 1757static int __init i2c_i801_init(struct pci_driver *drv) 1758{ 1759 if (dmi_name_in_vendors("FUJITSU")) 1760 input_apanel_init(); 1761 return pci_register_driver(drv); 1762} 1763 1764MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1765MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1766MODULE_DESCRIPTION("I801 SMBus driver"); 1767MODULE_LICENSE("GPL"); 1768 1769module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);
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