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i2c-exynos5.c
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linux-6.19.14/drivers/i2c/busses/i2c-exynos5.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6*/ 7 8#include <linux/kernel.h> 9#include <linux/module.h> 10 11#include <linux/i2c.h> 12#include <linux/time.h> 13#include <linux/interrupt.h> 14#include <linux/delay.h> 15#include <linux/errno.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/clk.h> 19#include <linux/slab.h> 20#include <linux/io.h> 21#include <linux/of.h> 22#include <linux/spinlock.h> 23 24/* 25 * HSI2C controller from Samsung supports 2 modes of operation 26 * 1. Auto mode: Where in master automatically controls the whole transaction 27 * 2. Manual mode: Software controls the transaction by issuing commands 28 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. 29 * 30 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register 31 * 32 * Special bits are available for both modes of operation to set commands 33 * and for checking transfer status 34 */ 35 36/* Register Map */ 37#define HSI2C_CTL 0x00 38#define HSI2C_FIFO_CTL 0x04 39#define HSI2C_TRAILIG_CTL 0x08 40#define HSI2C_CLK_CTL 0x0C 41#define HSI2C_CLK_SLOT 0x10 42#define HSI2C_INT_ENABLE 0x20 43#define HSI2C_INT_STATUS 0x24 44#define HSI2C_ERR_STATUS 0x2C 45#define HSI2C_FIFO_STATUS 0x30 46#define HSI2C_TX_DATA 0x34 47#define HSI2C_RX_DATA 0x38 48#define HSI2C_CONF 0x40 49#define HSI2C_AUTO_CONF 0x44 50#define HSI2C_TIMEOUT 0x48 51#define HSI2C_MANUAL_CMD 0x4C 52#define HSI2C_TRANS_STATUS 0x50 53#define HSI2C_TIMING_HS1 0x54 54#define HSI2C_TIMING_HS2 0x58 55#define HSI2C_TIMING_HS3 0x5C 56#define HSI2C_TIMING_FS1 0x60 57#define HSI2C_TIMING_FS2 0x64 58#define HSI2C_TIMING_FS3 0x68 59#define HSI2C_TIMING_SLA 0x6C 60#define HSI2C_ADDR 0x70 61 62/* I2C_CTL Register bits */ 63#define HSI2C_FUNC_MODE_I2C (1u << 0) 64#define HSI2C_MASTER (1u << 3) 65#define HSI2C_RXCHON (1u << 6) 66#define HSI2C_TXCHON (1u << 7) 67#define HSI2C_SW_RST (1u << 31) 68 69/* I2C_FIFO_CTL Register bits */ 70#define HSI2C_RXFIFO_EN (1u << 0) 71#define HSI2C_TXFIFO_EN (1u << 1) 72#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) 73#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) 74 75/* I2C_TRAILING_CTL Register bits */ 76#define HSI2C_TRAILING_COUNT (0xf) 77 78/* I2C_INT_EN Register bits */ 79#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 80#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 81#define HSI2C_INT_TRAILING_EN (1u << 6) 82 83/* I2C_INT_STAT Register bits */ 84#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) 85#define HSI2C_INT_RX_ALMOSTFULL (1u << 1) 86#define HSI2C_INT_TX_UNDERRUN (1u << 2) 87#define HSI2C_INT_TX_OVERRUN (1u << 3) 88#define HSI2C_INT_RX_UNDERRUN (1u << 4) 89#define HSI2C_INT_RX_OVERRUN (1u << 5) 90#define HSI2C_INT_TRAILING (1u << 6) 91#define HSI2C_INT_I2C (1u << 9) 92 93#define HSI2C_INT_TRANS_DONE (1u << 7) 94#define HSI2C_INT_TRANS_ABORT (1u << 8) 95#define HSI2C_INT_NO_DEV_ACK (1u << 9) 96#define HSI2C_INT_NO_DEV (1u << 10) 97#define HSI2C_INT_TIMEOUT (1u << 11) 98#define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \ 99 HSI2C_INT_TRANS_ABORT | \ 100 HSI2C_INT_NO_DEV_ACK | \ 101 HSI2C_INT_NO_DEV | \ 102 HSI2C_INT_TIMEOUT) 103 104/* I2C_FIFO_STAT Register bits */ 105#define HSI2C_RX_FIFO_EMPTY (1u << 24) 106#define HSI2C_RX_FIFO_FULL (1u << 23) 107#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) 108#define HSI2C_TX_FIFO_EMPTY (1u << 8) 109#define HSI2C_TX_FIFO_FULL (1u << 7) 110#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) 111 112/* I2C_CONF Register bits */ 113#define HSI2C_AUTO_MODE (1u << 31) 114#define HSI2C_10BIT_ADDR_MODE (1u << 30) 115#define HSI2C_HS_MODE (1u << 29) 116 117/* I2C_AUTO_CONF Register bits */ 118#define HSI2C_READ_WRITE (1u << 16) 119#define HSI2C_STOP_AFTER_TRANS (1u << 17) 120#define HSI2C_MASTER_RUN (1u << 31) 121 122/* I2C_TIMEOUT Register bits */ 123#define HSI2C_TIMEOUT_EN (1u << 31) 124#define HSI2C_TIMEOUT_MASK 0xff 125 126/* I2C_MANUAL_CMD register bits */ 127#define HSI2C_CMD_READ_DATA (1u << 4) 128#define HSI2C_CMD_SEND_STOP (1u << 2) 129 130/* I2C_TRANS_STATUS register bits */ 131#define HSI2C_MASTER_BUSY (1u << 17) 132#define HSI2C_SLAVE_BUSY (1u << 16) 133 134/* I2C_TRANS_STATUS register bits for Exynos5 variant */ 135#define HSI2C_TIMEOUT_AUTO (1u << 4) 136#define HSI2C_NO_DEV (1u << 3) 137#define HSI2C_NO_DEV_ACK (1u << 2) 138#define HSI2C_TRANS_ABORT (1u << 1) 139#define HSI2C_TRANS_DONE (1u << 0) 140 141/* I2C_TRANS_STATUS register bits for Exynos7 variant */ 142#define HSI2C_MASTER_ST_MASK 0xf 143#define HSI2C_MASTER_ST_IDLE 0x0 144#define HSI2C_MASTER_ST_START 0x1 145#define HSI2C_MASTER_ST_RESTART 0x2 146#define HSI2C_MASTER_ST_STOP 0x3 147#define HSI2C_MASTER_ST_MASTER_ID 0x4 148#define HSI2C_MASTER_ST_ADDR0 0x5 149#define HSI2C_MASTER_ST_ADDR1 0x6 150#define HSI2C_MASTER_ST_ADDR2 0x7 151#define HSI2C_MASTER_ST_ADDR_SR 0x8 152#define HSI2C_MASTER_ST_READ 0x9 153#define HSI2C_MASTER_ST_WRITE 0xa 154#define HSI2C_MASTER_ST_NO_ACK 0xb 155#define HSI2C_MASTER_ST_LOSE 0xc 156#define HSI2C_MASTER_ST_WAIT 0xd 157#define HSI2C_MASTER_ST_WAIT_CMD 0xe 158 159/* I2C_ADDR register bits */ 160#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 161#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 162#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) 163#define MASTER_ID(x) ((x & 0x7) + 0x08) 164 165#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100)) 166 167enum i2c_type_exynos { 168 I2C_TYPE_EXYNOS5, 169 I2C_TYPE_EXYNOS7, 170 I2C_TYPE_EXYNOSAUTOV9, 171 I2C_TYPE_EXYNOS8895, 172}; 173 174struct exynos5_i2c { 175 struct i2c_adapter adap; 176 177 struct i2c_msg *msg; 178 struct completion msg_complete; 179 unsigned int msg_ptr; 180 181 unsigned int irq; 182 183 void __iomem *regs; 184 struct clk *clk; /* operating clock */ 185 struct clk *pclk; /* bus clock */ 186 struct device *dev; 187 int state; 188 189 spinlock_t lock; /* IRQ synchronization */ 190 191 /* 192 * Since the TRANS_DONE bit is cleared on read, and we may read it 193 * either during an IRQ or after a transaction, keep track of its 194 * state here. 195 */ 196 int trans_done; 197 198 /* 199 * Called from atomic context, don't use interrupts. 200 */ 201 unsigned int atomic; 202 203 /* Controller operating frequency */ 204 unsigned int op_clock; 205 206 /* Version of HS-I2C Hardware */ 207 const struct exynos_hsi2c_variant *variant; 208}; 209 210/** 211 * struct exynos_hsi2c_variant - platform specific HSI2C driver data 212 * @fifo_depth: the fifo depth supported by the HSI2C module 213 * @hw: the hardware variant of Exynos I2C controller 214 * 215 * Specifies platform specific configuration of HSI2C module. 216 * Note: A structure for driver specific platform data is used for future 217 * expansion of its usage. 218 */ 219struct exynos_hsi2c_variant { 220 unsigned int fifo_depth; 221 enum i2c_type_exynos hw; 222}; 223 224static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { 225 .fifo_depth = 64, 226 .hw = I2C_TYPE_EXYNOS5, 227}; 228 229static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { 230 .fifo_depth = 16, 231 .hw = I2C_TYPE_EXYNOS5, 232}; 233 234static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { 235 .fifo_depth = 16, 236 .hw = I2C_TYPE_EXYNOS7, 237}; 238 239static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = { 240 .fifo_depth = 64, 241 .hw = I2C_TYPE_EXYNOSAUTOV9, 242}; 243 244static const struct exynos_hsi2c_variant exynos8895_hsi2c_data = { 245 .fifo_depth = 64, 246 .hw = I2C_TYPE_EXYNOS8895, 247}; 248 249static const struct of_device_id exynos5_i2c_match[] = { 250 { 251 .compatible = "samsung,exynos5-hsi2c", 252 .data = &exynos5250_hsi2c_data 253 }, { 254 .compatible = "samsung,exynos5250-hsi2c", 255 .data = &exynos5250_hsi2c_data 256 }, { 257 .compatible = "samsung,exynos5260-hsi2c", 258 .data = &exynos5260_hsi2c_data 259 }, { 260 .compatible = "samsung,exynos7-hsi2c", 261 .data = &exynos7_hsi2c_data 262 }, { 263 .compatible = "samsung,exynosautov9-hsi2c", 264 .data = &exynosautov9_hsi2c_data 265 }, { 266 .compatible = "samsung,exynos8895-hsi2c", 267 .data = &exynos8895_hsi2c_data 268 }, {}, 269}; 270MODULE_DEVICE_TABLE(of, exynos5_i2c_match); 271 272static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) 273{ 274 writel(readl(i2c->regs + HSI2C_INT_STATUS), 275 i2c->regs + HSI2C_INT_STATUS); 276} 277 278/* 279 * exynos5_i2c_set_timing: updates the registers with appropriate 280 * timing values calculated 281 * 282 * Timing values for operation are calculated against 100kHz, 400kHz 283 * or 1MHz controller operating frequency. 284 * 285 * Returns 0 on success, -EINVAL if the cycle length cannot 286 * be calculated. 287 */ 288static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) 289{ 290 u32 i2c_timing_s1; 291 u32 i2c_timing_s2; 292 u32 i2c_timing_s3; 293 u32 i2c_timing_sla; 294 unsigned int t_start_su, t_start_hd; 295 unsigned int t_stop_su; 296 unsigned int t_data_su, t_data_hd; 297 unsigned int t_scl_l, t_scl_h; 298 unsigned int t_sr_release; 299 unsigned int t_ftl_cycle; 300 unsigned int clkin = clk_get_rate(i2c->clk); 301 unsigned int op_clk = hs_timings ? i2c->op_clock : 302 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ : 303 i2c->op_clock; 304 int div, clk_cycle, temp; 305 306 /* 307 * In case of HSI2C controllers in ExynosAutoV9: 308 * 309 * FSCL = IPCLK / ((CLK_DIV + 1) * 16) 310 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M) 311 * [N : number of 0's in the TSCL_H_HS] 312 * [M : number of 0's in the TSCL_L_HS] 313 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M) 314 * [N : number of 1's in the TSCL_H_HS] 315 * [M : number of 1's in the TSCL_L_HS] 316 * 317 * Result of (N + M) is always 8. 318 * In general case, we don't need to control timing_s1 and timing_s2. 319 */ 320 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { 321 div = ((clkin / (16 * i2c->op_clock)) - 1); 322 i2c_timing_s3 = div << 16; 323 if (hs_timings) 324 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 325 else 326 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 327 328 return 0; 329 } 330 331 /* 332 * In case of HSI2C controller in Exynos5 series 333 * FPCLK / FI2C = 334 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 335 * 336 * In case of HSI2C controllers in Exynos7 series 337 * FPCLK / FI2C = 338 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE 339 * 340 * clk_cycle := TSCLK_L + TSCLK_H 341 * temp := (CLK_DIV + 1) * (clk_cycle + 2) 342 * 343 * In case of HSI2C controllers in Exynos8895 344 * FPCLK / FI2C = 345 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 346 * 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1)) 347 * 348 * clk_cycle := TSCLK_L + TSCLK_H 349 * temp := (FPCLK / FI2C) - (FLT_CYCLE + 3) * 2 350 * 351 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 352 * 353 * To split SCL clock into low, high periods appropriately, one 354 * proportion factor for each I2C mode is used, which is calculated 355 * using this formula. 356 * ``` 357 * ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock) 358 * ``` 359 * where: 360 * t_low_min is the minimal value of low period of the SCL clock in us; 361 * t_high_min is the minimal value of high period of the SCL clock in us; 362 * scl_clock is converted from SCL clock frequency into us. 363 * 364 * Below are the proportion factors for these I2C modes: 365 * t_low_min, t_high_min, scl_clock, proportion 366 * Standard Mode: 4.7us, 4.0us, 10us, 0.535 367 * Fast Mode: 1.3us, 0.6us, 2.5us, 0.64 368 * Fast-Plus Mode: 0.5us, 0.26us, 1us, 0.62 369 * 370 */ 371 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 372 if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) 373 temp = clkin / op_clk - (t_ftl_cycle + 3) * 2; 374 else if (i2c->variant->hw == I2C_TYPE_EXYNOS7) 375 temp = clkin / op_clk - 8 - t_ftl_cycle; 376 else 377 temp = clkin / op_clk - 8 - (t_ftl_cycle * 2); 378 div = temp / 512; 379 380 if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) 381 clk_cycle = (temp + ((t_ftl_cycle + 3) % (div + 1)) * 2) / 382 (div + 1) - 2; 383 else 384 clk_cycle = temp / (div + 1) - 2; 385 if (temp < 4 || div >= 256 || clk_cycle < 2) { 386 dev_err(i2c->dev, "%s clock set-up failed\n", 387 hs_timings ? "HS" : "FS"); 388 return -EINVAL; 389 } 390 391 /* 392 * Scale clk_cycle to get t_scl_l using the proption factors for individual I2C modes. 393 */ 394 if (op_clk <= I2C_MAX_STANDARD_MODE_FREQ) 395 t_scl_l = clk_cycle * 535 / 1000; 396 else if (op_clk <= I2C_MAX_FAST_MODE_FREQ) 397 t_scl_l = clk_cycle * 64 / 100; 398 else 399 t_scl_l = clk_cycle * 62 / 100; 400 401 if (t_scl_l > 0xFF) 402 t_scl_l = 0xFF; 403 t_scl_h = clk_cycle - t_scl_l; 404 t_start_su = t_scl_l; 405 t_start_hd = t_scl_l; 406 t_stop_su = t_scl_l; 407 t_data_su = t_scl_l / 2; 408 t_data_hd = t_scl_l / 2; 409 t_sr_release = clk_cycle; 410 411 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 412 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 413 i2c_timing_s3 = div << 16 | t_sr_release << 0; 414 i2c_timing_sla = t_data_hd << 0; 415 416 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", 417 t_start_su, t_start_hd, t_stop_su); 418 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", 419 t_data_su, t_scl_l, t_scl_h); 420 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", 421 div, t_sr_release); 422 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); 423 424 if (hs_timings) { 425 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); 426 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); 427 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 428 } else { 429 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); 430 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); 431 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 432 } 433 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); 434 435 return 0; 436} 437 438static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) 439{ 440 /* always set Fast Speed timings */ 441 int ret = exynos5_i2c_set_timing(i2c, false); 442 443 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ) 444 return ret; 445 446 return exynos5_i2c_set_timing(i2c, true); 447} 448 449/* 450 * exynos5_i2c_init: configures the controller for I2C functionality 451 * Programs I2C controller for Master mode operation 452 */ 453static void exynos5_i2c_init(struct exynos5_i2c *i2c) 454{ 455 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); 456 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); 457 458 /* Clear to disable Timeout */ 459 i2c_timeout &= ~HSI2C_TIMEOUT_EN; 460 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); 461 462 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 463 i2c->regs + HSI2C_CTL); 464 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); 465 466 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) { 467 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), 468 i2c->regs + HSI2C_ADDR); 469 i2c_conf |= HSI2C_HS_MODE; 470 } 471 472 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); 473} 474 475static void exynos5_i2c_reset(struct exynos5_i2c *i2c) 476{ 477 u32 i2c_ctl; 478 479 /* Set and clear the bit for reset */ 480 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 481 i2c_ctl |= HSI2C_SW_RST; 482 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 483 484 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 485 i2c_ctl &= ~HSI2C_SW_RST; 486 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 487 488 /* We don't expect calculations to fail during the run */ 489 exynos5_hsi2c_clock_setup(i2c); 490 /* Initialize the configure registers */ 491 exynos5_i2c_init(i2c); 492} 493 494/* 495 * exynos5_i2c_irq: top level IRQ servicing routine 496 * 497 * INT_STATUS registers gives the interrupt details. Further, 498 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed 499 * state of the bus. 500 */ 501static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) 502{ 503 struct exynos5_i2c *i2c = dev_id; 504 u32 fifo_level, int_status, fifo_status, trans_status; 505 unsigned char byte; 506 int len = 0; 507 508 i2c->state = -EINVAL; 509 510 spin_lock(&i2c->lock); 511 512 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 513 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 514 515 /* handle interrupt related to the transfer status */ 516 switch (i2c->variant->hw) { 517 case I2C_TYPE_EXYNOSAUTOV9: 518 fallthrough; 519 case I2C_TYPE_EXYNOS8895: 520 fallthrough; 521 case I2C_TYPE_EXYNOS7: 522 if (int_status & HSI2C_INT_TRANS_DONE) { 523 i2c->trans_done = 1; 524 i2c->state = 0; 525 } else if (int_status & HSI2C_INT_TRANS_ABORT) { 526 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 527 i2c->state = -EAGAIN; 528 goto stop; 529 } else if (int_status & HSI2C_INT_NO_DEV_ACK) { 530 dev_dbg(i2c->dev, "No ACK from device\n"); 531 i2c->state = -ENXIO; 532 goto stop; 533 } else if (int_status & HSI2C_INT_NO_DEV) { 534 dev_dbg(i2c->dev, "No device\n"); 535 i2c->state = -ENXIO; 536 goto stop; 537 } else if (int_status & HSI2C_INT_TIMEOUT) { 538 dev_dbg(i2c->dev, "Accessing device timed out\n"); 539 i2c->state = -ETIMEDOUT; 540 goto stop; 541 } 542 543 break; 544 case I2C_TYPE_EXYNOS5: 545 if (!(int_status & HSI2C_INT_I2C)) 546 break; 547 548 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 549 if (trans_status & HSI2C_NO_DEV_ACK) { 550 dev_dbg(i2c->dev, "No ACK from device\n"); 551 i2c->state = -ENXIO; 552 goto stop; 553 } else if (trans_status & HSI2C_NO_DEV) { 554 dev_dbg(i2c->dev, "No device\n"); 555 i2c->state = -ENXIO; 556 goto stop; 557 } else if (trans_status & HSI2C_TRANS_ABORT) { 558 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 559 i2c->state = -EAGAIN; 560 goto stop; 561 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 562 dev_dbg(i2c->dev, "Accessing device timed out\n"); 563 i2c->state = -ETIMEDOUT; 564 goto stop; 565 } else if (trans_status & HSI2C_TRANS_DONE) { 566 i2c->trans_done = 1; 567 i2c->state = 0; 568 } 569 570 break; 571 } 572 573 if ((i2c->msg->flags & I2C_M_RD) && (int_status & 574 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { 575 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 576 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); 577 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); 578 579 while (len > 0) { 580 byte = (unsigned char) 581 readl(i2c->regs + HSI2C_RX_DATA); 582 i2c->msg->buf[i2c->msg_ptr++] = byte; 583 len--; 584 } 585 i2c->state = 0; 586 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { 587 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 588 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 589 590 len = i2c->variant->fifo_depth - fifo_level; 591 if (len > (i2c->msg->len - i2c->msg_ptr)) { 592 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); 593 594 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN; 595 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 596 len = i2c->msg->len - i2c->msg_ptr; 597 } 598 599 while (len > 0) { 600 byte = i2c->msg->buf[i2c->msg_ptr++]; 601 writel(byte, i2c->regs + HSI2C_TX_DATA); 602 len--; 603 } 604 i2c->state = 0; 605 } 606 607 stop: 608 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 609 (i2c->state < 0)) { 610 writel(0, i2c->regs + HSI2C_INT_ENABLE); 611 exynos5_i2c_clr_pend_irq(i2c); 612 complete(&i2c->msg_complete); 613 } 614 615 spin_unlock(&i2c->lock); 616 617 return IRQ_HANDLED; 618} 619 620/* 621 * exynos5_i2c_wait_bus_idle 622 * 623 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being 624 * cleared. 625 * 626 * Returns -EBUSY if the bus cannot be bought to idle 627 */ 628static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) 629{ 630 unsigned long stop_time; 631 u32 trans_status; 632 633 /* wait for 100 milli seconds for the bus to be idle */ 634 stop_time = jiffies + msecs_to_jiffies(100) + 1; 635 do { 636 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 637 if (!(trans_status & HSI2C_MASTER_BUSY)) 638 return 0; 639 640 usleep_range(50, 200); 641 } while (time_before(jiffies, stop_time)); 642 643 return -EBUSY; 644} 645 646static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c) 647{ 648 u32 val; 649 650 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; 651 writel(val, i2c->regs + HSI2C_CTL); 652 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; 653 writel(val, i2c->regs + HSI2C_CONF); 654 655 /* 656 * Specification says master should send nine clock pulses. It can be 657 * emulated by sending manual read command (nine pulses for read eight 658 * bits + one pulse for NACK). 659 */ 660 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); 661 exynos5_i2c_wait_bus_idle(i2c); 662 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); 663 exynos5_i2c_wait_bus_idle(i2c); 664 665 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; 666 writel(val, i2c->regs + HSI2C_CTL); 667 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; 668 writel(val, i2c->regs + HSI2C_CONF); 669} 670 671static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) 672{ 673 unsigned long timeout; 674 675 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) 676 return; 677 678 /* 679 * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants) 680 * before transaction indicates that bus is stuck (SDA is low). 681 * In such case bus recovery can be performed. 682 */ 683 timeout = jiffies + msecs_to_jiffies(100); 684 for (;;) { 685 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); 686 687 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE) 688 return; 689 690 if (time_is_before_jiffies(timeout)) 691 return; 692 693 exynos5_i2c_bus_recover(i2c); 694 } 695} 696 697/* 698 * exynos5_i2c_message_start: Configures the bus and starts the xfer 699 * i2c: struct exynos5_i2c pointer for the current bus 700 * stop: Enables stop after transfer if set. Set for last transfer of 701 * in the list of messages. 702 * 703 * Configures the bus for read/write function 704 * Sets chip address to talk to, message length to be sent. 705 * Enables appropriate interrupts and sends start xfer command. 706 */ 707static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 708{ 709 u32 i2c_ctl; 710 u32 int_en = 0; 711 u32 i2c_auto_conf = 0; 712 u32 i2c_addr = 0; 713 u32 fifo_ctl; 714 unsigned long flags; 715 unsigned short trig_lvl; 716 717 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) 718 int_en |= HSI2C_INT_I2C; 719 else 720 int_en |= HSI2C_INT_I2C_TRANS; 721 722 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 723 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); 724 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; 725 726 if (i2c->msg->flags & I2C_M_RD) { 727 i2c_ctl |= HSI2C_RXCHON; 728 729 i2c_auto_conf |= HSI2C_READ_WRITE; 730 731 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 732 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; 733 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl); 734 735 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | 736 HSI2C_INT_TRAILING_EN); 737 } else { 738 i2c_ctl |= HSI2C_TXCHON; 739 740 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 741 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; 742 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl); 743 744 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; 745 } 746 747 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); 748 749 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) 750 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)); 751 752 writel(i2c_addr, i2c->regs + HSI2C_ADDR); 753 754 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); 755 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 756 757 exynos5_i2c_bus_check(i2c); 758 759 /* 760 * Enable interrupts before starting the transfer so that we don't 761 * miss any INT_I2C interrupts. 762 */ 763 spin_lock_irqsave(&i2c->lock, flags); 764 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 765 766 if (stop == 1) 767 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; 768 i2c_auto_conf |= i2c->msg->len; 769 i2c_auto_conf |= HSI2C_MASTER_RUN; 770 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); 771 spin_unlock_irqrestore(&i2c->lock, flags); 772} 773 774static bool exynos5_i2c_poll_irqs_timeout(struct exynos5_i2c *i2c, 775 unsigned long timeout) 776{ 777 unsigned long time_left = jiffies + timeout; 778 779 while (time_before(jiffies, time_left) && 780 !((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 781 (i2c->state < 0))) { 782 while (readl(i2c->regs + HSI2C_INT_ENABLE) & 783 readl(i2c->regs + HSI2C_INT_STATUS)) 784 exynos5_i2c_irq(i2c->irq, i2c); 785 usleep_range(100, 200); 786 } 787 return time_before(jiffies, time_left); 788} 789 790static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, 791 struct i2c_msg *msgs, int stop) 792{ 793 unsigned long time_left; 794 int ret; 795 796 i2c->msg = msgs; 797 i2c->msg_ptr = 0; 798 i2c->trans_done = 0; 799 800 reinit_completion(&i2c->msg_complete); 801 802 exynos5_i2c_message_start(i2c, stop); 803 804 if (!i2c->atomic) 805 time_left = wait_for_completion_timeout(&i2c->msg_complete, 806 EXYNOS5_I2C_TIMEOUT); 807 else 808 time_left = exynos5_i2c_poll_irqs_timeout(i2c, 809 EXYNOS5_I2C_TIMEOUT); 810 811 if (time_left == 0) 812 ret = -ETIMEDOUT; 813 else 814 ret = i2c->state; 815 816 /* 817 * If this is the last message to be transferred (stop == 1) 818 * Then check if the bus can be brought back to idle. 819 */ 820 if (ret == 0 && stop) 821 ret = exynos5_i2c_wait_bus_idle(i2c); 822 823 if (ret < 0) { 824 exynos5_i2c_reset(i2c); 825 if (ret == -ETIMEDOUT) 826 dev_warn(i2c->dev, "%s timeout\n", 827 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); 828 } 829 830 /* Return the state as in interrupt routine */ 831 return ret; 832} 833 834static int exynos5_i2c_xfer(struct i2c_adapter *adap, 835 struct i2c_msg *msgs, int num) 836{ 837 struct exynos5_i2c *i2c = adap->algo_data; 838 int i, ret; 839 840 ret = clk_enable(i2c->pclk); 841 if (ret) 842 return ret; 843 844 ret = clk_enable(i2c->clk); 845 if (ret) 846 goto err_pclk; 847 848 for (i = 0; i < num; ++i) { 849 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num); 850 if (ret) 851 break; 852 } 853 854 clk_disable(i2c->clk); 855err_pclk: 856 clk_disable(i2c->pclk); 857 858 return ret ?: num; 859} 860 861static int exynos5_i2c_xfer_atomic(struct i2c_adapter *adap, 862 struct i2c_msg *msgs, int num) 863{ 864 struct exynos5_i2c *i2c = adap->algo_data; 865 int ret; 866 867 disable_irq(i2c->irq); 868 i2c->atomic = true; 869 ret = exynos5_i2c_xfer(adap, msgs, num); 870 i2c->atomic = false; 871 enable_irq(i2c->irq); 872 873 return ret; 874} 875 876static u32 exynos5_i2c_func(struct i2c_adapter *adap) 877{ 878 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 879} 880 881static const struct i2c_algorithm exynos5_i2c_algorithm = { 882 .xfer = exynos5_i2c_xfer, 883 .xfer_atomic = exynos5_i2c_xfer_atomic, 884 .functionality = exynos5_i2c_func, 885}; 886 887static int exynos5_i2c_probe(struct platform_device *pdev) 888{ 889 struct device_node *np = pdev->dev.of_node; 890 struct exynos5_i2c *i2c; 891 int ret; 892 893 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); 894 if (!i2c) 895 return -ENOMEM; 896 897 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) 898 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; 899 900 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); 901 i2c->adap.owner = THIS_MODULE; 902 i2c->adap.algo = &exynos5_i2c_algorithm; 903 i2c->adap.retries = 3; 904 905 i2c->dev = &pdev->dev; 906 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); 907 if (IS_ERR(i2c->clk)) { 908 dev_err(&pdev->dev, "cannot get clock\n"); 909 return -ENOENT; 910 } 911 912 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk"); 913 if (IS_ERR(i2c->pclk)) { 914 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk), 915 "cannot get pclk"); 916 } 917 918 ret = clk_prepare_enable(i2c->pclk); 919 if (ret) 920 return ret; 921 922 ret = clk_prepare_enable(i2c->clk); 923 if (ret) 924 goto err_pclk; 925 926 i2c->regs = devm_platform_ioremap_resource(pdev, 0); 927 if (IS_ERR(i2c->regs)) { 928 ret = PTR_ERR(i2c->regs); 929 goto err_clk; 930 } 931 932 i2c->adap.dev.of_node = np; 933 i2c->adap.algo_data = i2c; 934 i2c->adap.dev.parent = &pdev->dev; 935 936 /* Clear pending interrupts from u-boot or misc causes */ 937 exynos5_i2c_clr_pend_irq(i2c); 938 939 spin_lock_init(&i2c->lock); 940 init_completion(&i2c->msg_complete); 941 942 i2c->irq = ret = platform_get_irq(pdev, 0); 943 if (ret < 0) 944 goto err_clk; 945 946 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 947 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c); 948 if (ret != 0) { 949 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); 950 goto err_clk; 951 } 952 953 i2c->variant = of_device_get_match_data(&pdev->dev); 954 955 ret = exynos5_hsi2c_clock_setup(i2c); 956 if (ret) 957 goto err_clk; 958 959 exynos5_i2c_reset(i2c); 960 961 ret = i2c_add_adapter(&i2c->adap); 962 if (ret < 0) 963 goto err_clk; 964 965 platform_set_drvdata(pdev, i2c); 966 967 clk_disable(i2c->clk); 968 clk_disable(i2c->pclk); 969 970 return 0; 971 972 err_clk: 973 clk_disable_unprepare(i2c->clk); 974 975 err_pclk: 976 clk_disable_unprepare(i2c->pclk); 977 return ret; 978} 979 980static void exynos5_i2c_remove(struct platform_device *pdev) 981{ 982 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 983 984 i2c_del_adapter(&i2c->adap); 985 986 clk_unprepare(i2c->clk); 987 clk_unprepare(i2c->pclk); 988} 989 990static int exynos5_i2c_suspend_noirq(struct device *dev) 991{ 992 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 993 994 i2c_mark_adapter_suspended(&i2c->adap); 995 clk_unprepare(i2c->clk); 996 clk_unprepare(i2c->pclk); 997 998 return 0; 999} 1000 1001static int exynos5_i2c_resume_noirq(struct device *dev) 1002{ 1003 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 1004 int ret = 0; 1005 1006 ret = clk_prepare_enable(i2c->pclk); 1007 if (ret) 1008 return ret; 1009 1010 ret = clk_prepare_enable(i2c->clk); 1011 if (ret) 1012 goto err_pclk; 1013 1014 ret = exynos5_hsi2c_clock_setup(i2c); 1015 if (ret) 1016 goto err_clk; 1017 1018 exynos5_i2c_init(i2c); 1019 clk_disable(i2c->clk); 1020 clk_disable(i2c->pclk); 1021 i2c_mark_adapter_resumed(&i2c->adap); 1022 1023 return 0; 1024 1025err_clk: 1026 clk_disable_unprepare(i2c->clk); 1027err_pclk: 1028 clk_disable_unprepare(i2c->pclk); 1029 return ret; 1030} 1031 1032static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = { 1033 NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq, 1034 exynos5_i2c_resume_noirq) 1035}; 1036 1037static struct platform_driver exynos5_i2c_driver = { 1038 .probe = exynos5_i2c_probe, 1039 .remove = exynos5_i2c_remove, 1040 .driver = { 1041 .name = "exynos5-hsi2c", 1042 .pm = pm_sleep_ptr(&exynos5_i2c_dev_pm_ops), 1043 .of_match_table = exynos5_i2c_match, 1044 }, 1045}; 1046 1047module_platform_driver(exynos5_i2c_driver); 1048 1049MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); 1050MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 1051MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>"); 1052MODULE_LICENSE("GPL v2");
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