i2c-eg20t.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  4 */
  5
  6#include <linux/module.h>
  7#include <linux/kernel.h>
  8#include <linux/delay.h>
  9#include <linux/errno.h>
 10#include <linux/i2c.h>
 11#include <linux/fs.h>
 12#include <linux/io.h>
 13#include <linux/types.h>
 14#include <linux/interrupt.h>
 15#include <linux/jiffies.h>
 16#include <linux/pci.h>
 17#include <linux/mutex.h>
 18#include <linux/ktime.h>
 19#include <linux/slab.h>
 20
 21#define PCH_EVENT_SET	0	/* I2C Interrupt Event Set Status */
 22#define PCH_EVENT_NONE	1	/* I2C Interrupt Event Clear Status */
 23#define PCH_MAX_CLK		100000	/* Maximum Clock speed in MHz */
 24#define PCH_BUFFER_MODE_ENABLE	0x0002	/* flag for Buffer mode enable */
 25#define PCH_EEPROM_SW_RST_MODE_ENABLE	0x0008	/* EEPROM SW RST enable flag */
 26
 27#define PCH_I2CSADR	0x00	/* I2C slave address register */
 28#define PCH_I2CCTL	0x04	/* I2C control register */
 29#define PCH_I2CSR	0x08	/* I2C status register */
 30#define PCH_I2CDR	0x0C	/* I2C data register */
 31#define PCH_I2CMON	0x10	/* I2C bus monitor register */
 32#define PCH_I2CBC	0x14	/* I2C bus transfer rate setup counter */
 33#define PCH_I2CMOD	0x18	/* I2C mode register */
 34#define PCH_I2CBUFSLV	0x1C	/* I2C buffer mode slave address register */
 35#define PCH_I2CBUFSUB	0x20	/* I2C buffer mode subaddress register */
 36#define PCH_I2CBUFFOR	0x24	/* I2C buffer mode format register */
 37#define PCH_I2CBUFCTL	0x28	/* I2C buffer mode control register */
 38#define PCH_I2CBUFMSK	0x2C	/* I2C buffer mode interrupt mask register */
 39#define PCH_I2CBUFSTA	0x30	/* I2C buffer mode status register */
 40#define PCH_I2CBUFLEV	0x34	/* I2C buffer mode level register */
 41#define PCH_I2CESRFOR	0x38	/* EEPROM software reset mode format register */
 42#define PCH_I2CESRCTL	0x3C	/* EEPROM software reset mode ctrl register */
 43#define PCH_I2CESRMSK	0x40	/* EEPROM software reset mode */
 44#define PCH_I2CESRSTA	0x44	/* EEPROM software reset mode status register */
 45#define PCH_I2CTMR	0x48	/* I2C timer register */
 46#define PCH_I2CSRST	0xFC	/* I2C reset register */
 47#define PCH_I2CNF	0xF8	/* I2C noise filter register */
 48
 49#define BUS_IDLE_TIMEOUT	20
 50#define PCH_I2CCTL_I2CMEN	0x0080
 51#define PCH_START		0x0020
 52#define PCH_RESTART		0x0004
 53#define PCH_ESR_START		0x0001
 54#define PCH_BUFF_START		0x1
 55#define PCH_REPSTART		0x0004
 56#define PCH_ACK			0x0008
 57#define PCH_GETACK		0x0001
 58#define CLR_REG			0x0
 59#define I2CMCF_BIT		0x0080
 60#define I2CMIF_BIT		0x0002
 61#define I2CMAL_BIT		0x0010
 62#define I2CBMFI_BIT		0x0001
 63#define I2CBMAL_BIT		0x0002
 64#define I2CBMNA_BIT		0x0004
 65#define I2CBMTO_BIT		0x0008
 66#define I2CBMIS_BIT		0x0010
 67#define I2CESRFI_BIT		0X0001
 68#define I2CESRTO_BIT		0x0002
 69#define I2CESRFIIE_BIT		0x1
 70#define I2CESRTOIE_BIT		0x2
 71#define I2CBMDZ_BIT		0x0040
 72#define I2CBMAG_BIT		0x0020
 73#define I2CMBB_BIT		0x0020
 74#define BUFFER_MODE_MASK	(I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
 75				I2CBMTO_BIT | I2CBMIS_BIT)
 76#define FAST_MODE_CLK		400
 77#define FAST_MODE_EN		0x0001
 78#define SUB_ADDR_LEN_MAX	4
 79#define BUF_LEN_MAX		32
 80#define PCH_BUFFER_MODE		0x1
 81#define EEPROM_SW_RST_MODE	0x0002
 82#define NORMAL_INTR_ENBL	0x0300
 83#define EEPROM_RST_INTR_ENBL	(I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 84#define EEPROM_RST_INTR_DISBL	0x0
 85#define BUFFER_MODE_INTR_ENBL	0x001F
 86#define BUFFER_MODE_INTR_DISBL	0x0
 87#define NORMAL_MODE		0x0
 88#define BUFFER_MODE		0x1
 89#define EEPROM_SR_MODE		0x2
 90#define I2C_TX_MODE		0x0010
 91#define PCH_BUF_TX		0xFFF7
 92#define PCH_BUF_RD		0x0008
 93#define I2C_ERROR_MASK	(I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 94			I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 95#define I2CMAL_EVENT		0x0001
 96#define I2CMCF_EVENT		0x0002
 97#define I2CBMFI_EVENT		0x0004
 98#define I2CBMAL_EVENT		0x0008
 99#define I2CBMNA_EVENT		0x0010
100#define I2CBMTO_EVENT		0x0020
101#define I2CBMIS_EVENT		0x0040
102#define I2CESRFI_EVENT		0x0080
103#define I2CESRTO_EVENT		0x0100
104#define PCI_DEVICE_ID_PCH_I2C	0x8817
105
106#define pch_dbg(adap, fmt, arg...)  \
107	dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
108
109#define pch_err(adap, fmt, arg...)  \
110	dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
111
112#define pch_pci_err(pdev, fmt, arg...)  \
113	dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
114
115#define pch_pci_dbg(pdev, fmt, arg...)  \
116	dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
117
118/*
119Set the number of I2C instance max
120Intel EG20T PCH :		1ch
121LAPIS Semiconductor ML7213 IOH :	2ch
122LAPIS Semiconductor ML7831 IOH :	1ch
123*/
124#define PCH_I2C_MAX_DEV			2
125
126/**
127 * struct i2c_algo_pch_data - for I2C driver functionalities
128 * @pch_adapter:		stores the reference to i2c_adapter structure
129 * @p_adapter_info:		stores the reference to adapter_info structure
130 * @pch_base_address:		specifies the remapped base address
131 * @pch_buff_mode_en:		specifies if buffer mode is enabled
132 * @pch_event_flag:		specifies occurrence of interrupt events
133 * @pch_i2c_xfer_in_progress:	specifies whether the transfer is completed
134 */
135struct i2c_algo_pch_data {
136	struct i2c_adapter pch_adapter;
137	struct adapter_info *p_adapter_info;
138	void __iomem *pch_base_address;
139	int pch_buff_mode_en;
140	u32 pch_event_flag;
141	bool pch_i2c_xfer_in_progress;
142};
143
144/**
145 * struct adapter_info - This structure holds the adapter information for the
146 *			 PCH i2c controller
147 * @pch_data:		stores a list of i2c_algo_pch_data
148 * @pch_i2c_suspended:	specifies whether the system is suspended or not
149 *			perhaps with more lines and words.
150 * @ch_num:		specifies the number of i2c instance
151 *
152 * pch_data has as many elements as maximum I2C channels
153 */
154struct adapter_info {
155	struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
156	bool pch_i2c_suspended;
157	int ch_num;
158};
159
160
161static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
162static int pch_clk = 50000;	/* specifies I2C clock speed in KHz */
163static wait_queue_head_t pch_event;
164static DEFINE_MUTEX(pch_mutex);
165
166/* Definition for ML7213 by LAPIS Semiconductor */
167#define PCI_DEVICE_ID_ML7213_I2C	0x802D
168#define PCI_DEVICE_ID_ML7223_I2C	0x8010
169#define PCI_DEVICE_ID_ML7831_I2C	0x8817
170
171static const struct pci_device_id pch_pcidev_id[] = {
172	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
173	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
174	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
175	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
176	{0,}
177};
178MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
179
180static irqreturn_t pch_i2c_handler(int irq, void *pData);
181
182static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
183{
184	u32 val;
185	val = ioread32(addr + offset);
186	val |= bitmask;
187	iowrite32(val, addr + offset);
188}
189
190static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
191{
192	u32 val;
193	val = ioread32(addr + offset);
194	val &= (~bitmask);
195	iowrite32(val, addr + offset);
196}
197
198/**
199 * pch_i2c_init() - hardware initialization of I2C module
200 * @adap:	Pointer to struct i2c_algo_pch_data.
201 */
202static void pch_i2c_init(struct i2c_algo_pch_data *adap)
203{
204	void __iomem *p = adap->pch_base_address;
205	u32 pch_i2cbc;
206	u32 pch_i2ctmr;
207	u32 reg_value;
208
209	/* reset I2C controller */
210	iowrite32(0x01, p + PCH_I2CSRST);
211	msleep(20);
212	iowrite32(0x0, p + PCH_I2CSRST);
213
214	/* Initialize I2C registers */
215	iowrite32(0x21, p + PCH_I2CNF);
216
217	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
218
219	if (pch_i2c_speed != 400)
220		pch_i2c_speed = 100;
221
222	reg_value = PCH_I2CCTL_I2CMEN;
223	if (pch_i2c_speed == FAST_MODE_CLK) {
224		reg_value |= FAST_MODE_EN;
225		pch_dbg(adap, "Fast mode enabled\n");
226	}
227
228	if (pch_clk > PCH_MAX_CLK)
229		pch_clk = 62500;
230
231	pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
232	/* Set transfer speed in I2CBC */
233	iowrite32(pch_i2cbc, p + PCH_I2CBC);
234
235	pch_i2ctmr = (pch_clk) / 8;
236	iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
237
238	reg_value |= NORMAL_INTR_ENBL;	/* Enable interrupts in normal mode */
239	iowrite32(reg_value, p + PCH_I2CCTL);
240
241	pch_dbg(adap,
242		"I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
243		ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
244
245	init_waitqueue_head(&pch_event);
246}
247
248/**
249 * pch_i2c_wait_for_bus_idle() - check the status of bus.
250 * @adap:	Pointer to struct i2c_algo_pch_data.
251 * @timeout:	waiting time counter (ms).
252 */
253static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
254				     s32 timeout)
255{
256	void __iomem *p = adap->pch_base_address;
257	int schedule = 0;
258	unsigned long end = jiffies + msecs_to_jiffies(timeout);
259
260	while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
261		if (time_after(jiffies, end)) {
262			pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
263			pch_err(adap, "%s: Timeout Error.return%d\n",
264					__func__, -ETIME);
265			pch_i2c_init(adap);
266
267			return -ETIME;
268		}
269
270		if (!schedule)
271			/* Retry after some usecs */
272			udelay(5);
273		else
274			/* Wait a bit more without consuming CPU */
275			usleep_range(20, 1000);
276
277		schedule = 1;
278	}
279
280	return 0;
281}
282
283/**
284 * pch_i2c_start() - Generate I2C start condition in normal mode.
285 * @adap:	Pointer to struct i2c_algo_pch_data.
286 *
287 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
288 */
289static void pch_i2c_start(struct i2c_algo_pch_data *adap)
290{
291	void __iomem *p = adap->pch_base_address;
292	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
293	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
294}
295
296/**
297 * pch_i2c_stop() - generate stop condition in normal mode.
298 * @adap:	Pointer to struct i2c_algo_pch_data.
299 */
300static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
301{
302	void __iomem *p = adap->pch_base_address;
303	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
304	/* clear the start bit */
305	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
306}
307
308static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
309{
310	long ret;
311	void __iomem *p = adap->pch_base_address;
312
313	ret = wait_event_timeout(pch_event,
314			(adap->pch_event_flag != 0), msecs_to_jiffies(1000));
315	if (!ret) {
316		pch_err(adap, "%s:wait-event timeout\n", __func__);
317		adap->pch_event_flag = 0;
318		pch_i2c_stop(adap);
319		pch_i2c_init(adap);
320		return -ETIMEDOUT;
321	}
322
323	if (adap->pch_event_flag & I2C_ERROR_MASK) {
324		pch_err(adap, "Lost Arbitration\n");
325		adap->pch_event_flag = 0;
326		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
327		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
328		pch_i2c_init(adap);
329		return -EAGAIN;
330	}
331
332	adap->pch_event_flag = 0;
333
334	if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
335		pch_dbg(adap, "Receive NACK for slave address setting\n");
336		return -ENXIO;
337	}
338
339	return 0;
340}
341
342/**
343 * pch_i2c_repstart() - generate repeated start condition in normal mode
344 * @adap:	Pointer to struct i2c_algo_pch_data.
345 */
346static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
347{
348	void __iomem *p = adap->pch_base_address;
349	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
350	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
351}
352
353/**
354 * pch_i2c_writebytes() - write data to I2C bus in normal mode
355 * @i2c_adap:	Pointer to the struct i2c_adapter.
356 * @msgs:	Pointer to the i2c message structure.
357 * @last:	specifies whether last message or not.
358 *		In the case of compound mode it will be 1 for last message,
359 *		otherwise 0.
360 * @first:	specifies whether first message or not.
361 *		1 for first message otherwise 0.
362 */
363static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
364			      struct i2c_msg *msgs, u32 last, u32 first)
365{
366	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
367	u8 *buf;
368	u32 length;
369	s32 wrcount;
370	s32 rtn;
371	void __iomem *p = adap->pch_base_address;
372
373	length = msgs->len;
374	buf = msgs->buf;
375
376	/* enable master tx */
377	pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
378
379	pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
380		length);
381
382	if (first) {
383		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
384			return -ETIME;
385	}
386
387	if (msgs->flags & I2C_M_TEN) {
388		iowrite32(i2c_10bit_addr_hi_from_msg(msgs), p + PCH_I2CDR);
389		if (first)
390			pch_i2c_start(adap);
391
392		rtn = pch_i2c_wait_for_check_xfer(adap);
393		if (rtn)
394			return rtn;
395
396		iowrite32(i2c_10bit_addr_lo_from_msg(msgs), p + PCH_I2CDR);
397	} else {
398		/* set 7 bit slave address and R/W bit as 0 */
399		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
400		if (first)
401			pch_i2c_start(adap);
402	}
403
404	rtn = pch_i2c_wait_for_check_xfer(adap);
405	if (rtn)
406		return rtn;
407
408	for (wrcount = 0; wrcount < length; ++wrcount) {
409		/* write buffer value to I2C data register */
410		iowrite32(buf[wrcount], p + PCH_I2CDR);
411		pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
412
413		rtn = pch_i2c_wait_for_check_xfer(adap);
414		if (rtn)
415			return rtn;
416
417		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
418		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
419	}
420
421	/* check if this is the last message */
422	if (last)
423		pch_i2c_stop(adap);
424	else
425		pch_i2c_repstart(adap);
426
427	pch_dbg(adap, "return=%d\n", wrcount);
428
429	return wrcount;
430}
431
432/**
433 * pch_i2c_sendack() - send ACK
434 * @adap:	Pointer to struct i2c_algo_pch_data.
435 */
436static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
437{
438	void __iomem *p = adap->pch_base_address;
439	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
440	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
441}
442
443/**
444 * pch_i2c_sendnack() - send NACK
445 * @adap:	Pointer to struct i2c_algo_pch_data.
446 */
447static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
448{
449	void __iomem *p = adap->pch_base_address;
450	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
451	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
452}
453
454/**
455 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
456 * @adap:	Pointer to struct i2c_algo_pch_data.
457 *
458 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
459 */
460static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
461{
462	void __iomem *p = adap->pch_base_address;
463	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
464	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
465}
466
467/**
468 * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
469 * @i2c_adap:	Pointer to the struct i2c_adapter.
470 * @msgs:	Pointer to i2c_msg structure.
471 * @last:	specifies whether last message or not.
472 * @first:	specifies whether first message or not.
473 */
474static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
475			     u32 last, u32 first)
476{
477	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
478
479	u8 *buf;
480	u32 count;
481	u32 length;
482	void __iomem *p = adap->pch_base_address;
483	s32 rtn;
484
485	length = msgs->len;
486	buf = msgs->buf;
487
488	/* enable master reception */
489	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
490
491	if (first) {
492		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
493			return -ETIME;
494	}
495
496	if (msgs->flags & I2C_M_TEN) {
497		iowrite32(i2c_10bit_addr_hi_from_msg(msgs) & ~I2C_M_RD, p + PCH_I2CDR);
498		if (first)
499			pch_i2c_start(adap);
500
501		rtn = pch_i2c_wait_for_check_xfer(adap);
502		if (rtn)
503			return rtn;
504
505		iowrite32(i2c_10bit_addr_lo_from_msg(msgs), p + PCH_I2CDR);
506
507		pch_i2c_restart(adap);
508
509		rtn = pch_i2c_wait_for_check_xfer(adap);
510		if (rtn)
511			return rtn;
512
513		iowrite32(i2c_10bit_addr_hi_from_msg(msgs), p + PCH_I2CDR);
514	} else {
515		/* 7 address bits + R/W bit */
516		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
517	}
518
519	/* check if it is the first message */
520	if (first)
521		pch_i2c_start(adap);
522
523	rtn = pch_i2c_wait_for_check_xfer(adap);
524	if (rtn)
525		return rtn;
526
527	if (length == 0) {
528		pch_i2c_stop(adap);
529		ioread32(p + PCH_I2CDR); /* Dummy read needs */
530
531		count = length;
532	} else {
533		int read_index;
534		int loop;
535		pch_i2c_sendack(adap);
536
537		/* Dummy read */
538		for (loop = 1, read_index = 0; loop < length; loop++) {
539			buf[read_index] = ioread32(p + PCH_I2CDR);
540
541			if (loop != 1)
542				read_index++;
543
544			rtn = pch_i2c_wait_for_check_xfer(adap);
545			if (rtn)
546				return rtn;
547		}	/* end for */
548
549		pch_i2c_sendnack(adap);
550
551		buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
552
553		if (length != 1)
554			read_index++;
555
556		rtn = pch_i2c_wait_for_check_xfer(adap);
557		if (rtn)
558			return rtn;
559
560		if (last)
561			pch_i2c_stop(adap);
562		else
563			pch_i2c_repstart(adap);
564
565		buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
566		count = read_index;
567	}
568
569	return count;
570}
571
572/**
573 * pch_i2c_cb() - Interrupt handler Call back function
574 * @adap:	Pointer to struct i2c_algo_pch_data.
575 */
576static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
577{
578	u32 sts;
579	void __iomem *p = adap->pch_base_address;
580
581	sts = ioread32(p + PCH_I2CSR);
582	sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
583	if (sts & I2CMAL_BIT)
584		adap->pch_event_flag |= I2CMAL_EVENT;
585
586	if (sts & I2CMCF_BIT)
587		adap->pch_event_flag |= I2CMCF_EVENT;
588
589	/* clear the applicable bits */
590	pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
591
592	pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
593
594	wake_up(&pch_event);
595}
596
597/**
598 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
599 * @irq:	irq number.
600 * @pData:	cookie passed back to the handler function.
601 */
602static irqreturn_t pch_i2c_handler(int irq, void *pData)
603{
604	u32 reg_val;
605	int flag;
606	int i;
607	struct adapter_info *adap_info = pData;
608	void __iomem *p;
609	u32 mode;
610
611	for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
612		p = adap_info->pch_data[i].pch_base_address;
613		mode = ioread32(p + PCH_I2CMOD);
614		mode &= BUFFER_MODE | EEPROM_SR_MODE;
615		if (mode != NORMAL_MODE) {
616			pch_err(adap_info->pch_data,
617				"I2C-%d mode(%d) is not supported\n", mode, i);
618			continue;
619		}
620		reg_val = ioread32(p + PCH_I2CSR);
621		if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
622			pch_i2c_cb(&adap_info->pch_data[i]);
623			flag = 1;
624		}
625	}
626
627	return flag ? IRQ_HANDLED : IRQ_NONE;
628}
629
630/**
631 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
632 * @i2c_adap:	Pointer to the struct i2c_adapter.
633 * @msgs:	Pointer to i2c_msg structure.
634 * @num:	number of messages.
635 */
636static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
637			struct i2c_msg *msgs, s32 num)
638{
639	struct i2c_msg *pmsg;
640	u32 i = 0;
641	u32 status;
642	s32 ret;
643
644	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
645
646	ret = mutex_lock_interruptible(&pch_mutex);
647	if (ret)
648		return ret;
649
650	if (adap->p_adapter_info->pch_i2c_suspended) {
651		mutex_unlock(&pch_mutex);
652		return -EBUSY;
653	}
654
655	pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
656		adap->p_adapter_info->pch_i2c_suspended);
657	/* transfer not completed */
658	adap->pch_i2c_xfer_in_progress = true;
659
660	for (i = 0; i < num && ret >= 0; i++) {
661		pmsg = &msgs[i];
662		pmsg->flags |= adap->pch_buff_mode_en;
663		status = pmsg->flags;
664		pch_dbg(adap,
665			"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
666
667		if ((status & (I2C_M_RD)) != false) {
668			ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
669						(i == 0));
670		} else {
671			ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
672						 (i == 0));
673		}
674	}
675
676	adap->pch_i2c_xfer_in_progress = false;	/* transfer completed */
677
678	mutex_unlock(&pch_mutex);
679
680	return (ret < 0) ? ret : num;
681}
682
683/**
684 * pch_i2c_func() - return the functionality of the I2C driver
685 * @adap:	Pointer to struct i2c_algo_pch_data.
686 */
687static u32 pch_i2c_func(struct i2c_adapter *adap)
688{
689	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
690}
691
692static const struct i2c_algorithm pch_algorithm = {
693	.xfer = pch_i2c_xfer,
694	.functionality = pch_i2c_func
695};
696
697/**
698 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
699 * @adap:	Pointer to struct i2c_algo_pch_data.
700 */
701static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
702{
703	void __iomem *p = adap->pch_base_address;
704
705	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
706
707	iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
708
709	iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
710}
711
712static int pch_i2c_probe(struct pci_dev *pdev,
713				   const struct pci_device_id *id)
714{
715	void __iomem *base_addr;
716	int ret;
717	int i, j;
718	struct adapter_info *adap_info;
719	struct i2c_adapter *pch_adap;
720
721	pch_pci_dbg(pdev, "Entered.\n");
722
723	adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
724	if (adap_info == NULL)
725		return -ENOMEM;
726
727	ret = pci_enable_device(pdev);
728	if (ret) {
729		pch_pci_err(pdev, "pci_enable_device FAILED\n");
730		goto err_pci_enable;
731	}
732
733	ret = pci_request_regions(pdev, KBUILD_MODNAME);
734	if (ret) {
735		pch_pci_err(pdev, "pci_request_regions FAILED\n");
736		goto err_pci_req;
737	}
738
739	base_addr = pci_iomap(pdev, 1, 0);
740
741	if (base_addr == NULL) {
742		pch_pci_err(pdev, "pci_iomap FAILED\n");
743		ret = -ENOMEM;
744		goto err_pci_iomap;
745	}
746
747	/* Set the number of I2C channel instance */
748	adap_info->ch_num = id->driver_data;
749
750	for (i = 0; i < adap_info->ch_num; i++) {
751		pch_adap = &adap_info->pch_data[i].pch_adapter;
752		adap_info->pch_i2c_suspended = false;
753
754		adap_info->pch_data[i].p_adapter_info = adap_info;
755
756		pch_adap->owner = THIS_MODULE;
757		pch_adap->class = I2C_CLASS_HWMON;
758		strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
759		pch_adap->algo = &pch_algorithm;
760		pch_adap->algo_data = &adap_info->pch_data[i];
761
762		/* base_addr + offset; */
763		adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
764
765		pch_adap->dev.of_node = pdev->dev.of_node;
766		pch_adap->dev.parent = &pdev->dev;
767	}
768
769	ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
770		  KBUILD_MODNAME, adap_info);
771	if (ret) {
772		pch_pci_err(pdev, "request_irq FAILED\n");
773		goto err_request_irq;
774	}
775
776	for (i = 0; i < adap_info->ch_num; i++) {
777		pch_adap = &adap_info->pch_data[i].pch_adapter;
778
779		pch_i2c_init(&adap_info->pch_data[i]);
780
781		pch_adap->nr = i;
782		ret = i2c_add_numbered_adapter(pch_adap);
783		if (ret) {
784			pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
785			goto err_add_adapter;
786		}
787	}
788
789	pci_set_drvdata(pdev, adap_info);
790	pch_pci_dbg(pdev, "returns %d.\n", ret);
791	return 0;
792
793err_add_adapter:
794	for (j = 0; j < i; j++)
795		i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
796	free_irq(pdev->irq, adap_info);
797err_request_irq:
798	pci_iounmap(pdev, base_addr);
799err_pci_iomap:
800	pci_release_regions(pdev);
801err_pci_req:
802	pci_disable_device(pdev);
803err_pci_enable:
804	kfree(adap_info);
805	return ret;
806}
807
808static void pch_i2c_remove(struct pci_dev *pdev)
809{
810	int i;
811	struct adapter_info *adap_info = pci_get_drvdata(pdev);
812
813	free_irq(pdev->irq, adap_info);
814
815	for (i = 0; i < adap_info->ch_num; i++) {
816		pch_i2c_disbl_int(&adap_info->pch_data[i]);
817		i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
818	}
819
820	if (adap_info->pch_data[0].pch_base_address)
821		pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
822
823	for (i = 0; i < adap_info->ch_num; i++)
824		adap_info->pch_data[i].pch_base_address = NULL;
825
826	pci_release_regions(pdev);
827
828	pci_disable_device(pdev);
829	kfree(adap_info);
830}
831
832static int __maybe_unused pch_i2c_suspend(struct device *dev)
833{
834	int i;
835	struct pci_dev *pdev = to_pci_dev(dev);
836	struct adapter_info *adap_info = pci_get_drvdata(pdev);
837	void __iomem *p = adap_info->pch_data[0].pch_base_address;
838
839	adap_info->pch_i2c_suspended = true;
840
841	for (i = 0; i < adap_info->ch_num; i++) {
842		while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
843			/* Wait until all channel transfers are completed */
844			msleep(20);
845		}
846	}
847
848	/* Disable the i2c interrupts */
849	for (i = 0; i < adap_info->ch_num; i++)
850		pch_i2c_disbl_int(&adap_info->pch_data[i]);
851
852	pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
853		"invoked function pch_i2c_disbl_int successfully\n",
854		ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
855		ioread32(p + PCH_I2CESRSTA));
856
857	return 0;
858}
859
860static int __maybe_unused pch_i2c_resume(struct device *dev)
861{
862	int i;
863	struct adapter_info *adap_info = dev_get_drvdata(dev);
864
865	for (i = 0; i < adap_info->ch_num; i++)
866		pch_i2c_init(&adap_info->pch_data[i]);
867
868	adap_info->pch_i2c_suspended = false;
869
870	return 0;
871}
872
873static SIMPLE_DEV_PM_OPS(pch_i2c_pm_ops, pch_i2c_suspend, pch_i2c_resume);
874
875static struct pci_driver pch_pcidriver = {
876	.name = KBUILD_MODNAME,
877	.id_table = pch_pcidev_id,
878	.probe = pch_i2c_probe,
879	.remove = pch_i2c_remove,
880	.driver.pm = &pch_i2c_pm_ops,
881};
882
883module_pci_driver(pch_pcidriver);
884
885MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
886MODULE_LICENSE("GPL");
887MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
888module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
889module_param(pch_clk, int, (S_IRUSR | S_IWUSR));