i2c-designware-pcidrv.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Synopsys DesignWare I2C adapter driver (master only).
  4 *
  5 * Based on the TI DAVINCI I2C adapter driver.
  6 *
  7 * Copyright (C) 2006 Texas Instruments.
  8 * Copyright (C) 2007 MontaVista Software Inc.
  9 * Copyright (C) 2009 Provigent Ltd.
 10 * Copyright (C) 2011, 2015, 2016 Intel Corporation.
 11 */
 12#include <linux/delay.h>
 13#include <linux/err.h>
 14#include <linux/errno.h>
 15#include <linux/i2c.h>
 16#include <linux/interrupt.h>
 17#include <linux/io.h>
 18#include <linux/kernel.h>
 19#include <linux/module.h>
 20#include <linux/pci.h>
 21#include <linux/pm.h>
 22#include <linux/pm_runtime.h>
 23#include <linux/power_supply.h>
 24#include <linux/sched.h>
 25#include <linux/slab.h>
 26
 27#include "i2c-designware-core.h"
 28#include "i2c-ccgx-ucsi.h"
 29
 30#define DRIVER_NAME "i2c-designware-pci"
 31
 32enum dw_pci_ctl_id_t {
 33	medfield,
 34	merrifield,
 35	baytrail,
 36	cherrytrail,
 37	haswell,
 38	elkhartlake,
 39	navi_amd,
 40};
 41
 42/*
 43 * This is a legacy structure to describe the hardware counters
 44 * to configure signal timings on the bus. For Device Tree platforms
 45 * one should use the respective properties and for ACPI there is
 46 * a set of ACPI methods that provide these counters. No new
 47 * platform should use this structure.
 48 */
 49struct dw_scl_sda_cfg {
 50	u16 ss_hcnt;
 51	u16 fs_hcnt;
 52	u16 ss_lcnt;
 53	u16 fs_lcnt;
 54	u32 sda_hold_time;
 55};
 56
 57struct dw_pci_controller {
 58	u32 bus_num;
 59	u32 flags;
 60	struct dw_scl_sda_cfg *scl_sda_cfg;
 61	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
 62	u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
 63};
 64
 65/* Merrifield HCNT/LCNT/SDA hold time */
 66static struct dw_scl_sda_cfg mrfld_config = {
 67	.ss_hcnt = 0x2f8,
 68	.fs_hcnt = 0x87,
 69	.ss_lcnt = 0x37b,
 70	.fs_lcnt = 0x10a,
 71};
 72
 73/* BayTrail HCNT/LCNT/SDA hold time */
 74static struct dw_scl_sda_cfg byt_config = {
 75	.ss_hcnt = 0x200,
 76	.fs_hcnt = 0x55,
 77	.ss_lcnt = 0x200,
 78	.fs_lcnt = 0x99,
 79	.sda_hold_time = 0x6,
 80};
 81
 82/* Haswell HCNT/LCNT/SDA hold time */
 83static struct dw_scl_sda_cfg hsw_config = {
 84	.ss_hcnt = 0x01b0,
 85	.fs_hcnt = 0x48,
 86	.ss_lcnt = 0x01fb,
 87	.fs_lcnt = 0xa0,
 88	.sda_hold_time = 0x9,
 89};
 90
 91/* NAVI-AMD HCNT/LCNT/SDA hold time */
 92static struct dw_scl_sda_cfg navi_amd_config = {
 93	.ss_hcnt = 0x1ae,
 94	.ss_lcnt = 0x23a,
 95	.sda_hold_time = 0x9,
 96};
 97
 98static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
 99{
100	return 25000;
101}
102
103static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
104{
105	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
106
107	switch (pdev->device) {
108	case 0x0817:
109		dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
110		fallthrough;
111	case 0x0818:
112	case 0x0819:
113		c->bus_num = pdev->device - 0x817 + 3;
114		return 0;
115	case 0x082C:
116	case 0x082D:
117	case 0x082E:
118		c->bus_num = pdev->device - 0x82C + 0;
119		return 0;
120	}
121	return -ENODEV;
122}
123
124static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
125{
126	/*
127	 * On Intel Merrifield the user visible i2c buses are enumerated
128	 * [1..7]. So, we add 1 to shift the default range. Besides that the
129	 * first PCI slot provides 4 functions, that's why we have to add 0 to
130	 * the first slot and 4 to the next one.
131	 */
132	switch (PCI_SLOT(pdev->devfn)) {
133	case 8:
134		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
135		return 0;
136	case 9:
137		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
138		return 0;
139	}
140	return -ENODEV;
141}
142
143static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
144{
145	return 100000;
146}
147
148static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
149{
150	return 100000;
151}
152
153static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
154{
155	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
156
157	dev->flags |= MODEL_AMD_NAVI_GPU | ACCESS_POLLING;
158	dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
159	return 0;
160}
161
162static struct dw_pci_controller dw_pci_controllers[] = {
163	[medfield] = {
164		.bus_num = -1,
165		.setup = mfld_setup,
166		.get_clk_rate_khz = mfld_get_clk_rate_khz,
167	},
168	[merrifield] = {
169		.bus_num = -1,
170		.scl_sda_cfg = &mrfld_config,
171		.setup = mrfld_setup,
172	},
173	[baytrail] = {
174		.bus_num = -1,
175		.scl_sda_cfg = &byt_config,
176	},
177	[haswell] = {
178		.bus_num = -1,
179		.scl_sda_cfg = &hsw_config,
180	},
181	[cherrytrail] = {
182		.bus_num = -1,
183		.scl_sda_cfg = &byt_config,
184	},
185	[elkhartlake] = {
186		.bus_num = -1,
187		.get_clk_rate_khz = ehl_get_clk_rate_khz,
188	},
189	[navi_amd] = {
190		.bus_num = -1,
191		.scl_sda_cfg = &navi_amd_config,
192		.setup =  navi_amd_setup,
193		.get_clk_rate_khz = navi_amd_get_clk_rate_khz,
194	},
195};
196
197static const struct property_entry dgpu_properties[] = {
198	/* USB-C doesn't power the system */
199	PROPERTY_ENTRY_U8("scope", POWER_SUPPLY_SCOPE_DEVICE),
200	{}
201};
202
203static const struct software_node dgpu_node = {
204	.properties = dgpu_properties,
205};
206
207static int i2c_dw_pci_probe(struct pci_dev *pdev,
208			    const struct pci_device_id *id)
209{
210	struct device *device = &pdev->dev;
211	struct dw_i2c_dev *dev;
212	struct i2c_adapter *adap;
213	int r;
214	struct dw_pci_controller *controller;
215	struct dw_scl_sda_cfg *cfg;
216
217	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers))
218		return dev_err_probe(device, -EINVAL, "Invalid driver data %ld\n",
219				     id->driver_data);
220
221	controller = &dw_pci_controllers[id->driver_data];
222
223	r = pcim_enable_device(pdev);
224	if (r)
225		return dev_err_probe(device, r, "Failed to enable I2C PCI device\n");
226
227	pci_set_master(pdev);
228
229	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
230	if (r)
231		return dev_err_probe(device, r, "I/O memory remapping failed\n");
232
233	dev = devm_kzalloc(device, sizeof(*dev), GFP_KERNEL);
234	if (!dev)
235		return -ENOMEM;
236
237	r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
238	if (r < 0)
239		return r;
240
241	dev->get_clk_rate_khz = controller->get_clk_rate_khz;
242	dev->base = pcim_iomap_table(pdev)[0];
243	dev->dev = device;
244	dev->irq = pci_irq_vector(pdev, 0);
245	dev->flags |= controller->flags;
246
247	pci_set_drvdata(pdev, dev);
248
249	if (controller->setup) {
250		r = controller->setup(pdev, controller);
251		if (r)
252			return r;
253	}
254
255	r = i2c_dw_fw_parse_and_configure(dev);
256	if (r)
257		return r;
258
259	i2c_dw_configure(dev);
260
261	if (controller->scl_sda_cfg) {
262		cfg = controller->scl_sda_cfg;
263		dev->ss_hcnt = cfg->ss_hcnt;
264		dev->fs_hcnt = cfg->fs_hcnt;
265		dev->ss_lcnt = cfg->ss_lcnt;
266		dev->fs_lcnt = cfg->fs_lcnt;
267		dev->sda_hold_time = cfg->sda_hold_time;
268	}
269
270	adap = &dev->adapter;
271	adap->owner = THIS_MODULE;
272	adap->class = 0;
273	adap->nr = controller->bus_num;
274
275	r = i2c_dw_probe(dev);
276	if (r)
277		return r;
278
279	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
280		dev->slave = i2c_new_ccgx_ucsi(&dev->adapter, dev->irq, &dgpu_node);
281		if (IS_ERR(dev->slave)) {
282			i2c_del_adapter(&dev->adapter);
283			return dev_err_probe(device, PTR_ERR(dev->slave),
284					     "register UCSI failed\n");
285		}
286	}
287
288	pm_runtime_set_autosuspend_delay(device, 1000);
289	pm_runtime_use_autosuspend(device);
290	pm_runtime_put_autosuspend(device);
291	pm_runtime_allow(device);
292
293	return 0;
294}
295
296static void i2c_dw_pci_remove(struct pci_dev *pdev)
297{
298	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
299	struct device *device = &pdev->dev;
300
301	i2c_dw_disable(dev);
302
303	pm_runtime_forbid(device);
304	pm_runtime_get_noresume(device);
305
306	i2c_del_adapter(&dev->adapter);
307}
308
309static const struct pci_device_id i2c_designware_pci_ids[] = {
310	/* Medfield */
311	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
312	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
313	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
314	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
315	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
316	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
317	/* Merrifield */
318	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
319	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
320	/* Baytrail */
321	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
322	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
323	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
324	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
325	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
326	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
327	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
328	/* Haswell */
329	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
330	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
331	/* Braswell / Cherrytrail */
332	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
333	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
334	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
335	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
336	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
337	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
338	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
339	/* Elkhart Lake (PSE I2C) */
340	{ PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
341	{ PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
342	{ PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
343	{ PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
344	{ PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
345	{ PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
346	{ PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
347	{ PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
348	/* AMD NAVI */
349	{ PCI_VDEVICE(ATI,  0x7314), navi_amd },
350	{ PCI_VDEVICE(ATI,  0x73a4), navi_amd },
351	{ PCI_VDEVICE(ATI,  0x73e4), navi_amd },
352	{ PCI_VDEVICE(ATI,  0x73c4), navi_amd },
353	{ PCI_VDEVICE(ATI,  0x7444), navi_amd },
354	{ PCI_VDEVICE(ATI,  0x7464), navi_amd },
355	{}
356};
357MODULE_DEVICE_TABLE(pci, i2c_designware_pci_ids);
358
359static struct pci_driver dw_i2c_driver = {
360	.name		= DRIVER_NAME,
361	.probe		= i2c_dw_pci_probe,
362	.remove		= i2c_dw_pci_remove,
363	.driver         = {
364		.pm	= pm_ptr(&i2c_dw_dev_pm_ops),
365	},
366	.id_table	= i2c_designware_pci_ids,
367};
368module_pci_driver(dw_i2c_driver);
369
370MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
371MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
372MODULE_LICENSE("GPL");
373MODULE_IMPORT_NS("I2C_DW");
374MODULE_IMPORT_NS("I2C_DW_COMMON");