i2c-bcm2835.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * BCM2835 I2C controller driver
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/clkdev.h>
  8#include <linux/clk-provider.h>
  9#include <linux/completion.h>
 10#include <linux/err.h>
 11#include <linux/i2c.h>
 12#include <linux/interrupt.h>
 13#include <linux/io.h>
 14#include <linux/module.h>
 15#include <linux/of.h>
 16#include <linux/platform_device.h>
 17#include <linux/slab.h>
 18
 19#define BCM2835_I2C_C		0x0
 20#define BCM2835_I2C_S		0x4
 21#define BCM2835_I2C_DLEN	0x8
 22#define BCM2835_I2C_A		0xc
 23#define BCM2835_I2C_FIFO	0x10
 24#define BCM2835_I2C_DIV		0x14
 25#define BCM2835_I2C_DEL		0x18
 26/*
 27 * 16-bit field for the number of SCL cycles to wait after rising SCL
 28 * before deciding the target is not responding. 0 disables the
 29 * timeout detection.
 30 */
 31#define BCM2835_I2C_CLKT	0x1c
 32
 33#define BCM2835_I2C_C_READ	BIT(0)
 34#define BCM2835_I2C_C_CLEAR	BIT(4) /* bits 4 and 5 both clear */
 35#define BCM2835_I2C_C_ST	BIT(7)
 36#define BCM2835_I2C_C_INTD	BIT(8)
 37#define BCM2835_I2C_C_INTT	BIT(9)
 38#define BCM2835_I2C_C_INTR	BIT(10)
 39#define BCM2835_I2C_C_I2CEN	BIT(15)
 40
 41#define BCM2835_I2C_S_TA	BIT(0)
 42#define BCM2835_I2C_S_DONE	BIT(1)
 43#define BCM2835_I2C_S_TXW	BIT(2)
 44#define BCM2835_I2C_S_RXR	BIT(3)
 45#define BCM2835_I2C_S_TXD	BIT(4)
 46#define BCM2835_I2C_S_RXD	BIT(5)
 47#define BCM2835_I2C_S_TXE	BIT(6)
 48#define BCM2835_I2C_S_RXF	BIT(7)
 49#define BCM2835_I2C_S_ERR	BIT(8)
 50#define BCM2835_I2C_S_CLKT	BIT(9)
 51#define BCM2835_I2C_S_LEN	BIT(10) /* Fake bit for SW error reporting */
 52
 53#define BCM2835_I2C_FEDL_SHIFT	16
 54#define BCM2835_I2C_REDL_SHIFT	0
 55
 56#define BCM2835_I2C_CDIV_MIN	0x0002
 57#define BCM2835_I2C_CDIV_MAX	0xFFFE
 58
 59struct bcm2835_i2c_dev {
 60	struct device *dev;
 61	void __iomem *regs;
 62	int irq;
 63	struct i2c_adapter adapter;
 64	struct completion completion;
 65	struct i2c_msg *curr_msg;
 66	struct clk *bus_clk;
 67	int num_msgs;
 68	u32 msg_err;
 69	u8 *msg_buf;
 70	size_t msg_buf_remaining;
 71};
 72
 73static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
 74				      u32 reg, u32 val)
 75{
 76	writel(val, i2c_dev->regs + reg);
 77}
 78
 79static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
 80{
 81	return readl(i2c_dev->regs + reg);
 82}
 83
 84#define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw)
 85struct clk_bcm2835_i2c {
 86	struct clk_hw hw;
 87	struct bcm2835_i2c_dev *i2c_dev;
 88};
 89
 90static int clk_bcm2835_i2c_calc_divider(unsigned long rate,
 91				unsigned long parent_rate)
 92{
 93	u32 divider = DIV_ROUND_UP(parent_rate, rate);
 94
 95	/*
 96	 * Per the datasheet, the register is always interpreted as an even
 97	 * number, by rounding down. In other words, the LSB is ignored. So,
 98	 * if the LSB is set, increment the divider to avoid any issue.
 99	 */
100	if (divider & 1)
101		divider++;
102	if ((divider < BCM2835_I2C_CDIV_MIN) ||
103	    (divider > BCM2835_I2C_CDIV_MAX))
104		return -EINVAL;
105
106	return divider;
107}
108
109static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate,
110				unsigned long parent_rate)
111{
112	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
113	u32 redl, fedl;
114	u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
115
116	if (divider == -EINVAL)
117		return -EINVAL;
118
119	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
120
121	/*
122	 * Number of core clocks to wait after falling edge before
123	 * outputting the next data bit.  Note that both FEDL and REDL
124	 * can't be greater than CDIV/2.
125	 */
126	fedl = max(divider / 16, 1u);
127
128	/*
129	 * Number of core clocks to wait after rising edge before
130	 * sampling the next incoming data bit.
131	 */
132	redl = max(divider / 4, 1u);
133
134	bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,
135			   (fedl << BCM2835_I2C_FEDL_SHIFT) |
136			   (redl << BCM2835_I2C_REDL_SHIFT));
137	return 0;
138}
139
140static int clk_bcm2835_i2c_determine_rate(struct clk_hw *hw,
141					  struct clk_rate_request *req)
142{
143	u32 divider = clk_bcm2835_i2c_calc_divider(req->rate, req->best_parent_rate);
144
145	req->rate = DIV_ROUND_UP(req->best_parent_rate, divider);
146
147	return 0;
148}
149
150static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw,
151						unsigned long parent_rate)
152{
153	struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);
154	u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
155
156	return DIV_ROUND_UP(parent_rate, divider);
157}
158
159static const struct clk_ops clk_bcm2835_i2c_ops = {
160	.set_rate = clk_bcm2835_i2c_set_rate,
161	.determine_rate = clk_bcm2835_i2c_determine_rate,
162	.recalc_rate = clk_bcm2835_i2c_recalc_rate,
163};
164
165static struct clk *bcm2835_i2c_register_div(struct device *dev,
166					struct clk *mclk,
167					struct bcm2835_i2c_dev *i2c_dev)
168{
169	struct clk_init_data init;
170	struct clk_bcm2835_i2c *priv;
171	char name[32];
172	const char *mclk_name;
173
174	snprintf(name, sizeof(name), "%s_div", dev_name(dev));
175
176	mclk_name = __clk_get_name(mclk);
177
178	init.ops = &clk_bcm2835_i2c_ops;
179	init.name = name;
180	init.parent_names = (const char* []) { mclk_name };
181	init.num_parents = 1;
182	init.flags = 0;
183
184	priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL);
185	if (priv == NULL)
186		return ERR_PTR(-ENOMEM);
187
188	priv->hw.init = &init;
189	priv->i2c_dev = i2c_dev;
190
191	clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev));
192	return devm_clk_register(dev, &priv->hw);
193}
194
195static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev)
196{
197	u32 val;
198
199	while (i2c_dev->msg_buf_remaining) {
200		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
201		if (!(val & BCM2835_I2C_S_TXD))
202			break;
203		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO,
204				   *i2c_dev->msg_buf);
205		i2c_dev->msg_buf++;
206		i2c_dev->msg_buf_remaining--;
207	}
208}
209
210static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev)
211{
212	u32 val;
213
214	while (i2c_dev->msg_buf_remaining) {
215		val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
216		if (!(val & BCM2835_I2C_S_RXD))
217			break;
218		*i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev,
219						      BCM2835_I2C_FIFO);
220		i2c_dev->msg_buf++;
221		i2c_dev->msg_buf_remaining--;
222	}
223}
224
225/*
226 * Repeated Start Condition (Sr)
227 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it
228 * talks about reading from a target with 10 bit address. This is achieved by
229 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then
230 * issue a read.
231 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the
232 * firmware actually does it using polling and says that it's a workaround for
233 * a problem in the state machine.
234 * It turns out that it is possible to use the TXW interrupt to know when the
235 * transfer is active, provided the FIFO has not been prefilled.
236 */
237
238static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev)
239{
240	u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN;
241	struct i2c_msg *msg = i2c_dev->curr_msg;
242	bool last_msg = (i2c_dev->num_msgs == 1);
243
244	if (!i2c_dev->num_msgs)
245		return;
246
247	i2c_dev->num_msgs--;
248	i2c_dev->msg_buf = msg->buf;
249	i2c_dev->msg_buf_remaining = msg->len;
250
251	if (msg->flags & I2C_M_RD)
252		c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR;
253	else
254		c |= BCM2835_I2C_C_INTT;
255
256	if (last_msg)
257		c |= BCM2835_I2C_C_INTD;
258
259	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
260	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
261	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
262}
263
264static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)
265{
266	i2c_dev->curr_msg = NULL;
267	i2c_dev->num_msgs = 0;
268
269	i2c_dev->msg_buf = NULL;
270	i2c_dev->msg_buf_remaining = 0;
271}
272
273/*
274 * Note about I2C_C_CLEAR on error:
275 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in
276 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through
277 * the state machine to send a NACK and a STOP. Since we're setting CLEAR
278 * without I2CEN, that NACK will be hanging around queued up for next time
279 * we start the engine.
280 */
281
282static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
283{
284	struct bcm2835_i2c_dev *i2c_dev = data;
285	u32 val, err;
286
287	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
288
289	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
290	if (err) {
291		i2c_dev->msg_err = err;
292		goto complete;
293	}
294
295	if (val & BCM2835_I2C_S_DONE) {
296		if (!i2c_dev->curr_msg) {
297			dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
298		} else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
299			bcm2835_drain_rxfifo(i2c_dev);
300			val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
301		}
302
303		if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining)
304			i2c_dev->msg_err = BCM2835_I2C_S_LEN;
305		else
306			i2c_dev->msg_err = 0;
307		goto complete;
308	}
309
310	if (val & BCM2835_I2C_S_TXW) {
311		if (!i2c_dev->msg_buf_remaining) {
312			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
313			goto complete;
314		}
315
316		bcm2835_fill_txfifo(i2c_dev);
317
318		if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) {
319			i2c_dev->curr_msg++;
320			bcm2835_i2c_start_transfer(i2c_dev);
321		}
322
323		return IRQ_HANDLED;
324	}
325
326	if (val & BCM2835_I2C_S_RXR) {
327		if (!i2c_dev->msg_buf_remaining) {
328			i2c_dev->msg_err = val | BCM2835_I2C_S_LEN;
329			goto complete;
330		}
331
332		bcm2835_drain_rxfifo(i2c_dev);
333		return IRQ_HANDLED;
334	}
335
336	return IRQ_NONE;
337
338complete:
339	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR);
340	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT |
341			   BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE);
342	complete(&i2c_dev->completion);
343
344	return IRQ_HANDLED;
345}
346
347static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
348			    int num)
349{
350	struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
351	unsigned long time_left;
352	int i;
353
354	for (i = 0; i < (num - 1); i++)
355		if (msgs[i].flags & I2C_M_RD) {
356			dev_warn_once(i2c_dev->dev,
357				      "only one read message supported, has to be last\n");
358			return -EOPNOTSUPP;
359		}
360
361	i2c_dev->curr_msg = msgs;
362	i2c_dev->num_msgs = num;
363	reinit_completion(&i2c_dev->completion);
364
365	bcm2835_i2c_start_transfer(i2c_dev);
366
367	time_left = wait_for_completion_timeout(&i2c_dev->completion,
368						adap->timeout);
369
370	bcm2835_i2c_finish_transfer(i2c_dev);
371
372	if (!time_left) {
373		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
374				   BCM2835_I2C_C_CLEAR);
375		return -ETIMEDOUT;
376	}
377
378	if (!i2c_dev->msg_err)
379		return num;
380
381	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
382
383	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
384		return -EREMOTEIO;
385
386	return -EIO;
387}
388
389static u32 bcm2835_i2c_func(struct i2c_adapter *adap)
390{
391	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
392}
393
394static const struct i2c_algorithm bcm2835_i2c_algo = {
395	.xfer = bcm2835_i2c_xfer,
396	.functionality = bcm2835_i2c_func,
397};
398
399/*
400 * The BCM2835 was reported to have problems with clock stretching:
401 * https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
402 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272
403 */
404static const struct i2c_adapter_quirks bcm2835_i2c_quirks = {
405	.flags = I2C_AQ_NO_CLK_STRETCH,
406};
407
408static int bcm2835_i2c_probe(struct platform_device *pdev)
409{
410	struct bcm2835_i2c_dev *i2c_dev;
411	int ret;
412	struct i2c_adapter *adap;
413	struct clk *mclk;
414	u32 bus_clk_rate;
415
416	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
417	if (!i2c_dev)
418		return -ENOMEM;
419	platform_set_drvdata(pdev, i2c_dev);
420	i2c_dev->dev = &pdev->dev;
421	init_completion(&i2c_dev->completion);
422
423	i2c_dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
424	if (IS_ERR(i2c_dev->regs))
425		return PTR_ERR(i2c_dev->regs);
426
427	mclk = devm_clk_get(&pdev->dev, NULL);
428	if (IS_ERR(mclk))
429		return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
430				     "Could not get clock\n");
431
432	i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev);
433
434	if (IS_ERR(i2c_dev->bus_clk))
435		return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->bus_clk),
436				     "Could not register clock\n");
437
438	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
439				   &bus_clk_rate);
440	if (ret < 0) {
441		dev_warn(&pdev->dev,
442			 "Could not read clock-frequency property\n");
443		bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
444	}
445
446	ret = clk_set_rate_exclusive(i2c_dev->bus_clk, bus_clk_rate);
447	if (ret < 0)
448		return dev_err_probe(&pdev->dev, ret,
449				     "Could not set clock frequency\n");
450
451	ret = clk_prepare_enable(i2c_dev->bus_clk);
452	if (ret) {
453		dev_err(&pdev->dev, "Couldn't prepare clock");
454		goto err_put_exclusive_rate;
455	}
456
457	i2c_dev->irq = platform_get_irq(pdev, 0);
458	if (i2c_dev->irq < 0) {
459		ret = i2c_dev->irq;
460		goto err_disable_unprepare_clk;
461	}
462
463	ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED,
464			  dev_name(&pdev->dev), i2c_dev);
465	if (ret) {
466		dev_err(&pdev->dev, "Could not request IRQ\n");
467		goto err_disable_unprepare_clk;
468	}
469
470	adap = &i2c_dev->adapter;
471	i2c_set_adapdata(adap, i2c_dev);
472	adap->owner = THIS_MODULE;
473	adap->class = I2C_CLASS_DEPRECATED;
474	snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
475		 of_node_full_name(pdev->dev.of_node));
476	adap->algo = &bcm2835_i2c_algo;
477	adap->dev.parent = &pdev->dev;
478	adap->dev.of_node = pdev->dev.of_node;
479	adap->quirks = of_device_get_match_data(&pdev->dev);
480
481	/*
482	 * Disable the hardware clock stretching timeout. SMBUS
483	 * specifies a limit for how long the device can stretch the
484	 * clock, but core I2C doesn't.
485	 */
486	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_CLKT, 0);
487	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
488
489	ret = i2c_add_adapter(adap);
490	if (ret)
491		goto err_free_irq;
492
493	return 0;
494
495err_free_irq:
496	free_irq(i2c_dev->irq, i2c_dev);
497err_disable_unprepare_clk:
498	clk_disable_unprepare(i2c_dev->bus_clk);
499err_put_exclusive_rate:
500	clk_rate_exclusive_put(i2c_dev->bus_clk);
501
502	return ret;
503}
504
505static void bcm2835_i2c_remove(struct platform_device *pdev)
506{
507	struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
508
509	clk_rate_exclusive_put(i2c_dev->bus_clk);
510	clk_disable_unprepare(i2c_dev->bus_clk);
511
512	free_irq(i2c_dev->irq, i2c_dev);
513	i2c_del_adapter(&i2c_dev->adapter);
514}
515
516static const struct of_device_id bcm2835_i2c_of_match[] = {
517	{ .compatible = "brcm,bcm2711-i2c" },
518	{ .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
519	{},
520};
521MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
522
523static struct platform_driver bcm2835_i2c_driver = {
524	.probe		= bcm2835_i2c_probe,
525	.remove		= bcm2835_i2c_remove,
526	.driver		= {
527		.name	= "i2c-bcm2835",
528		.of_match_table = bcm2835_i2c_of_match,
529	},
530};
531module_platform_driver(bcm2835_i2c_driver);
532
533MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>");
534MODULE_DESCRIPTION("BCM2835 I2C bus adapter");
535MODULE_LICENSE("GPL v2");
536MODULE_ALIAS("platform:i2c-bcm2835");