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coresight-stm.c
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linux-6.19.14/drivers/hwtracing/coresight/coresight-stm.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight System Trace Macrocell driver 6 * 7 * Initial implementation by Pratik Patel 8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org> 9 * 10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream 11 * framework by Mathieu Poirier 12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org> 13 * 14 * Guaranteed timing and support for various packet type coming from the 15 * generic STM API by Chunyan Zhang 16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org> 17 */ 18#include <asm/local.h> 19#include <linux/acpi.h> 20#include <linux/amba/bus.h> 21#include <linux/bitmap.h> 22#include <linux/clk.h> 23#include <linux/coresight.h> 24#include <linux/coresight-stm.h> 25#include <linux/err.h> 26#include <linux/kernel.h> 27#include <linux/moduleparam.h> 28#include <linux/of_address.h> 29#include <linux/perf_event.h> 30#include <linux/pm_runtime.h> 31#include <linux/stm.h> 32#include <linux/platform_device.h> 33 34#include "coresight-priv.h" 35#include "coresight-trace-id.h" 36 37#define STMDMASTARTR 0xc04 38#define STMDMASTOPR 0xc08 39#define STMDMASTATR 0xc0c 40#define STMDMACTLR 0xc10 41#define STMDMAIDR 0xcfc 42#define STMHEER 0xd00 43#define STMHETER 0xd20 44#define STMHEBSR 0xd60 45#define STMHEMCR 0xd64 46#define STMHEMASTR 0xdf4 47#define STMHEFEAT1R 0xdf8 48#define STMHEIDR 0xdfc 49#define STMSPER 0xe00 50#define STMSPTER 0xe20 51#define STMPRIVMASKR 0xe40 52#define STMSPSCR 0xe60 53#define STMSPMSCR 0xe64 54#define STMSPOVERRIDER 0xe68 55#define STMSPMOVERRIDER 0xe6c 56#define STMSPTRIGCSR 0xe70 57#define STMTCSR 0xe80 58#define STMTSSTIMR 0xe84 59#define STMTSFREQR 0xe8c 60#define STMSYNCR 0xe90 61#define STMAUXCR 0xe94 62#define STMSPFEAT1R 0xea0 63#define STMSPFEAT2R 0xea4 64#define STMSPFEAT3R 0xea8 65#define STMITTRIGGER 0xee8 66#define STMITATBDATA0 0xeec 67#define STMITATBCTR2 0xef0 68#define STMITATBID 0xef4 69#define STMITATBCTR0 0xef8 70 71#define STM_32_CHANNEL 32 72#define BYTES_PER_CHANNEL 256 73#define STM_TRACE_BUF_SIZE 4096 74#define STM_SW_MASTER_END 127 75 76/* Register bit definition */ 77#define STMTCSR_BUSY_BIT 23 78/* Reserve the first 10 channels for kernel usage */ 79#define STM_CHANNEL_OFFSET 0 80 81enum stm_pkt_type { 82 STM_PKT_TYPE_DATA = 0x98, 83 STM_PKT_TYPE_FLAG = 0xE8, 84 STM_PKT_TYPE_TRIG = 0xF8, 85}; 86 87#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ 88 (ch * BYTES_PER_CHANNEL)) 89#define stm_channel_off(type, opts) (type & ~opts) 90 91static int boot_nr_channel; 92 93/* 94 * Not really modular but using module_param is the easiest way to 95 * remain consistent with existing use cases for now. 96 */ 97module_param_named( 98 boot_nr_channel, boot_nr_channel, int, S_IRUGO 99); 100 101/* 102 * struct channel_space - central management entity for extended ports 103 * @base: memory mapped base address where channels start. 104 * @phys: physical base address of channel region. 105 * @guaraneed: is the channel delivery guaranteed. 106 */ 107struct channel_space { 108 void __iomem *base; 109 phys_addr_t phys; 110 unsigned long *guaranteed; 111}; 112 113DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm"); 114 115/** 116 * struct stm_drvdata - specifics associated to an STM component 117 * @base: memory mapped base address for this component. 118 * @atclk: optional clock for the core parts of the STM. 119 * @pclk: APB clock if present, otherwise NULL 120 * @csdev: component vitals needed by the framework. 121 * @spinlock: only one at a time pls. 122 * @chs: the channels accociated to this STM. 123 * @stm: structure associated to the generic STM interface. 124 * @traceid: value of the current ID for this component. 125 * @write_bytes: Maximus bytes this STM can write at a time. 126 * @stmsper: settings for register STMSPER. 127 * @stmspscr: settings for register STMSPSCR. 128 * @numsp: the total number of stimulus port support by this STM. 129 * @stmheer: settings for register STMHEER. 130 * @stmheter: settings for register STMHETER. 131 * @stmhebsr: settings for register STMHEBSR. 132 */ 133struct stm_drvdata { 134 void __iomem *base; 135 struct clk *atclk; 136 struct clk *pclk; 137 struct coresight_device *csdev; 138 spinlock_t spinlock; 139 struct channel_space chs; 140 struct stm_data stm; 141 u8 traceid; 142 u32 write_bytes; 143 u32 stmsper; 144 u32 stmspscr; 145 u32 numsp; 146 u32 stmheer; 147 u32 stmheter; 148 u32 stmhebsr; 149}; 150 151static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) 152{ 153 CS_UNLOCK(drvdata->base); 154 155 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); 156 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); 157 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); 158 writel_relaxed(0x01 | /* Enable HW event tracing */ 159 0x04, /* Error detection on event tracing */ 160 drvdata->base + STMHEMCR); 161 162 CS_LOCK(drvdata->base); 163} 164 165static void stm_port_enable_hw(struct stm_drvdata *drvdata) 166{ 167 CS_UNLOCK(drvdata->base); 168 /* ATB trigger enable on direct writes to TRIG locations */ 169 writel_relaxed(0x10, 170 drvdata->base + STMSPTRIGCSR); 171 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 172 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 173 174 CS_LOCK(drvdata->base); 175} 176 177static void stm_enable_hw(struct stm_drvdata *drvdata) 178{ 179 if (drvdata->stmheer) 180 stm_hwevent_enable_hw(drvdata); 181 182 stm_port_enable_hw(drvdata); 183 184 CS_UNLOCK(drvdata->base); 185 186 /* 4096 byte between synchronisation packets */ 187 writel_relaxed(0xFFF, drvdata->base + STMSYNCR); 188 writel_relaxed((drvdata->traceid << 16 | /* trace id */ 189 0x02 | /* timestamp enable */ 190 0x01), /* global STM enable */ 191 drvdata->base + STMTCSR); 192 193 CS_LOCK(drvdata->base); 194} 195 196static int stm_enable(struct coresight_device *csdev, struct perf_event *event, 197 enum cs_mode mode, 198 __maybe_unused struct coresight_path *path) 199{ 200 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 201 202 if (mode != CS_MODE_SYSFS) 203 return -EINVAL; 204 205 if (!coresight_take_mode(csdev, mode)) { 206 /* Someone is already using the tracer */ 207 return -EBUSY; 208 } 209 210 pm_runtime_get_sync(csdev->dev.parent); 211 212 spin_lock(&drvdata->spinlock); 213 stm_enable_hw(drvdata); 214 spin_unlock(&drvdata->spinlock); 215 216 dev_dbg(&csdev->dev, "STM tracing enabled\n"); 217 return 0; 218} 219 220static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) 221{ 222 CS_UNLOCK(drvdata->base); 223 224 writel_relaxed(0x0, drvdata->base + STMHEMCR); 225 writel_relaxed(0x0, drvdata->base + STMHEER); 226 writel_relaxed(0x0, drvdata->base + STMHETER); 227 228 CS_LOCK(drvdata->base); 229} 230 231static void stm_port_disable_hw(struct stm_drvdata *drvdata) 232{ 233 CS_UNLOCK(drvdata->base); 234 235 writel_relaxed(0x0, drvdata->base + STMSPER); 236 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); 237 238 CS_LOCK(drvdata->base); 239} 240 241static void stm_disable_hw(struct stm_drvdata *drvdata) 242{ 243 u32 val; 244 245 CS_UNLOCK(drvdata->base); 246 247 val = readl_relaxed(drvdata->base + STMTCSR); 248 val &= ~0x1; /* clear global STM enable [0] */ 249 writel_relaxed(val, drvdata->base + STMTCSR); 250 251 CS_LOCK(drvdata->base); 252 253 stm_port_disable_hw(drvdata); 254 if (drvdata->stmheer) 255 stm_hwevent_disable_hw(drvdata); 256} 257 258static void stm_disable(struct coresight_device *csdev, 259 struct perf_event *event) 260{ 261 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 262 struct csdev_access *csa = &csdev->access; 263 264 /* 265 * For as long as the tracer isn't disabled another entity can't 266 * change its status. As such we can read the status here without 267 * fearing it will change under us. 268 */ 269 if (coresight_get_mode(csdev) == CS_MODE_SYSFS) { 270 spin_lock(&drvdata->spinlock); 271 stm_disable_hw(drvdata); 272 spin_unlock(&drvdata->spinlock); 273 274 /* Wait until the engine has completely stopped */ 275 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0); 276 277 pm_runtime_put(csdev->dev.parent); 278 279 coresight_set_mode(csdev, CS_MODE_DISABLED); 280 dev_dbg(&csdev->dev, "STM tracing disabled\n"); 281 } 282} 283 284static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, 285 __maybe_unused struct coresight_device *sink) 286{ 287 struct stm_drvdata *drvdata; 288 289 drvdata = dev_get_drvdata(csdev->dev.parent); 290 291 return drvdata->traceid; 292} 293 294static const struct coresight_ops_source stm_source_ops = { 295 .enable = stm_enable, 296 .disable = stm_disable, 297}; 298 299static const struct coresight_ops stm_cs_ops = { 300 .trace_id = stm_trace_id, 301 .source_ops = &stm_source_ops, 302}; 303 304static bool stm_addr_unaligned(const void *addr, u8 write_bytes) 305{ 306 return ((unsigned long)addr & (write_bytes - 1)); 307} 308 309static void stm_send(void __iomem *addr, const void *data, 310 u32 size, u8 write_bytes) 311{ 312 u8 paload[8]; 313 314 if (stm_addr_unaligned(data, write_bytes)) { 315 memcpy(paload, data, size); 316 data = paload; 317 } 318 319 /* now we are 64bit/32bit aligned */ 320 switch (size) { 321#ifdef CONFIG_64BIT 322 case 8: 323 writeq_relaxed(*(u64 *)data, addr); 324 break; 325#endif 326 case 4: 327 writel_relaxed(*(u32 *)data, addr); 328 break; 329 case 2: 330 writew_relaxed(*(u16 *)data, addr); 331 break; 332 case 1: 333 writeb_relaxed(*(u8 *)data, addr); 334 break; 335 default: 336 break; 337 } 338} 339 340static int stm_generic_link(struct stm_data *stm_data, 341 unsigned int master, unsigned int channel) 342{ 343 struct stm_drvdata *drvdata = container_of(stm_data, 344 struct stm_drvdata, stm); 345 if (!drvdata->csdev) 346 return -EINVAL; 347 348 return coresight_enable_sysfs(drvdata->csdev); 349} 350 351static void stm_generic_unlink(struct stm_data *stm_data, 352 unsigned int master, unsigned int channel) 353{ 354 struct stm_drvdata *drvdata = container_of(stm_data, 355 struct stm_drvdata, stm); 356 if (!drvdata->csdev) 357 return; 358 359 coresight_disable_sysfs(drvdata->csdev); 360} 361 362static phys_addr_t 363stm_mmio_addr(struct stm_data *stm_data, unsigned int master, 364 unsigned int channel, unsigned int nr_chans) 365{ 366 struct stm_drvdata *drvdata = container_of(stm_data, 367 struct stm_drvdata, stm); 368 phys_addr_t addr; 369 370 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL; 371 372 if (offset_in_page(addr) || 373 offset_in_page(nr_chans * BYTES_PER_CHANNEL)) 374 return 0; 375 376 return addr; 377} 378 379static long stm_generic_set_options(struct stm_data *stm_data, 380 unsigned int master, 381 unsigned int channel, 382 unsigned int nr_chans, 383 unsigned long options) 384{ 385 struct stm_drvdata *drvdata = container_of(stm_data, 386 struct stm_drvdata, stm); 387 if (!coresight_get_mode(drvdata->csdev)) 388 return -EINVAL; 389 390 if (channel >= drvdata->numsp) 391 return -EINVAL; 392 393 switch (options) { 394 case STM_OPTION_GUARANTEED: 395 set_bit(channel, drvdata->chs.guaranteed); 396 break; 397 398 case STM_OPTION_INVARIANT: 399 clear_bit(channel, drvdata->chs.guaranteed); 400 break; 401 402 default: 403 return -EINVAL; 404 } 405 406 return 0; 407} 408 409static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, 410 unsigned int master, 411 unsigned int channel, 412 unsigned int packet, 413 unsigned int flags, 414 unsigned int size, 415 const unsigned char *payload) 416{ 417 void __iomem *ch_addr; 418 struct stm_drvdata *drvdata = container_of(stm_data, 419 struct stm_drvdata, stm); 420 unsigned int stm_flags; 421 422 if (!coresight_get_mode(drvdata->csdev)) 423 return -EACCES; 424 425 if (channel >= drvdata->numsp) 426 return -EINVAL; 427 428 ch_addr = stm_channel_addr(drvdata, channel); 429 430 stm_flags = (flags & STP_PACKET_TIMESTAMPED) ? 431 STM_FLAG_TIMESTAMPED : 0; 432 stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ? 433 STM_FLAG_GUARANTEED : 0; 434 435 if (size > drvdata->write_bytes) 436 size = drvdata->write_bytes; 437 else 438 size = rounddown_pow_of_two(size); 439 440 switch (packet) { 441 case STP_PACKET_FLAG: 442 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags); 443 444 /* 445 * The generic STM core sets a size of '0' on flag packets. 446 * As such send a flag packet of size '1' and tell the 447 * core we did so. 448 */ 449 stm_send(ch_addr, payload, 1, drvdata->write_bytes); 450 size = 1; 451 break; 452 453 case STP_PACKET_DATA: 454 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0; 455 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags); 456 stm_send(ch_addr, payload, size, 457 drvdata->write_bytes); 458 break; 459 460 default: 461 return -ENOTSUPP; 462 } 463 464 return size; 465} 466 467static ssize_t hwevent_enable_show(struct device *dev, 468 struct device_attribute *attr, char *buf) 469{ 470 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 471 unsigned long val = drvdata->stmheer; 472 473 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 474} 475 476static ssize_t hwevent_enable_store(struct device *dev, 477 struct device_attribute *attr, 478 const char *buf, size_t size) 479{ 480 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 481 unsigned long val; 482 int ret = 0; 483 484 ret = kstrtoul(buf, 16, &val); 485 if (ret) 486 return -EINVAL; 487 488 drvdata->stmheer = val; 489 /* HW event enable and trigger go hand in hand */ 490 drvdata->stmheter = val; 491 492 return size; 493} 494static DEVICE_ATTR_RW(hwevent_enable); 495 496static ssize_t hwevent_select_show(struct device *dev, 497 struct device_attribute *attr, char *buf) 498{ 499 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 500 unsigned long val = drvdata->stmhebsr; 501 502 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 503} 504 505static ssize_t hwevent_select_store(struct device *dev, 506 struct device_attribute *attr, 507 const char *buf, size_t size) 508{ 509 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 510 unsigned long val; 511 int ret = 0; 512 513 ret = kstrtoul(buf, 16, &val); 514 if (ret) 515 return -EINVAL; 516 517 drvdata->stmhebsr = val; 518 519 return size; 520} 521static DEVICE_ATTR_RW(hwevent_select); 522 523static ssize_t port_select_show(struct device *dev, 524 struct device_attribute *attr, char *buf) 525{ 526 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 527 unsigned long val; 528 529 if (!coresight_get_mode(drvdata->csdev)) { 530 val = drvdata->stmspscr; 531 } else { 532 spin_lock(&drvdata->spinlock); 533 val = readl_relaxed(drvdata->base + STMSPSCR); 534 spin_unlock(&drvdata->spinlock); 535 } 536 537 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 538} 539 540static ssize_t port_select_store(struct device *dev, 541 struct device_attribute *attr, 542 const char *buf, size_t size) 543{ 544 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 545 unsigned long val, stmsper; 546 int ret = 0; 547 548 ret = kstrtoul(buf, 16, &val); 549 if (ret) 550 return ret; 551 552 spin_lock(&drvdata->spinlock); 553 drvdata->stmspscr = val; 554 555 if (coresight_get_mode(drvdata->csdev)) { 556 CS_UNLOCK(drvdata->base); 557 /* Process as per ARM's TRM recommendation */ 558 stmsper = readl_relaxed(drvdata->base + STMSPER); 559 writel_relaxed(0x0, drvdata->base + STMSPER); 560 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 561 writel_relaxed(stmsper, drvdata->base + STMSPER); 562 CS_LOCK(drvdata->base); 563 } 564 spin_unlock(&drvdata->spinlock); 565 566 return size; 567} 568static DEVICE_ATTR_RW(port_select); 569 570static ssize_t port_enable_show(struct device *dev, 571 struct device_attribute *attr, char *buf) 572{ 573 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 574 unsigned long val; 575 576 if (!coresight_get_mode(drvdata->csdev)) { 577 val = drvdata->stmsper; 578 } else { 579 spin_lock(&drvdata->spinlock); 580 val = readl_relaxed(drvdata->base + STMSPER); 581 spin_unlock(&drvdata->spinlock); 582 } 583 584 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 585} 586 587static ssize_t port_enable_store(struct device *dev, 588 struct device_attribute *attr, 589 const char *buf, size_t size) 590{ 591 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 592 unsigned long val; 593 int ret = 0; 594 595 ret = kstrtoul(buf, 16, &val); 596 if (ret) 597 return ret; 598 599 spin_lock(&drvdata->spinlock); 600 drvdata->stmsper = val; 601 602 if (coresight_get_mode(drvdata->csdev)) { 603 CS_UNLOCK(drvdata->base); 604 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 605 CS_LOCK(drvdata->base); 606 } 607 spin_unlock(&drvdata->spinlock); 608 609 return size; 610} 611static DEVICE_ATTR_RW(port_enable); 612 613static ssize_t traceid_show(struct device *dev, 614 struct device_attribute *attr, char *buf) 615{ 616 unsigned long val; 617 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 618 619 val = drvdata->traceid; 620 return sprintf(buf, "%#lx\n", val); 621} 622static DEVICE_ATTR_RO(traceid); 623 624static struct attribute *coresight_stm_attrs[] = { 625 &dev_attr_hwevent_enable.attr, 626 &dev_attr_hwevent_select.attr, 627 &dev_attr_port_enable.attr, 628 &dev_attr_port_select.attr, 629 &dev_attr_traceid.attr, 630 NULL, 631}; 632 633static struct attribute *coresight_stm_mgmt_attrs[] = { 634 coresight_simple_reg32(tcsr, STMTCSR), 635 coresight_simple_reg32(tsfreqr, STMTSFREQR), 636 coresight_simple_reg32(syncr, STMSYNCR), 637 coresight_simple_reg32(sper, STMSPER), 638 coresight_simple_reg32(spter, STMSPTER), 639 coresight_simple_reg32(privmaskr, STMPRIVMASKR), 640 coresight_simple_reg32(spscr, STMSPSCR), 641 coresight_simple_reg32(spmscr, STMSPMSCR), 642 coresight_simple_reg32(spfeat1r, STMSPFEAT1R), 643 coresight_simple_reg32(spfeat2r, STMSPFEAT2R), 644 coresight_simple_reg32(spfeat3r, STMSPFEAT3R), 645 coresight_simple_reg32(devid, CORESIGHT_DEVID), 646 NULL, 647}; 648 649static const struct attribute_group coresight_stm_group = { 650 .attrs = coresight_stm_attrs, 651}; 652 653static const struct attribute_group coresight_stm_mgmt_group = { 654 .attrs = coresight_stm_mgmt_attrs, 655 .name = "mgmt", 656}; 657 658static const struct attribute_group *coresight_stm_groups[] = { 659 &coresight_stm_group, 660 &coresight_stm_mgmt_group, 661 NULL, 662}; 663 664#ifdef CONFIG_OF 665static int of_stm_get_stimulus_area(struct device *dev, struct resource *res) 666{ 667 const char *name = NULL; 668 int index = 0, found = 0; 669 struct device_node *np = dev->of_node; 670 671 while (!of_property_read_string_index(np, "reg-names", index, &name)) { 672 if (strcmp("stm-stimulus-base", name)) { 673 index++; 674 continue; 675 } 676 677 /* We have a match and @index is where it's at */ 678 found = 1; 679 break; 680 } 681 682 if (!found) 683 return -EINVAL; 684 685 return of_address_to_resource(np, index, res); 686} 687#else 688static int of_stm_get_stimulus_area(struct device *dev, 689 struct resource *res) 690{ 691 return -ENOENT; 692} 693#endif 694 695#ifdef CONFIG_ACPI 696static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res) 697{ 698 int rc; 699 bool found_base = false; 700 struct resource_entry *rent; 701 LIST_HEAD(res_list); 702 703 struct acpi_device *adev = ACPI_COMPANION(dev); 704 705 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL); 706 if (rc < 0) 707 return rc; 708 709 /* 710 * The stimulus base for STM device must be listed as the second memory 711 * resource, followed by the programming base address as described in 712 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design 713 * document (DEN0067). 714 */ 715 rc = -ENOENT; 716 list_for_each_entry(rent, &res_list, node) { 717 if (resource_type(rent->res) != IORESOURCE_MEM) 718 continue; 719 if (found_base) { 720 *res = *rent->res; 721 rc = 0; 722 break; 723 } 724 725 found_base = true; 726 } 727 728 acpi_dev_free_resource_list(&res_list); 729 return rc; 730} 731#else 732static int acpi_stm_get_stimulus_area(struct device *dev, 733 struct resource *res) 734{ 735 return -ENOENT; 736} 737#endif 738 739static int stm_get_stimulus_area(struct device *dev, struct resource *res) 740{ 741 struct fwnode_handle *fwnode = dev_fwnode(dev); 742 743 if (is_of_node(fwnode)) 744 return of_stm_get_stimulus_area(dev, res); 745 else if (is_acpi_node(fwnode)) 746 return acpi_stm_get_stimulus_area(dev, res); 747 return -ENOENT; 748} 749 750static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata) 751{ 752 u32 stmspfeat2r; 753 754 if (!IS_ENABLED(CONFIG_64BIT)) 755 return 4; 756 757 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); 758 759 /* 760 * bit[15:12] represents the fundamental data size 761 * 0 - 32-bit data 762 * 1 - 64-bit data 763 */ 764 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4; 765} 766 767static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata) 768{ 769 u32 numsp; 770 771 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 772 /* 773 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0, 774 * 32 stimulus ports are supported. 775 */ 776 numsp &= 0x1ffff; 777 if (!numsp) 778 numsp = STM_32_CHANNEL; 779 return numsp; 780} 781 782static void stm_init_default_data(struct stm_drvdata *drvdata) 783{ 784 /* Don't use port selection */ 785 drvdata->stmspscr = 0x0; 786 /* 787 * Enable all channel regardless of their number. When port 788 * selection isn't used (see above) STMSPER applies to all 789 * 32 channel group available, hence setting all 32 bits to 1 790 */ 791 drvdata->stmsper = ~0x0; 792 793 /* Set invariant transaction timing on all channels */ 794 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); 795} 796 797static void stm_init_generic_data(struct stm_drvdata *drvdata, 798 const char *name) 799{ 800 drvdata->stm.name = name; 801 802 /* 803 * MasterIDs are assigned at HW design phase. As such the core is 804 * using a single master for interaction with this device. 805 */ 806 drvdata->stm.sw_start = 1; 807 drvdata->stm.sw_end = 1; 808 drvdata->stm.hw_override = true; 809 drvdata->stm.sw_nchannels = drvdata->numsp; 810 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL; 811 drvdata->stm.packet = stm_generic_packet; 812 drvdata->stm.mmio_addr = stm_mmio_addr; 813 drvdata->stm.link = stm_generic_link; 814 drvdata->stm.unlink = stm_generic_unlink; 815 drvdata->stm.set_options = stm_generic_set_options; 816} 817 818static const struct amba_id stm_ids[]; 819 820static char *stm_csdev_name(struct coresight_device *csdev) 821{ 822 u32 stm_pid = coresight_get_pid(&csdev->access); 823 void *uci_data = coresight_get_uci_data_from_amba(stm_ids, stm_pid); 824 825 return uci_data ? (char *)uci_data : "STM"; 826} 827 828static int __stm_probe(struct device *dev, struct resource *res) 829{ 830 int ret, trace_id; 831 void __iomem *base; 832 struct coresight_platform_data *pdata = NULL; 833 struct stm_drvdata *drvdata; 834 struct resource ch_res; 835 struct coresight_desc desc = { 0 }; 836 837 desc.name = coresight_alloc_device_name(&stm_devs, dev); 838 if (!desc.name) 839 return -ENOMEM; 840 841 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 842 if (!drvdata) 843 return -ENOMEM; 844 845 ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); 846 if (ret) 847 return ret; 848 849 dev_set_drvdata(dev, drvdata); 850 851 base = devm_ioremap_resource(dev, res); 852 if (IS_ERR(base)) 853 return PTR_ERR(base); 854 drvdata->base = base; 855 desc.access = CSDEV_ACCESS_IOMEM(base); 856 857 ret = stm_get_stimulus_area(dev, &ch_res); 858 if (ret) 859 return ret; 860 drvdata->chs.phys = ch_res.start; 861 862 base = devm_ioremap_resource(dev, &ch_res); 863 if (IS_ERR(base)) 864 return PTR_ERR(base); 865 drvdata->chs.base = base; 866 867 drvdata->write_bytes = stm_fundamental_data_size(drvdata); 868 869 if (boot_nr_channel) 870 drvdata->numsp = boot_nr_channel; 871 else 872 drvdata->numsp = stm_num_stimulus_port(drvdata); 873 874 drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp, 875 GFP_KERNEL); 876 if (!drvdata->chs.guaranteed) 877 return -ENOMEM; 878 879 spin_lock_init(&drvdata->spinlock); 880 881 stm_init_default_data(drvdata); 882 stm_init_generic_data(drvdata, desc.name); 883 884 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) { 885 dev_info(dev, 886 "%s : stm_register_device failed, probing deferred\n", 887 desc.name); 888 return -EPROBE_DEFER; 889 } 890 891 pdata = coresight_get_platform_data(dev); 892 if (IS_ERR(pdata)) { 893 ret = PTR_ERR(pdata); 894 goto stm_unregister; 895 } 896 dev->platform_data = pdata; 897 898 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 899 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; 900 desc.ops = &stm_cs_ops; 901 desc.pdata = pdata; 902 desc.dev = dev; 903 desc.groups = coresight_stm_groups; 904 drvdata->csdev = coresight_register(&desc); 905 if (IS_ERR(drvdata->csdev)) { 906 ret = PTR_ERR(drvdata->csdev); 907 goto stm_unregister; 908 } 909 910 trace_id = coresight_trace_id_get_system_id(); 911 if (trace_id < 0) { 912 ret = trace_id; 913 goto cs_unregister; 914 } 915 drvdata->traceid = (u8)trace_id; 916 917 dev_info(&drvdata->csdev->dev, "%s initialized\n", 918 stm_csdev_name(drvdata->csdev)); 919 return 0; 920 921cs_unregister: 922 coresight_unregister(drvdata->csdev); 923 924stm_unregister: 925 stm_unregister_device(&drvdata->stm); 926 return ret; 927} 928 929static int stm_probe(struct amba_device *adev, const struct amba_id *id) 930{ 931 int ret; 932 933 ret = __stm_probe(&adev->dev, &adev->res); 934 if (!ret) 935 pm_runtime_put(&adev->dev); 936 937 return ret; 938} 939 940static void __stm_remove(struct device *dev) 941{ 942 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 943 944 coresight_trace_id_put_system_id(drvdata->traceid); 945 coresight_unregister(drvdata->csdev); 946 947 stm_unregister_device(&drvdata->stm); 948} 949 950static void stm_remove(struct amba_device *adev) 951{ 952 __stm_remove(&adev->dev); 953} 954 955#ifdef CONFIG_PM 956static int stm_runtime_suspend(struct device *dev) 957{ 958 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 959 960 clk_disable_unprepare(drvdata->atclk); 961 clk_disable_unprepare(drvdata->pclk); 962 963 return 0; 964} 965 966static int stm_runtime_resume(struct device *dev) 967{ 968 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 969 int ret; 970 971 ret = clk_prepare_enable(drvdata->pclk); 972 if (ret) 973 return ret; 974 975 ret = clk_prepare_enable(drvdata->atclk); 976 if (ret) 977 clk_disable_unprepare(drvdata->pclk); 978 979 return ret; 980} 981#endif 982 983static const struct dev_pm_ops stm_dev_pm_ops = { 984 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL) 985}; 986 987static const struct amba_id stm_ids[] = { 988 CS_AMBA_ID_DATA(0x000bb962, "STM32"), 989 CS_AMBA_ID_DATA(0x000bb963, "STM500"), 990 { 0, 0, NULL }, 991}; 992 993MODULE_DEVICE_TABLE(amba, stm_ids); 994 995static struct amba_driver stm_driver = { 996 .drv = { 997 .name = "coresight-stm", 998 .pm = &stm_dev_pm_ops, 999 .suppress_bind_attrs = true, 1000 }, 1001 .probe = stm_probe, 1002 .remove = stm_remove, 1003 .id_table = stm_ids, 1004}; 1005 1006static int stm_platform_probe(struct platform_device *pdev) 1007{ 1008 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1009 int ret = 0; 1010 1011 pm_runtime_get_noresume(&pdev->dev); 1012 pm_runtime_set_active(&pdev->dev); 1013 pm_runtime_enable(&pdev->dev); 1014 1015 ret = __stm_probe(&pdev->dev, res); 1016 pm_runtime_put(&pdev->dev); 1017 if (ret) 1018 pm_runtime_disable(&pdev->dev); 1019 1020 return ret; 1021} 1022 1023static void stm_platform_remove(struct platform_device *pdev) 1024{ 1025 struct stm_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 1026 1027 if (WARN_ON(!drvdata)) 1028 return; 1029 1030 __stm_remove(&pdev->dev); 1031 pm_runtime_disable(&pdev->dev); 1032} 1033 1034#ifdef CONFIG_ACPI 1035static const struct acpi_device_id stm_acpi_ids[] = { 1036 {"ARMHC502", 0, 0, 0}, /* ARM CoreSight STM */ 1037 {}, 1038}; 1039MODULE_DEVICE_TABLE(acpi, stm_acpi_ids); 1040#endif 1041 1042static struct platform_driver stm_platform_driver = { 1043 .probe = stm_platform_probe, 1044 .remove = stm_platform_remove, 1045 .driver = { 1046 .name = "coresight-stm-platform", 1047 .acpi_match_table = ACPI_PTR(stm_acpi_ids), 1048 .suppress_bind_attrs = true, 1049 .pm = &stm_dev_pm_ops, 1050 }, 1051}; 1052 1053static int __init stm_init(void) 1054{ 1055 return coresight_init_driver("stm", &stm_driver, &stm_platform_driver, THIS_MODULE); 1056} 1057 1058static void __exit stm_exit(void) 1059{ 1060 coresight_remove_driver(&stm_driver, &stm_platform_driver); 1061} 1062module_init(stm_init); 1063module_exit(stm_exit); 1064 1065MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 1066MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver"); 1067MODULE_LICENSE("GPL v2");
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