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coresight-etm4x.h

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linux-6.19.14/drivers/hwtracing/coresight/coresight-etm4x.h C 
   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef _CORESIGHT_CORESIGHT_ETM_H
   7#define _CORESIGHT_CORESIGHT_ETM_H
   8
   9#include <asm/local.h>
  10#include <linux/const.h>
  11#include <linux/spinlock.h>
  12#include <linux/types.h>
  13#include "coresight-priv.h"
  14
  15/*
  16 * Device registers:
  17 * 0x000 - 0x2FC: Trace		registers
  18 * 0x300 - 0x314: Management	registers
  19 * 0x318 - 0xEFC: Trace		registers
  20 * 0xF00: Management		registers
  21 * 0xFA0 - 0xFA4: Trace		registers
  22 * 0xFA8 - 0xFFC: Management	registers
  23 */
  24/* Trace registers (0x000-0x2FC) */
  25/* Main control and configuration registers */
  26#define TRCPRGCTLR			0x004
  27#define TRCPROCSELR			0x008
  28#define TRCSTATR			0x00C
  29#define TRCCONFIGR			0x010
  30#define TRCAUXCTLR			0x018
  31#define TRCEVENTCTL0R			0x020
  32#define TRCEVENTCTL1R			0x024
  33#define TRCRSR				0x028
  34#define TRCSTALLCTLR			0x02C
  35#define TRCTSCTLR			0x030
  36#define TRCSYNCPR			0x034
  37#define TRCCCCTLR			0x038
  38#define TRCBBCTLR			0x03C
  39#define TRCTRACEIDR			0x040
  40#define TRCQCTLR			0x044
  41/* Filtering control registers */
  42#define TRCVICTLR			0x080
  43#define TRCVIIECTLR			0x084
  44#define TRCVISSCTLR			0x088
  45#define TRCVIPCSSCTLR			0x08C
  46/* Derived resources registers */
  47#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */
  48#define TRCSEQRSTEVR			0x118
  49#define TRCSEQSTR			0x11C
  50#define TRCEXTINSELR			0x120
  51#define TRCEXTINSELRn(n)		(0x120 + (n * 4)) /* n = 0-3 */
  52#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
  53#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
  54#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
  55/* ID registers */
  56#define TRCIDR8				0x180
  57#define TRCIDR9				0x184
  58#define TRCIDR10			0x188
  59#define TRCIDR11			0x18C
  60#define TRCIDR12			0x190
  61#define TRCIDR13			0x194
  62#define TRCIMSPEC0			0x1C0
  63#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */
  64#define TRCIDR0				0x1E0
  65#define TRCIDR1				0x1E4
  66#define TRCIDR2				0x1E8
  67#define TRCIDR3				0x1EC
  68#define TRCIDR4				0x1F0
  69#define TRCIDR5				0x1F4
  70#define TRCIDR6				0x1F8
  71#define TRCIDR7				0x1FC
  72/*
  73 * Resource selection registers, n = 2-31.
  74 * First pair (regs 0, 1) is always present and is reserved.
  75 */
  76#define TRCRSCTLRn(n)			(0x200 + (n * 4))
  77/* Single-shot comparator registers, n = 0-7 */
  78#define TRCSSCCRn(n)			(0x280 + (n * 4))
  79#define TRCSSCSRn(n)			(0x2A0 + (n * 4))
  80#define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
  81/* Management registers (0x300-0x314) */
  82#define TRCOSLAR			0x300
  83#define TRCOSLSR			0x304
  84#define TRCPDCR				0x310
  85#define TRCPDSR				0x314
  86/* Trace registers (0x318-0xEFC) */
  87/* Address Comparator registers n = 0-15 */
  88#define TRCACVRn(n)			(0x400 + (n * 8))
  89#define TRCACATRn(n)			(0x480 + (n * 8))
  90/* ContextID/Virtual ContextID comparators, n = 0-7 */
  91#define TRCCIDCVRn(n)			(0x600 + (n * 8))
  92#define TRCVMIDCVRn(n)			(0x640 + (n * 8))
  93#define TRCCIDCCTLR0			0x680
  94#define TRCCIDCCTLR1			0x684
  95#define TRCVMIDCCTLR0			0x688
  96#define TRCVMIDCCTLR1			0x68C
  97/* Management register (0xF00) */
  98/* Integration control registers */
  99#define TRCITCTRL			0xF00
 100/* Trace registers (0xFA0-0xFA4) */
 101/* Claim tag registers */
 102#define TRCCLAIMSET			0xFA0
 103#define TRCCLAIMCLR			0xFA4
 104/* Management registers (0xFA8-0xFFC) */
 105#define TRCDEVAFF0			0xFA8
 106#define TRCDEVAFF1			0xFAC
 107#define TRCLAR				0xFB0
 108#define TRCLSR				0xFB4
 109#define TRCAUTHSTATUS			0xFB8
 110#define TRCDEVARCH			0xFBC
 111#define TRCDEVID			0xFC8
 112#define TRCDEVTYPE			0xFCC
 113#define TRCPIDR4			0xFD0
 114#define TRCPIDR5			0xFD4
 115#define TRCPIDR6			0xFD8
 116#define TRCPIDR7			0xFDC
 117#define TRCPIDR0			0xFE0
 118#define TRCPIDR1			0xFE4
 119#define TRCPIDR2			0xFE8
 120#define TRCPIDR3			0xFEC
 121#define TRCCIDR0			0xFF0
 122#define TRCCIDR1			0xFF4
 123#define TRCCIDR2			0xFF8
 124#define TRCCIDR3			0xFFC
 125
 126#define TRCRSR_TA			BIT(12)
 127
 128/*
 129 * Bit positions of registers that are defined above, in the sysreg.h style
 130 * of _MASK for multi bit fields and BIT() for single bits.
 131 */
 132#define TRCIDR0_INSTP0_MASK			GENMASK(2, 1)
 133#define TRCIDR0_TRCBB				BIT(5)
 134#define TRCIDR0_TRCCOND				BIT(6)
 135#define TRCIDR0_TRCCCI				BIT(7)
 136#define TRCIDR0_RETSTACK			BIT(9)
 137#define TRCIDR0_NUMEVENT_MASK			GENMASK(11, 10)
 138#define TRCIDR0_QFILT				BIT(14)
 139#define TRCIDR0_QSUPP_MASK			GENMASK(16, 15)
 140#define TRCIDR0_TSSIZE_MASK			GENMASK(28, 24)
 141
 142#define TRCIDR2_CIDSIZE_MASK			GENMASK(9, 5)
 143#define TRCIDR2_VMIDSIZE_MASK			GENMASK(14, 10)
 144#define TRCIDR2_CCSIZE_MASK			GENMASK(28, 25)
 145
 146#define TRCIDR3_CCITMIN_MASK			GENMASK(11, 0)
 147#define TRCIDR3_EXLEVEL_S_MASK			GENMASK(19, 16)
 148#define TRCIDR3_EXLEVEL_NS_MASK			GENMASK(23, 20)
 149#define TRCIDR3_TRCERR				BIT(24)
 150#define TRCIDR3_SYNCPR				BIT(25)
 151#define TRCIDR3_STALLCTL			BIT(26)
 152#define TRCIDR3_SYSSTALL			BIT(27)
 153#define TRCIDR3_NUMPROC_LO_MASK			GENMASK(30, 28)
 154#define TRCIDR3_NUMPROC_HI_MASK			GENMASK(13, 12)
 155#define TRCIDR3_NOOVERFLOW			BIT(31)
 156
 157#define TRCIDR4_NUMACPAIRS_MASK			GENMASK(3, 0)
 158#define TRCIDR4_NUMPC_MASK			GENMASK(15, 12)
 159#define TRCIDR4_NUMRSPAIR_MASK			GENMASK(19, 16)
 160#define TRCIDR4_NUMSSCC_MASK			GENMASK(23, 20)
 161#define TRCIDR4_NUMCIDC_MASK			GENMASK(27, 24)
 162#define TRCIDR4_NUMVMIDC_MASK			GENMASK(31, 28)
 163
 164#define TRCIDR5_NUMEXTIN_MASK			GENMASK(8, 0)
 165#define TRCIDR5_NUMEXTINSEL_MASK               GENMASK(11, 9)
 166#define TRCIDR5_TRACEIDSIZE_MASK		GENMASK(21, 16)
 167#define TRCIDR5_ATBTRIG				BIT(22)
 168#define TRCIDR5_LPOVERRIDE			BIT(23)
 169#define TRCIDR5_NUMSEQSTATE_MASK		GENMASK(27, 25)
 170#define TRCIDR5_NUMCNTR_MASK			GENMASK(30, 28)
 171
 172#define TRCCONFIGR_INSTP0_LOAD			BIT(1)
 173#define TRCCONFIGR_INSTP0_STORE			BIT(2)
 174#define TRCCONFIGR_INSTP0_LOAD_STORE		(TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
 175#define TRCCONFIGR_BB				BIT(3)
 176#define TRCCONFIGR_CCI				BIT(4)
 177#define TRCCONFIGR_CID				BIT(6)
 178#define TRCCONFIGR_VMID				BIT(7)
 179#define TRCCONFIGR_COND_MASK			GENMASK(10, 8)
 180#define TRCCONFIGR_TS				BIT(11)
 181#define TRCCONFIGR_RS				BIT(12)
 182#define TRCCONFIGR_QE_W_COUNTS			BIT(13)
 183#define TRCCONFIGR_QE_WO_COUNTS			BIT(14)
 184#define TRCCONFIGR_VMIDOPT			BIT(15)
 185#define TRCCONFIGR_DA				BIT(16)
 186#define TRCCONFIGR_DV				BIT(17)
 187
 188#define TRCEVENTCTL1R_INSTEN_MASK		GENMASK(3, 0)
 189#define TRCEVENTCTL1R_INSTEN_0			BIT(0)
 190#define TRCEVENTCTL1R_INSTEN_1			BIT(1)
 191#define TRCEVENTCTL1R_INSTEN_2			BIT(2)
 192#define TRCEVENTCTL1R_INSTEN_3			BIT(3)
 193#define TRCEVENTCTL1R_ATB			BIT(11)
 194#define TRCEVENTCTL1R_LPOVERRIDE		BIT(12)
 195
 196#define TRCSTALLCTLR_ISTALL			BIT(8)
 197#define TRCSTALLCTLR_INSTPRIORITY		BIT(10)
 198#define TRCSTALLCTLR_NOOVERFLOW			BIT(13)
 199
 200#define TRCVICTLR_EVENT_MASK			GENMASK(7, 0)
 201#define TRCVICTLR_SSSTATUS			BIT(9)
 202#define TRCVICTLR_TRCRESET			BIT(10)
 203#define TRCVICTLR_TRCERR			BIT(11)
 204#define TRCVICTLR_EXLEVEL_MASK			GENMASK(22, 16)
 205#define TRCVICTLR_EXLEVEL_S_MASK		GENMASK(19, 16)
 206#define TRCVICTLR_EXLEVEL_NS_MASK		GENMASK(22, 20)
 207
 208#define TRCACATRn_TYPE_MASK			GENMASK(1, 0)
 209#define TRCACATRn_CONTEXTTYPE_MASK		GENMASK(3, 2)
 210#define TRCACATRn_CONTEXTTYPE_CTXID		BIT(2)
 211#define TRCACATRn_CONTEXTTYPE_VMID		BIT(3)
 212#define TRCACATRn_CONTEXT_MASK			GENMASK(6, 4)
 213#define TRCACATRn_EXLEVEL_MASK			GENMASK(14, 8)
 214
 215#define TRCSSCSRn_STATUS			BIT(31)
 216#define TRCSSCCRn_SAC_ARC_RST_MASK		GENMASK(24, 0)
 217
 218#define TRCSSPCICRn_PC_MASK			GENMASK(7, 0)
 219
 220#define TRCBBCTLR_MODE				BIT(8)
 221#define TRCBBCTLR_RANGE_MASK			GENMASK(7, 0)
 222
 223#define TRCRSCTLRn_PAIRINV			BIT(21)
 224#define TRCRSCTLRn_INV				BIT(20)
 225#define TRCRSCTLRn_GROUP_MASK			GENMASK(19, 16)
 226#define TRCRSCTLRn_SELECT_MASK			GENMASK(15, 0)
 227
 228/*
 229 * System instructions to access ETM registers.
 230 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
 231 */
 232#define ETM4x_OFFSET_TO_REG(x)		((x) >> 2)
 233
 234#define ETM4x_CRn(n)			(((n) >> 7) & 0x7)
 235#define ETM4x_Op2(n)			(((n) >> 4) & 0x7)
 236#define ETM4x_CRm(n)			((n) & 0xf)
 237
 238#include <asm/sysreg.h>
 239#define ETM4x_REG_NUM_TO_SYSREG(n)				\
 240	sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
 241
 242#define READ_ETM4x_REG(reg)					\
 243	read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
 244#define WRITE_ETM4x_REG(val, reg)				\
 245	write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
 246
 247#define read_etm4x_sysreg_const_offset(offset)			\
 248	READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
 249
 250#define write_etm4x_sysreg_const_offset(val, offset)		\
 251	WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
 252
 253#define CASE_READ(res, x)					\
 254	case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
 255
 256#define CASE_WRITE(val, x)					\
 257	case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
 258
 259#define CASE_NOP(__unused, x)					\
 260	case (x):	/* fall through */
 261
 262#define ETE_ONLY_SYSREG_LIST(op, val)		\
 263	CASE_##op((val), TRCRSR)		\
 264	CASE_##op((val), TRCEXTINSELRn(1))	\
 265	CASE_##op((val), TRCEXTINSELRn(2))	\
 266	CASE_##op((val), TRCEXTINSELRn(3))
 267
 268/* List of registers accessible via System instructions */
 269#define ETM4x_ONLY_SYSREG_LIST(op, val)		\
 270	CASE_##op((val), TRCPROCSELR)		\
 271	CASE_##op((val), TRCOSLAR)
 272
 273#define ETM_COMMON_SYSREG_LIST(op, val)		\
 274	CASE_##op((val), TRCPRGCTLR)		\
 275	CASE_##op((val), TRCSTATR)		\
 276	CASE_##op((val), TRCCONFIGR)		\
 277	CASE_##op((val), TRCAUXCTLR)		\
 278	CASE_##op((val), TRCEVENTCTL0R)		\
 279	CASE_##op((val), TRCEVENTCTL1R)		\
 280	CASE_##op((val), TRCSTALLCTLR)		\
 281	CASE_##op((val), TRCTSCTLR)		\
 282	CASE_##op((val), TRCSYNCPR)		\
 283	CASE_##op((val), TRCCCCTLR)		\
 284	CASE_##op((val), TRCBBCTLR)		\
 285	CASE_##op((val), TRCTRACEIDR)		\
 286	CASE_##op((val), TRCQCTLR)		\
 287	CASE_##op((val), TRCVICTLR)		\
 288	CASE_##op((val), TRCVIIECTLR)		\
 289	CASE_##op((val), TRCVISSCTLR)		\
 290	CASE_##op((val), TRCVIPCSSCTLR)		\
 291	CASE_##op((val), TRCSEQEVRn(0))		\
 292	CASE_##op((val), TRCSEQEVRn(1))		\
 293	CASE_##op((val), TRCSEQEVRn(2))		\
 294	CASE_##op((val), TRCSEQRSTEVR)		\
 295	CASE_##op((val), TRCSEQSTR)		\
 296	CASE_##op((val), TRCEXTINSELR)		\
 297	CASE_##op((val), TRCCNTRLDVRn(0))	\
 298	CASE_##op((val), TRCCNTRLDVRn(1))	\
 299	CASE_##op((val), TRCCNTRLDVRn(2))	\
 300	CASE_##op((val), TRCCNTRLDVRn(3))	\
 301	CASE_##op((val), TRCCNTCTLRn(0))	\
 302	CASE_##op((val), TRCCNTCTLRn(1))	\
 303	CASE_##op((val), TRCCNTCTLRn(2))	\
 304	CASE_##op((val), TRCCNTCTLRn(3))	\
 305	CASE_##op((val), TRCCNTVRn(0))		\
 306	CASE_##op((val), TRCCNTVRn(1))		\
 307	CASE_##op((val), TRCCNTVRn(2))		\
 308	CASE_##op((val), TRCCNTVRn(3))		\
 309	CASE_##op((val), TRCIDR8)		\
 310	CASE_##op((val), TRCIDR9)		\
 311	CASE_##op((val), TRCIDR10)		\
 312	CASE_##op((val), TRCIDR11)		\
 313	CASE_##op((val), TRCIDR12)		\
 314	CASE_##op((val), TRCIDR13)		\
 315	CASE_##op((val), TRCIMSPECn(0))		\
 316	CASE_##op((val), TRCIMSPECn(1))		\
 317	CASE_##op((val), TRCIMSPECn(2))		\
 318	CASE_##op((val), TRCIMSPECn(3))		\
 319	CASE_##op((val), TRCIMSPECn(4))		\
 320	CASE_##op((val), TRCIMSPECn(5))		\
 321	CASE_##op((val), TRCIMSPECn(6))		\
 322	CASE_##op((val), TRCIMSPECn(7))		\
 323	CASE_##op((val), TRCIDR0)		\
 324	CASE_##op((val), TRCIDR1)		\
 325	CASE_##op((val), TRCIDR2)		\
 326	CASE_##op((val), TRCIDR3)		\
 327	CASE_##op((val), TRCIDR4)		\
 328	CASE_##op((val), TRCIDR5)		\
 329	CASE_##op((val), TRCIDR6)		\
 330	CASE_##op((val), TRCIDR7)		\
 331	CASE_##op((val), TRCRSCTLRn(2))		\
 332	CASE_##op((val), TRCRSCTLRn(3))		\
 333	CASE_##op((val), TRCRSCTLRn(4))		\
 334	CASE_##op((val), TRCRSCTLRn(5))		\
 335	CASE_##op((val), TRCRSCTLRn(6))		\
 336	CASE_##op((val), TRCRSCTLRn(7))		\
 337	CASE_##op((val), TRCRSCTLRn(8))		\
 338	CASE_##op((val), TRCRSCTLRn(9))		\
 339	CASE_##op((val), TRCRSCTLRn(10))	\
 340	CASE_##op((val), TRCRSCTLRn(11))	\
 341	CASE_##op((val), TRCRSCTLRn(12))	\
 342	CASE_##op((val), TRCRSCTLRn(13))	\
 343	CASE_##op((val), TRCRSCTLRn(14))	\
 344	CASE_##op((val), TRCRSCTLRn(15))	\
 345	CASE_##op((val), TRCRSCTLRn(16))	\
 346	CASE_##op((val), TRCRSCTLRn(17))	\
 347	CASE_##op((val), TRCRSCTLRn(18))	\
 348	CASE_##op((val), TRCRSCTLRn(19))	\
 349	CASE_##op((val), TRCRSCTLRn(20))	\
 350	CASE_##op((val), TRCRSCTLRn(21))	\
 351	CASE_##op((val), TRCRSCTLRn(22))	\
 352	CASE_##op((val), TRCRSCTLRn(23))	\
 353	CASE_##op((val), TRCRSCTLRn(24))	\
 354	CASE_##op((val), TRCRSCTLRn(25))	\
 355	CASE_##op((val), TRCRSCTLRn(26))	\
 356	CASE_##op((val), TRCRSCTLRn(27))	\
 357	CASE_##op((val), TRCRSCTLRn(28))	\
 358	CASE_##op((val), TRCRSCTLRn(29))	\
 359	CASE_##op((val), TRCRSCTLRn(30))	\
 360	CASE_##op((val), TRCRSCTLRn(31))	\
 361	CASE_##op((val), TRCSSCCRn(0))		\
 362	CASE_##op((val), TRCSSCCRn(1))		\
 363	CASE_##op((val), TRCSSCCRn(2))		\
 364	CASE_##op((val), TRCSSCCRn(3))		\
 365	CASE_##op((val), TRCSSCCRn(4))		\
 366	CASE_##op((val), TRCSSCCRn(5))		\
 367	CASE_##op((val), TRCSSCCRn(6))		\
 368	CASE_##op((val), TRCSSCCRn(7))		\
 369	CASE_##op((val), TRCSSCSRn(0))		\
 370	CASE_##op((val), TRCSSCSRn(1))		\
 371	CASE_##op((val), TRCSSCSRn(2))		\
 372	CASE_##op((val), TRCSSCSRn(3))		\
 373	CASE_##op((val), TRCSSCSRn(4))		\
 374	CASE_##op((val), TRCSSCSRn(5))		\
 375	CASE_##op((val), TRCSSCSRn(6))		\
 376	CASE_##op((val), TRCSSCSRn(7))		\
 377	CASE_##op((val), TRCSSPCICRn(0))	\
 378	CASE_##op((val), TRCSSPCICRn(1))	\
 379	CASE_##op((val), TRCSSPCICRn(2))	\
 380	CASE_##op((val), TRCSSPCICRn(3))	\
 381	CASE_##op((val), TRCSSPCICRn(4))	\
 382	CASE_##op((val), TRCSSPCICRn(5))	\
 383	CASE_##op((val), TRCSSPCICRn(6))	\
 384	CASE_##op((val), TRCSSPCICRn(7))	\
 385	CASE_##op((val), TRCOSLSR)		\
 386	CASE_##op((val), TRCACVRn(0))		\
 387	CASE_##op((val), TRCACVRn(1))		\
 388	CASE_##op((val), TRCACVRn(2))		\
 389	CASE_##op((val), TRCACVRn(3))		\
 390	CASE_##op((val), TRCACVRn(4))		\
 391	CASE_##op((val), TRCACVRn(5))		\
 392	CASE_##op((val), TRCACVRn(6))		\
 393	CASE_##op((val), TRCACVRn(7))		\
 394	CASE_##op((val), TRCACVRn(8))		\
 395	CASE_##op((val), TRCACVRn(9))		\
 396	CASE_##op((val), TRCACVRn(10))		\
 397	CASE_##op((val), TRCACVRn(11))		\
 398	CASE_##op((val), TRCACVRn(12))		\
 399	CASE_##op((val), TRCACVRn(13))		\
 400	CASE_##op((val), TRCACVRn(14))		\
 401	CASE_##op((val), TRCACVRn(15))		\
 402	CASE_##op((val), TRCACATRn(0))		\
 403	CASE_##op((val), TRCACATRn(1))		\
 404	CASE_##op((val), TRCACATRn(2))		\
 405	CASE_##op((val), TRCACATRn(3))		\
 406	CASE_##op((val), TRCACATRn(4))		\
 407	CASE_##op((val), TRCACATRn(5))		\
 408	CASE_##op((val), TRCACATRn(6))		\
 409	CASE_##op((val), TRCACATRn(7))		\
 410	CASE_##op((val), TRCACATRn(8))		\
 411	CASE_##op((val), TRCACATRn(9))		\
 412	CASE_##op((val), TRCACATRn(10))		\
 413	CASE_##op((val), TRCACATRn(11))		\
 414	CASE_##op((val), TRCACATRn(12))		\
 415	CASE_##op((val), TRCACATRn(13))		\
 416	CASE_##op((val), TRCACATRn(14))		\
 417	CASE_##op((val), TRCACATRn(15))		\
 418	CASE_##op((val), TRCCIDCVRn(0))		\
 419	CASE_##op((val), TRCCIDCVRn(1))		\
 420	CASE_##op((val), TRCCIDCVRn(2))		\
 421	CASE_##op((val), TRCCIDCVRn(3))		\
 422	CASE_##op((val), TRCCIDCVRn(4))		\
 423	CASE_##op((val), TRCCIDCVRn(5))		\
 424	CASE_##op((val), TRCCIDCVRn(6))		\
 425	CASE_##op((val), TRCCIDCVRn(7))		\
 426	CASE_##op((val), TRCVMIDCVRn(0))	\
 427	CASE_##op((val), TRCVMIDCVRn(1))	\
 428	CASE_##op((val), TRCVMIDCVRn(2))	\
 429	CASE_##op((val), TRCVMIDCVRn(3))	\
 430	CASE_##op((val), TRCVMIDCVRn(4))	\
 431	CASE_##op((val), TRCVMIDCVRn(5))	\
 432	CASE_##op((val), TRCVMIDCVRn(6))	\
 433	CASE_##op((val), TRCVMIDCVRn(7))	\
 434	CASE_##op((val), TRCCIDCCTLR0)		\
 435	CASE_##op((val), TRCCIDCCTLR1)		\
 436	CASE_##op((val), TRCVMIDCCTLR0)		\
 437	CASE_##op((val), TRCVMIDCCTLR1)		\
 438	CASE_##op((val), TRCCLAIMSET)		\
 439	CASE_##op((val), TRCCLAIMCLR)		\
 440	CASE_##op((val), TRCAUTHSTATUS)		\
 441	CASE_##op((val), TRCDEVARCH)		\
 442	CASE_##op((val), TRCDEVID)
 443
 444/* List of registers only accessible via memory-mapped interface */
 445#define ETM_MMAP_LIST(op, val)			\
 446	CASE_##op((val), TRCDEVTYPE)		\
 447	CASE_##op((val), TRCPDCR)		\
 448	CASE_##op((val), TRCPDSR)		\
 449	CASE_##op((val), TRCDEVAFF0)		\
 450	CASE_##op((val), TRCDEVAFF1)		\
 451	CASE_##op((val), TRCLAR)		\
 452	CASE_##op((val), TRCLSR)		\
 453	CASE_##op((val), TRCITCTRL)		\
 454	CASE_##op((val), TRCPIDR4)		\
 455	CASE_##op((val), TRCPIDR0)		\
 456	CASE_##op((val), TRCPIDR1)		\
 457	CASE_##op((val), TRCPIDR2)		\
 458	CASE_##op((val), TRCPIDR3)
 459
 460#define ETM4x_READ_SYSREG_CASES(res)		\
 461	ETM_COMMON_SYSREG_LIST(READ, (res))	\
 462	ETM4x_ONLY_SYSREG_LIST(READ, (res))
 463
 464#define ETM4x_WRITE_SYSREG_CASES(val)		\
 465	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
 466	ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
 467
 468#define ETM_COMMON_SYSREG_LIST_CASES		\
 469	ETM_COMMON_SYSREG_LIST(NOP, __unused)
 470
 471#define ETM4x_ONLY_SYSREG_LIST_CASES		\
 472	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
 473
 474#define ETM4x_SYSREG_LIST_CASES			\
 475	ETM_COMMON_SYSREG_LIST_CASES		\
 476	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
 477
 478#define ETM4x_MMAP_LIST_CASES		ETM_MMAP_LIST(NOP, __unused)
 479
 480/* ETE only supports system register access */
 481#define ETE_READ_CASES(res)			\
 482	ETM_COMMON_SYSREG_LIST(READ, (res))	\
 483	ETE_ONLY_SYSREG_LIST(READ, (res))
 484
 485#define ETE_WRITE_CASES(val)			\
 486	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
 487	ETE_ONLY_SYSREG_LIST(WRITE, (val))
 488
 489#define ETE_ONLY_SYSREG_LIST_CASES		\
 490	ETE_ONLY_SYSREG_LIST(NOP, __unused)
 491
 492#define read_etm4x_sysreg_offset(offset, _64bit)				\
 493	({									\
 494		u64 __val;							\
 495										\
 496		if (__is_constexpr((offset)))					\
 497			__val = read_etm4x_sysreg_const_offset((offset));	\
 498		else								\
 499			__val = etm4x_sysreg_read((offset), true, (_64bit));	\
 500		__val;								\
 501	 })
 502
 503#define write_etm4x_sysreg_offset(val, offset, _64bit)			\
 504	do {								\
 505		if (__builtin_constant_p((offset)))			\
 506			write_etm4x_sysreg_const_offset((val),		\
 507							(offset));	\
 508		else							\
 509			etm4x_sysreg_write((val), (offset), true,	\
 510					   (_64bit));			\
 511	} while (0)
 512
 513
 514#define etm4x_relaxed_read32(csa, offset)				\
 515	((u32)((csa)->io_mem ?						\
 516		 readl_relaxed((csa)->base + (offset)) :		\
 517		 read_etm4x_sysreg_offset((offset), false)))
 518
 519#define etm4x_relaxed_read64(csa, offset)				\
 520	((u64)((csa)->io_mem ?						\
 521		 readq_relaxed((csa)->base + (offset)) :		\
 522		 read_etm4x_sysreg_offset((offset), true)))
 523
 524#define etm4x_read32(csa, offset)					\
 525	({								\
 526		u32 __val = etm4x_relaxed_read32((csa), (offset));	\
 527		__io_ar(__val);						\
 528		__val;							\
 529	 })
 530
 531#define etm4x_read64(csa, offset)					\
 532	({								\
 533		u64 __val = etm4x_relaxed_read64((csa), (offset));	\
 534		__io_ar(__val);						\
 535		__val;							\
 536	 })
 537
 538#define etm4x_relaxed_write32(csa, val, offset)				\
 539	do {								\
 540		if ((csa)->io_mem)					\
 541			writel_relaxed((val), (csa)->base + (offset));	\
 542		else							\
 543			write_etm4x_sysreg_offset((val), (offset),	\
 544						  false);		\
 545	} while (0)
 546
 547#define etm4x_relaxed_write64(csa, val, offset)				\
 548	do {								\
 549		if ((csa)->io_mem)					\
 550			writeq_relaxed((val), (csa)->base + (offset));	\
 551		else							\
 552			write_etm4x_sysreg_offset((val), (offset),	\
 553						  true);		\
 554	} while (0)
 555
 556#define etm4x_write32(csa, val, offset)					\
 557	do {								\
 558		__io_bw();						\
 559		etm4x_relaxed_write32((csa), (val), (offset));		\
 560	} while (0)
 561
 562#define etm4x_write64(csa, val, offset)					\
 563	do {								\
 564		__io_bw();						\
 565		etm4x_relaxed_write64((csa), (val), (offset));		\
 566	} while (0)
 567
 568
 569/* ETMv4 resources */
 570#define ETM_MAX_NR_PE			8
 571#define ETMv4_MAX_CNTR			4
 572#define ETM_MAX_SEQ_STATES		4
 573#define ETM_MAX_EXT_INP_SEL		4
 574#define ETM_MAX_EXT_INP			256
 575#define ETM_MAX_EXT_OUT			4
 576#define ETM_MAX_SINGLE_ADDR_CMP		16
 577#define ETM_MAX_ADDR_RANGE_CMP		(ETM_MAX_SINGLE_ADDR_CMP / 2)
 578#define ETM_MAX_DATA_VAL_CMP		8
 579#define ETMv4_MAX_CTXID_CMP		8
 580#define ETM_MAX_VMID_CMP		8
 581#define ETM_MAX_PE_CMP			8
 582#define ETM_MAX_RES_SEL			32
 583#define ETM_MAX_SS_CMP			8
 584
 585#define ETMv4_SYNC_MASK			0x1F
 586#define ETM_CYC_THRESHOLD_MASK		0xFFF
 587#define ETM_CYC_THRESHOLD_DEFAULT       0x100
 588#define ETMv4_EVENT_MASK		0xFF
 589#define ETM_CNTR_MAX_VAL		0xFFFF
 590#define ETM_TRACEID_MASK		0x3f
 591
 592/* ETMv4 programming modes */
 593#define ETM_MODE_EXCLUDE		BIT(0)
 594#define ETM_MODE_LOAD			BIT(1)
 595#define ETM_MODE_STORE			BIT(2)
 596#define ETM_MODE_LOAD_STORE		BIT(3)
 597#define ETM_MODE_BB			BIT(4)
 598#define ETMv4_MODE_CYCACC		BIT(5)
 599#define ETMv4_MODE_CTXID		BIT(6)
 600#define ETM_MODE_VMID			BIT(7)
 601#define ETM_MODE_COND(val)		BMVAL(val, 8, 10)
 602#define ETMv4_MODE_TIMESTAMP		BIT(11)
 603#define ETM_MODE_RETURNSTACK		BIT(12)
 604#define ETM_MODE_QELEM(val)		BMVAL(val, 13, 14)
 605#define ETM_MODE_DATA_TRACE_ADDR	BIT(15)
 606#define ETM_MODE_DATA_TRACE_VAL		BIT(16)
 607#define ETM_MODE_ISTALL			BIT(17)
 608#define ETM_MODE_DSTALL			BIT(18)
 609#define ETM_MODE_ATB_TRIGGER		BIT(19)
 610#define ETM_MODE_LPOVERRIDE		BIT(20)
 611#define ETM_MODE_ISTALL_EN		BIT(21)
 612#define ETM_MODE_DSTALL_EN		BIT(22)
 613#define ETM_MODE_INSTPRIO		BIT(23)
 614#define ETM_MODE_NOOVERFLOW		BIT(24)
 615#define ETM_MODE_TRACE_RESET		BIT(25)
 616#define ETM_MODE_TRACE_ERR		BIT(26)
 617#define ETM_MODE_VIEWINST_STARTSTOP	BIT(27)
 618#define ETMv4_MODE_ALL			(GENMASK(27, 0) | \
 619					 ETM_MODE_EXCL_KERN | \
 620					 ETM_MODE_EXCL_USER)
 621
 622/*
 623 * TRCOSLSR.OSLM advertises the OS Lock model.
 624 * OSLM[2:0] = TRCOSLSR[4:3,0]
 625 *
 626 *	0b000 - Trace OS Lock is not implemented.
 627 *	0b010 - Trace OS Lock is implemented.
 628 *	0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
 629 */
 630#define ETM_OSLOCK_NI		0b000
 631#define ETM_OSLOCK_PRESENT	0b010
 632#define ETM_OSLOCK_PE		0b100
 633
 634#define ETM_OSLSR_OSLM(oslsr)	((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
 635
 636/*
 637 * TRCDEVARCH Bit field definitions
 638 * Bits[31:21]	- ARCHITECT = Always Arm Ltd.
 639 *                * Bits[31:28] = 0x4
 640 *                * Bits[27:21] = 0b0111011
 641 * Bit[20]	- PRESENT,  Indicates the presence of this register.
 642 *
 643 * Bit[19:16]	- REVISION, Revision of the architecture.
 644 *
 645 * Bit[15:0]	- ARCHID, Identifies this component as an ETM
 646 *                * Bits[15:12] - architecture version of ETM
 647 *                *             = 4 for ETMv4
 648 *                * Bits[11:0] = 0xA13, architecture part number for ETM.
 649 */
 650#define ETM_DEVARCH_ARCHITECT_MASK		GENMASK(31, 21)
 651#define ETM_DEVARCH_ARCHITECT_ARM		((0x4 << 28) | (0b0111011 << 21))
 652#define ETM_DEVARCH_PRESENT			BIT(20)
 653#define ETM_DEVARCH_REVISION_SHIFT		16
 654#define ETM_DEVARCH_REVISION_MASK		GENMASK(19, 16)
 655#define ETM_DEVARCH_REVISION(x)			\
 656	(((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
 657#define ETM_DEVARCH_ARCHID_MASK			GENMASK(15, 0)
 658#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT	12
 659#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK	GENMASK(15, 12)
 660#define ETM_DEVARCH_ARCHID_ARCH_VER(x)		\
 661	(((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
 662
 663#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver)			\
 664	(((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
 665
 666#define ETM_DEVARCH_ARCHID_ARCH_PART(x)		((x) & 0xfffUL)
 667
 668#define ETM_DEVARCH_MAKE_ARCHID(major)			\
 669	((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
 670
 671#define ETM_DEVARCH_ARCHID_ETMv4x		ETM_DEVARCH_MAKE_ARCHID(0x4)
 672#define ETM_DEVARCH_ARCHID_ETE			ETM_DEVARCH_MAKE_ARCHID(0x5)
 673
 674#define ETM_DEVARCH_ID_MASK						\
 675	(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
 676#define ETM_DEVARCH_ETMv4x_ARCH						\
 677	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
 678#define ETM_DEVARCH_ETE_ARCH						\
 679	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
 680
 681#define CS_DEVTYPE_PE_TRACE		0x00000013
 682
 683#define TRCSTATR_IDLE_BIT		0
 684#define TRCSTATR_PMSTABLE_BIT		1
 685#define ETM_DEFAULT_ADDR_COMP		0
 686
 687#define TRCSSCSRn_PC			BIT(3)
 688
 689/* PowerDown Control Register bits */
 690#define TRCPDCR_PU			BIT(3)
 691
 692#define TRCACATR_EXLEVEL_SHIFT		8
 693
 694/*
 695 * Exception level mask for Secure and Non-Secure ELs.
 696 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
 697 * The Secure and Non-Secure ELs are always to gether.
 698 * Non-secure EL3 is never implemented.
 699 * We use the following generic mask as they appear in different
 700 * registers and this can be shifted for the appropriate
 701 * fields.
 702 */
 703#define ETM_EXLEVEL_S_APP		BIT(0)	/* Secure EL0		*/
 704#define ETM_EXLEVEL_S_OS		BIT(1)	/* Secure EL1		*/
 705#define ETM_EXLEVEL_S_HYP		BIT(2)	/* Secure EL2		*/
 706#define ETM_EXLEVEL_S_MON		BIT(3)	/* Secure EL3/Monitor	*/
 707#define ETM_EXLEVEL_NS_APP		BIT(4)	/* NonSecure EL0	*/
 708#define ETM_EXLEVEL_NS_OS		BIT(5)	/* NonSecure EL1	*/
 709#define ETM_EXLEVEL_NS_HYP		BIT(6)	/* NonSecure EL2	*/
 710
 711/* access level controls in TRCACATRn */
 712#define TRCACATR_EXLEVEL_SHIFT		8
 713
 714#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT	8
 715#define ETM_TRCIDR1_ARCH_MAJOR_MASK	(0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
 716#define ETM_TRCIDR1_ARCH_MAJOR(x)	\
 717	(((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
 718#define ETM_TRCIDR1_ARCH_MINOR_SHIFT	4
 719#define ETM_TRCIDR1_ARCH_MINOR_MASK	(0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
 720#define ETM_TRCIDR1_ARCH_MINOR(x)	\
 721	(((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
 722#define ETM_TRCIDR1_ARCH_SHIFT		ETM_TRCIDR1_ARCH_MINOR_SHIFT
 723#define ETM_TRCIDR1_ARCH_MASK		\
 724	(ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
 725
 726#define ETM_TRCIDR1_ARCH_ETMv4		0x4
 727
 728/*
 729 * Driver representation of the ETM architecture.
 730 * The version of an ETM component can be detected from
 731 *
 732 * TRCDEVARCH	- CoreSight architected register
 733 *                - Bits[15:12] - Major version
 734 *                - Bits[19:16] - Minor version
 735 *
 736 * We must rely only on TRCDEVARCH for the version information. Even though,
 737 * TRCIDR1 also provides the architecture version, it is a "Trace" register
 738 * and as such must be accessed only with Trace power domain ON. This may
 739 * not be available at probe time.
 740 *
 741 * Now to make certain decisions easier based on the version
 742 * we use an internal representation of the version in the
 743 * driver, as follows :
 744 *
 745 * ETM_ARCH_VERSION[7:0], where :
 746 *      Bits[7:4] - Major version
 747 *      Bits[3:0] - Minro version
 748 */
 749#define ETM_ARCH_VERSION(major, minor)		\
 750	((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
 751#define ETM_ARCH_MAJOR_VERSION(arch)	(((arch) >> 4) & 0xfU)
 752#define ETM_ARCH_MINOR_VERSION(arch)	((arch) & 0xfU)
 753
 754#define ETM_ARCH_V4	ETM_ARCH_VERSION(4, 0)
 755#define ETM_ARCH_ETE	ETM_ARCH_VERSION(5, 0)
 756
 757/* Interpretation of resource numbers change at ETM v4.3 architecture */
 758#define ETM_ARCH_V4_3	ETM_ARCH_VERSION(4, 3)
 759
 760static inline u8 etm_devarch_to_arch(u32 devarch)
 761{
 762	return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
 763				ETM_DEVARCH_REVISION(devarch));
 764}
 765
 766enum etm_impdef_type {
 767	ETM4_IMPDEF_HISI_CORE_COMMIT,
 768	ETM4_IMPDEF_FEATURE_MAX,
 769};
 770
 771/**
 772 * struct etmv4_config - configuration information related to an ETMv4
 773 * @mode:	Controls various modes supported by this ETM.
 774 * @pe_sel:	Controls which PE to trace.
 775 * @cfg:	Controls the tracing options.
 776 * @eventctrl0: Controls the tracing of arbitrary events.
 777 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
 778 * @stallctl:	If functionality that prevents trace unit buffer overflows
 779 *		is available.
 780 * @ts_ctrl:	Controls the insertion of global timestamps in the
 781 *		trace streams.
 782 * @syncfreq:	Controls how often trace synchronization requests occur.
 783 *		the TRCCCCTLR register.
 784 * @ccctlr:	Sets the threshold value for cycle counting.
 785 * @vinst_ctrl:	Controls instruction trace filtering.
 786 * @viiectlr:	Set or read, the address range comparators.
 787 * @vissctlr:	Set, or read, the single address comparators that control the
 788 *		ViewInst start-stop logic.
 789 * @vipcssctlr:	Set, or read, which PE comparator inputs can control the
 790 *		ViewInst start-stop logic.
 791 * @seq_idx:	Sequencor index selector.
 792 * @seq_ctrl:	Control for the sequencer state transition control register.
 793 * @seq_rst:	Moves the sequencer to state 0 when a programmed event occurs.
 794 * @seq_state:	Set, or read the sequencer state.
 795 * @cntr_idx:	Counter index seletor.
 796 * @cntrldvr:	Sets or returns the reload count value for a counter.
 797 * @cntr_ctrl:	Controls the operation of a counter.
 798 * @cntr_val:	Sets or returns the value for a counter.
 799 * @res_idx:	Resource index selector.
 800 * @res_ctrl:	Controls the selection of the resources in the trace unit.
 801 * @ss_idx:	Single-shot index selector.
 802 * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
 803 * @ss_status:	The status of the corresponding single-shot comparator.
 804 * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
 805 * @addr_idx:	Address comparator index selector.
 806 * @addr_val:	Value for address comparator.
 807 * @addr_acc:	Address comparator access type.
 808 * @addr_type:	Current status of the comparator register.
 809 * @ctxid_idx:	Context ID index selector.
 810 * @ctxid_pid:	Value of the context ID comparator.
 811 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
 812 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
 813 * @vmid_idx:	VM ID index selector.
 814 * @vmid_val:	Value of the VM ID comparator.
 815 * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
 816 * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
 817 * @ext_inp:	External input selection.
 818 * @s_ex_level: Secure ELs where tracing is supported.
 819 */
 820struct etmv4_config {
 821	u64				mode;
 822	u32				pe_sel;
 823	u32				cfg;
 824	u32				eventctrl0;
 825	u32				eventctrl1;
 826	u32				stall_ctrl;
 827	u32				ts_ctrl;
 828	u32				syncfreq;
 829	u32				ccctlr;
 830	u32				bb_ctrl;
 831	u32				vinst_ctrl;
 832	u32				viiectlr;
 833	u32				vissctlr;
 834	u32				vipcssctlr;
 835	u8				seq_idx;
 836	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
 837	u32				seq_rst;
 838	u32				seq_state;
 839	u8				cntr_idx;
 840	u32				cntrldvr[ETMv4_MAX_CNTR];
 841	u32				cntr_ctrl[ETMv4_MAX_CNTR];
 842	u32				cntr_val[ETMv4_MAX_CNTR];
 843	u8				res_idx;
 844	u32				res_ctrl[ETM_MAX_RES_SEL];
 845	u8				ss_idx;
 846	u32				ss_ctrl[ETM_MAX_SS_CMP];
 847	u32				ss_status[ETM_MAX_SS_CMP];
 848	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
 849	u8				addr_idx;
 850	u64				addr_val[ETM_MAX_SINGLE_ADDR_CMP];
 851	u64				addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
 852	u8				addr_type[ETM_MAX_SINGLE_ADDR_CMP];
 853	u8				ctxid_idx;
 854	u64				ctxid_pid[ETMv4_MAX_CTXID_CMP];
 855	u32				ctxid_mask0;
 856	u32				ctxid_mask1;
 857	u8				vmid_idx;
 858	u64				vmid_val[ETM_MAX_VMID_CMP];
 859	u32				vmid_mask0;
 860	u32				vmid_mask1;
 861	u32				ext_inp;
 862	u8				s_ex_level;
 863};
 864
 865/**
 866 * struct etm4_save_state - state to be preserved when ETM is without power
 867 */
 868struct etmv4_save_state {
 869	u32	trcprocselr;
 870	u32	trcconfigr;
 871	u32	trcauxctlr;
 872	u32	trceventctl0r;
 873	u32	trceventctl1r;
 874	u32	trcstallctlr;
 875	u32	trctsctlr;
 876	u32	trcsyncpr;
 877	u32	trcccctlr;
 878	u32	trcbbctlr;
 879	u32	trctraceidr;
 880	u32	trcqctlr;
 881
 882	u32	trcvictlr;
 883	u32	trcviiectlr;
 884	u32	trcvissctlr;
 885	u32	trcvipcssctlr;
 886
 887	u32	trcseqevr[ETM_MAX_SEQ_STATES];
 888	u32	trcseqrstevr;
 889	u32	trcseqstr;
 890	u32	trcextinselr;
 891	u32	trccntrldvr[ETMv4_MAX_CNTR];
 892	u32	trccntctlr[ETMv4_MAX_CNTR];
 893	u32	trccntvr[ETMv4_MAX_CNTR];
 894
 895	u32	trcrsctlr[ETM_MAX_RES_SEL];
 896
 897	u32	trcssccr[ETM_MAX_SS_CMP];
 898	u32	trcsscsr[ETM_MAX_SS_CMP];
 899	u32	trcsspcicr[ETM_MAX_SS_CMP];
 900
 901	u64	trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
 902	u64	trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
 903	u64	trccidcvr[ETMv4_MAX_CTXID_CMP];
 904	u64	trcvmidcvr[ETM_MAX_VMID_CMP];
 905	u32	trccidcctlr0;
 906	u32	trccidcctlr1;
 907	u32	trcvmidcctlr0;
 908	u32	trcvmidcctlr1;
 909
 910	u32	trcclaimset;
 911
 912	u32	cntr_val[ETMv4_MAX_CNTR];
 913	u32	seq_state;
 914	u32	vinst_ctrl;
 915	u32	ss_status[ETM_MAX_SS_CMP];
 916
 917	u32	trcpdcr;
 918};
 919
 920/**
 921 * struct etm4_drvdata - specifics associated to an ETM component
 922 * @pclk:       APB clock if present, otherwise NULL
 923 * @atclk:      Optional clock for the core parts of the ETMv4.
 924 * @base:       Memory mapped base address for this component.
 925 * @csdev:      Component vitals needed by the framework.
 926 * @spinlock:   Only one at a time pls.
 927 * @mode:	This tracer's mode, i.e sysFS, Perf or disabled.
 928 * @cpu:        The cpu this component is affined to.
 929 * @arch:       ETM architecture version.
 930 * @nr_pe:	The number of processing entity available for tracing.
 931 * @nr_pe_cmp:	The number of processing entity comparator inputs that are
 932 *		available for tracing.
 933 * @nr_addr_cmp:Number of pairs of address comparators available
 934 *		as found in ETMIDR4 0-3.
 935 * @nr_cntr:    Number of counters as found in ETMIDR5 bit 28-30.
 936 * @nr_ext_inp: Number of external input.
 937 * @numcidc:	Number of contextID comparators.
 938 * @numvmidc:	Number of VMID comparators.
 939 * @nrseqstate: The number of sequencer states that are implemented.
 940 * @nr_event:	Indicates how many events the trace unit support.
 941 * @nr_resource:The number of resource selection pairs available for tracing.
 942 * @nr_ss_cmp:	Number of single-shot comparator controls that are available.
 943 * @trcid:	value of the current ID for this component.
 944 * @trcid_size: Indicates the trace ID width.
 945 * @ts_size:	Global timestamp size field.
 946 * @ctxid_size:	Size of the context ID field to consider.
 947 * @vmid_size:	Size of the VM ID comparator to consider.
 948 * @ccsize:	Indicates the size of the cycle counter in bits.
 949 * @ccitmin:	minimum value that can be programmed in
 950 * @s_ex_level:	In secure state, indicates whether instruction tracing is
 951 *		supported for the corresponding Exception level.
 952 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
 953 *		supported for the corresponding Exception level.
 954 * @sticky_enable: true if ETM base configuration has been done.
 955 * @boot_enable:True if we should start tracing at boot time.
 956 * @os_unlock:  True if access to management registers is allowed.
 957 * @instrp0:	Tracing of load and store instructions
 958 *		as P0 elements is supported.
 959 * @q_filt:	Q element filtering support, if Q elements are supported.
 960 * @trcbb:	Indicates if the trace unit supports branch broadcast tracing.
 961 * @trccond:	If the trace unit supports conditional
 962 *		instruction tracing.
 963 * @retstack:	Indicates if the implementation supports a return stack.
 964 * @trccci:	Indicates if the trace unit supports cycle counting
 965 *		for instruction.
 966 * @q_support:	Q element support characteristics.
 967 * @trc_error:	Whether a trace unit can trace a system
 968 *		error exception.
 969 * @syncpr:	Indicates if an implementation has a fixed
 970 *		synchronization period.
 971 * @stall_ctrl:	Enables trace unit functionality that prevents trace
 972 *		unit buffer overflows.
 973 * @sysstall:	Does the system support stall control of the PE?
 974 * @nooverflow:	Indicate if overflow prevention is supported.
 975 * @atbtrig:	If the implementation can support ATB triggers
 976 * @lpoverride:	If the implementation can support low-power state over.
 977 * @trfcr:	If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
 978 *		allows tracing at all ELs. We don't want to compute this
 979 *		at runtime, due to the additional setting of TRFCR_CX when
 980 *		in EL2. Otherwise, 0.
 981 * @config:	structure holding configuration parameters.
 982 * @save_state:	State to be preserved across power loss
 983 * @skip_power_up: Indicates if an implementation can skip powering up
 984 *		   the trace unit.
 985 * @paused:	Indicates if the trace unit is paused.
 986 * @arch_features: Bitmap of arch features of etmv4 devices.
 987 */
 988struct etmv4_drvdata {
 989	struct clk			*pclk;
 990	struct clk			*atclk;
 991	void __iomem			*base;
 992	struct coresight_device		*csdev;
 993	raw_spinlock_t			spinlock;
 994	int				cpu;
 995	u8				arch;
 996	u8				nr_pe;
 997	u8				nr_pe_cmp;
 998	u8				nr_addr_cmp;
 999	u8				nr_cntr;
1000	u8				nr_ext_inp;
1001	u8				numcidc;
1002	u8				numextinsel;
1003	u8				numvmidc;
1004	u8				nrseqstate;
1005	u8				nr_event;
1006	u8				nr_resource;
1007	u8				nr_ss_cmp;
1008	u8				trcid;
1009	u8				trcid_size;
1010	u8				ts_size;
1011	u8				ctxid_size;
1012	u8				vmid_size;
1013	u8				ccsize;
1014	u16				ccitmin;
1015	u8				s_ex_level;
1016	u8				ns_ex_level;
1017	u8				q_support;
1018	u8				os_lock_model;
1019	bool				sticky_enable;
1020	bool				boot_enable;
1021	bool				os_unlock;
1022	bool				instrp0;
1023	bool				q_filt;
1024	bool				trcbb;
1025	bool				trccond;
1026	bool				retstack;
1027	bool				trccci;
1028	bool				trc_error;
1029	bool				syncpr;
1030	bool				stallctl;
1031	bool				sysstall;
1032	bool				nooverflow;
1033	bool				atbtrig;
1034	bool				lpoverride;
1035	u64				trfcr;
1036	struct etmv4_config		config;
1037	struct etmv4_save_state		*save_state;
1038	bool				skip_power_up;
1039	bool				paused;
1040	DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
1041};
1042
1043/* Address comparator access types */
1044enum etm_addr_acctype {
1045	TRCACATRn_TYPE_ADDR,
1046	TRCACATRn_TYPE_DATA_LOAD_ADDR,
1047	TRCACATRn_TYPE_DATA_STORE_ADDR,
1048	TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR,
1049};
1050
1051/* Address comparator context types */
1052enum etm_addr_ctxtype {
1053	ETM_CTX_NONE,
1054	ETM_CTX_CTXID,
1055	ETM_CTX_VMID,
1056	ETM_CTX_CTXID_VMID,
1057};
1058
1059extern const struct attribute_group *coresight_etmv4_groups[];
1060void etm4_config_trace_mode(struct etmv4_config *config);
1061
1062u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
1063void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1064
1065static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1066{
1067	return drvdata->arch >= ETM_ARCH_ETE;
1068}
1069
1070void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
1071#endif
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