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coresight-etm4x-core.c
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linux-6.19.14/drivers/hwtracing/coresight/coresight-etm4x-core.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/acpi.h> 7#include <linux/bitfield.h> 8#include <linux/bitops.h> 9#include <linux/kernel.h> 10#include <linux/kvm_host.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/types.h> 14#include <linux/device.h> 15#include <linux/io.h> 16#include <linux/err.h> 17#include <linux/fs.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/smp.h> 21#include <linux/sysfs.h> 22#include <linux/stat.h> 23#include <linux/clk.h> 24#include <linux/cpu.h> 25#include <linux/cpu_pm.h> 26#include <linux/coresight.h> 27#include <linux/coresight-pmu.h> 28#include <linux/amba/bus.h> 29#include <linux/seq_file.h> 30#include <linux/uaccess.h> 31#include <linux/perf_event.h> 32#include <linux/platform_device.h> 33#include <linux/pm_runtime.h> 34#include <linux/property.h> 35#include <linux/clk/clk-conf.h> 36 37#include <asm/barrier.h> 38#include <asm/sections.h> 39#include <asm/sysreg.h> 40#include <asm/local.h> 41#include <asm/virt.h> 42 43#include "coresight-etm4x.h" 44#include "coresight-etm-perf.h" 45#include "coresight-etm4x-cfg.h" 46#include "coresight-self-hosted-trace.h" 47#include "coresight-syscfg.h" 48#include "coresight-trace-id.h" 49 50static int boot_enable; 51module_param(boot_enable, int, 0444); 52MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); 53 54#define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */ 55#define PARAM_PM_SAVE_NEVER 1 /* never save any state */ 56#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ 57 58static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; 59module_param(pm_save_enable, int, 0444); 60MODULE_PARM_DESC(pm_save_enable, 61 "Save/restore state on power down: 1 = never, 2 = self-hosted"); 62 63static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; 64static void etm4_set_default_config(struct etmv4_config *config); 65static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 66 struct perf_event *event); 67static u64 etm4_get_access_type(struct etmv4_config *config); 68 69static enum cpuhp_state hp_online; 70 71struct etm4_init_arg { 72 struct device *dev; 73 struct csdev_access *csa; 74}; 75 76static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); 77static int etm4_probe_cpu(unsigned int cpu); 78 79/* 80 * Check if TRCSSPCICRn(i) is implemented for a given instance. 81 * 82 * TRCSSPCICRn is implemented only if : 83 * TRCSSPCICR<n> is present only if all of the following are true: 84 * TRCIDR4.NUMSSCC > n. 85 * TRCIDR4.NUMPC > 0b0000 . 86 * TRCSSCSR<n>.PC == 0b1 87 */ 88static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) 89{ 90 return (n < drvdata->nr_ss_cmp) && 91 drvdata->nr_pe && 92 (drvdata->config.ss_status[n] & TRCSSCSRn_PC); 93} 94 95u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 96{ 97 u64 res = 0; 98 99 switch (offset) { 100 ETM4x_READ_SYSREG_CASES(res) 101 default : 102 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n", 103 offset); 104 } 105 106 if (!_relaxed) 107 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 108 109 return res; 110} 111 112void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 113{ 114 if (!_relaxed) 115 __io_bw(); /* Imitate the !relaxed I/O helpers */ 116 if (!_64bit) 117 val &= GENMASK(31, 0); 118 119 switch (offset) { 120 ETM4x_WRITE_SYSREG_CASES(val) 121 default : 122 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n", 123 offset); 124 } 125} 126 127static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 128{ 129 u64 res = 0; 130 131 switch (offset) { 132 ETE_READ_CASES(res) 133 default : 134 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n", 135 offset); 136 } 137 138 if (!_relaxed) 139 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 140 141 return res; 142} 143 144static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 145{ 146 if (!_relaxed) 147 __io_bw(); /* Imitate the !relaxed I/O helpers */ 148 if (!_64bit) 149 val &= GENMASK(31, 0); 150 151 switch (offset) { 152 ETE_WRITE_CASES(val) 153 default : 154 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n", 155 offset); 156 } 157} 158 159static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, 160 struct csdev_access *csa) 161{ 162 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); 163 164 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); 165} 166 167static void etm_write_os_lock(struct etmv4_drvdata *drvdata, 168 struct csdev_access *csa, u32 val) 169{ 170 val = !!val; 171 172 switch (drvdata->os_lock_model) { 173 case ETM_OSLOCK_PRESENT: 174 etm4x_relaxed_write32(csa, val, TRCOSLAR); 175 break; 176 case ETM_OSLOCK_PE: 177 write_sysreg_s(val, SYS_OSLAR_EL1); 178 break; 179 default: 180 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", 181 smp_processor_id(), drvdata->os_lock_model); 182 fallthrough; 183 case ETM_OSLOCK_NI: 184 return; 185 } 186 isb(); 187} 188 189static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, 190 struct csdev_access *csa) 191{ 192 WARN_ON(drvdata->cpu != smp_processor_id()); 193 194 /* Writing 0 to OS Lock unlocks the trace unit registers */ 195 etm_write_os_lock(drvdata, csa, 0x0); 196 drvdata->os_unlock = true; 197} 198 199static void etm4_os_unlock(struct etmv4_drvdata *drvdata) 200{ 201 if (!WARN_ON(!drvdata->csdev)) 202 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); 203} 204 205static void etm4_os_lock(struct etmv4_drvdata *drvdata) 206{ 207 if (WARN_ON(!drvdata->csdev)) 208 return; 209 /* Writing 0x1 to OS Lock locks the trace registers */ 210 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1); 211 drvdata->os_unlock = false; 212} 213 214static void etm4_cs_lock(struct etmv4_drvdata *drvdata, 215 struct csdev_access *csa) 216{ 217 /* Software Lock is only accessible via memory mapped interface */ 218 if (csa->io_mem) 219 CS_LOCK(csa->base); 220} 221 222static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, 223 struct csdev_access *csa) 224{ 225 if (csa->io_mem) 226 CS_UNLOCK(csa->base); 227} 228 229static int etm4_cpu_id(struct coresight_device *csdev) 230{ 231 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 232 233 return drvdata->cpu; 234} 235 236void etm4_release_trace_id(struct etmv4_drvdata *drvdata) 237{ 238 coresight_trace_id_put_cpu_id(drvdata->cpu); 239} 240 241struct etm4_enable_arg { 242 struct etmv4_drvdata *drvdata; 243 int rc; 244}; 245 246/* 247 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs. 248 * When the CPU supports FEAT_TRF, we could move the ETM to a trace 249 * prohibited state by filtering the Exception levels via TRFCR_EL1. 250 */ 251static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) 252{ 253 u64 trfcr; 254 255 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 256 if (!drvdata->trfcr) 257 return; 258 259 trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); 260 261 write_trfcr(trfcr); 262 kvm_tracing_set_el1_configuration(trfcr); 263} 264 265static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) 266{ 267 u64 trfcr = drvdata->trfcr; 268 269 if (drvdata->config.mode & ETM_MODE_EXCL_KERN) 270 trfcr &= ~TRFCR_EL1_ExTRE; 271 if (drvdata->config.mode & ETM_MODE_EXCL_USER) 272 trfcr &= ~TRFCR_EL1_E0TRE; 273 274 return trfcr; 275} 276 277/* 278 * etm4x_allow_trace - Allow CPU tracing in the respective ELs, 279 * as configured by the drvdata->config.mode for the current 280 * session. Even though we have TRCVICTLR bits to filter the 281 * trace in the ELs, it doesn't prevent the ETM from generating 282 * a packet (e.g, TraceInfo) that might contain the addresses from 283 * the excluded levels. Thus we use the additional controls provided 284 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace 285 * is generated for the excluded ELs. 286 */ 287static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) 288{ 289 u64 trfcr, guest_trfcr; 290 291 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 292 if (!drvdata->trfcr) 293 return; 294 295 if (drvdata->config.mode & ETM_MODE_EXCL_HOST) 296 trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); 297 else 298 trfcr = etm4x_get_kern_user_filter(drvdata); 299 300 write_trfcr(trfcr); 301 302 /* Set filters for guests and pass to KVM */ 303 if (drvdata->config.mode & ETM_MODE_EXCL_GUEST) 304 guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); 305 else 306 guest_trfcr = etm4x_get_kern_user_filter(drvdata); 307 308 /* TRFCR_EL1 doesn't have CX so mask it out. */ 309 guest_trfcr &= ~TRFCR_EL2_CX; 310 kvm_tracing_set_el1_configuration(guest_trfcr); 311} 312 313#ifdef CONFIG_ETM4X_IMPDEF_FEATURE 314 315#define HISI_HIP08_AMBA_ID 0x000b6d01 316#define ETM4_AMBA_MASK 0xfffff 317#define HISI_HIP08_CORE_COMMIT_MASK 0x3000 318#define HISI_HIP08_CORE_COMMIT_SHIFT 12 319#define HISI_HIP08_CORE_COMMIT_FULL 0b00 320#define HISI_HIP08_CORE_COMMIT_LVL_1 0b01 321#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) 322 323struct etm4_arch_features { 324 void (*arch_callback)(bool enable); 325}; 326 327static bool etm4_hisi_match_pid(unsigned int id) 328{ 329 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; 330} 331 332static void etm4_hisi_config_core_commit(bool enable) 333{ 334 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 : 335 HISI_HIP08_CORE_COMMIT_FULL; 336 u64 val; 337 338 /* 339 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together 340 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01, 341 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1 342 * speed(minimun value). So bit 12 and 13 should be cleared together. 343 */ 344 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); 345 val &= ~HISI_HIP08_CORE_COMMIT_MASK; 346 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT; 347 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG); 348} 349 350static struct etm4_arch_features etm4_features[] = { 351 [ETM4_IMPDEF_HISI_CORE_COMMIT] = { 352 .arch_callback = etm4_hisi_config_core_commit, 353 }, 354 {}, 355}; 356 357static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 358{ 359 struct etm4_arch_features *ftr; 360 int bit; 361 362 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 363 ftr = &etm4_features[bit]; 364 365 if (ftr->arch_callback) 366 ftr->arch_callback(true); 367 } 368} 369 370static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 371{ 372 struct etm4_arch_features *ftr; 373 int bit; 374 375 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 376 ftr = &etm4_features[bit]; 377 378 if (ftr->arch_callback) 379 ftr->arch_callback(false); 380 } 381} 382 383static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 384 struct csdev_access *csa) 385{ 386 /* 387 * TRCPIDR* registers are not required for ETMs with system 388 * instructions. They must be identified by the MIDR+REVIDRs. 389 * Skip the TRCPID checks for now. 390 */ 391 if (!csa->io_mem) 392 return; 393 394 if (etm4_hisi_match_pid(coresight_get_pid(csa))) 395 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); 396} 397#else 398static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 399{ 400} 401 402static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 403{ 404} 405 406static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 407 struct csdev_access *csa) 408{ 409} 410#endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ 411 412static void etm4x_sys_ins_barrier(struct csdev_access *csa, u32 offset, int pos, int val) 413{ 414 if (!csa->io_mem) 415 isb(); 416} 417 418/* 419 * etm4x_wait_status: Poll for TRCSTATR.<pos> == <val>. While using system 420 * instruction to access the trace unit, each access must be separated by a 421 * synchronization barrier. See ARM IHI0064H.b section "4.3.7 Synchronization of 422 * register updates", for system instructions section, in "Notes": 423 * 424 * "In particular, whenever disabling or enabling the trace unit, a poll of 425 * TRCSTATR needs explicit synchronization between each read of TRCSTATR" 426 */ 427static int etm4x_wait_status(struct csdev_access *csa, int pos, int val) 428{ 429 if (!csa->io_mem) 430 return coresight_timeout_action(csa, TRCSTATR, pos, val, 431 etm4x_sys_ins_barrier); 432 return coresight_timeout(csa, TRCSTATR, pos, val); 433} 434 435static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) 436{ 437 struct coresight_device *csdev = drvdata->csdev; 438 struct device *etm_dev = &csdev->dev; 439 struct csdev_access *csa = &csdev->access; 440 441 /* 442 * ETE mandates that the TRCRSR is written to before 443 * enabling it. 444 */ 445 if (etm4x_is_ete(drvdata)) 446 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); 447 448 etm4x_allow_trace(drvdata); 449 450 /* 451 * According to software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), 452 * execute a Context synchronization event to guarantee the trace unit 453 * will observe the new values of the System registers. 454 */ 455 if (!csa->io_mem) 456 isb(); 457 458 /* Enable the trace unit */ 459 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); 460 461 /* 462 * As recommended by section 4.3.7 ("Synchronization when using system 463 * instructions to progrom the trace unit") of ARM IHI 0064H.b, the 464 * self-hosted trace analyzer must perform a Context synchronization 465 * event between writing to the TRCPRGCTLR and reading the TRCSTATR. 466 */ 467 if (!csa->io_mem) 468 isb(); 469 470 /* wait for TRCSTATR.IDLE to go back down to '0' */ 471 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0)) { 472 dev_err(etm_dev, 473 "timeout while waiting for Idle Trace Status\n"); 474 return -ETIME; 475 } 476 477 /* 478 * As recommended in section 4.3.7 (Synchronization of register updates) 479 * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an 480 * ISB instruction after programming the trace unit registers. 481 * 482 * For the memory-mapped interface, the registers are mapped as Device 483 * type (Device-nGnRE). Reading back the value of any register in the 484 * trace unit ensures that all writes have completed. Therefore, polling 485 * on TRCSTATR guarantees that the writing TRCPRGCTLR is complete, and 486 * no explicit dsb() is required at here. 487 */ 488 isb(); 489 490 return 0; 491} 492 493static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 494{ 495 int i, rc; 496 struct etmv4_config *config = &drvdata->config; 497 struct coresight_device *csdev = drvdata->csdev; 498 struct device *etm_dev = &csdev->dev; 499 struct csdev_access *csa = &csdev->access; 500 501 502 etm4_cs_unlock(drvdata, csa); 503 etm4_enable_arch_specific(drvdata); 504 505 etm4_os_unlock(drvdata); 506 507 rc = coresight_claim_device_unlocked(csdev); 508 if (rc) 509 goto done; 510 511 /* Disable the trace unit before programming trace registers */ 512 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); 513 514 /* 515 * If we use system instructions, we need to synchronize the 516 * write to the TRCPRGCTLR, before accessing the TRCSTATR. 517 * See ARM IHI0064F, section 518 * "4.3.7 Synchronization of register updates" 519 */ 520 if (!csa->io_mem) 521 isb(); 522 523 /* wait for TRCSTATR.IDLE to go up */ 524 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) 525 dev_err(etm_dev, 526 "timeout while waiting for Idle Trace Status\n"); 527 if (drvdata->nr_pe) 528 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); 529 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); 530 /* nothing specific implemented */ 531 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); 532 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); 533 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); 534 if (drvdata->stallctl) 535 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); 536 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); 537 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); 538 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); 539 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); 540 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); 541 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); 542 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); 543 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); 544 if (drvdata->nr_pe_cmp) 545 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); 546 for (i = 0; i < drvdata->nrseqstate - 1; i++) 547 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); 548 if (drvdata->nrseqstate) { 549 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); 550 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); 551 } 552 if (drvdata->numextinsel) 553 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 554 for (i = 0; i < drvdata->nr_cntr; i++) { 555 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); 556 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); 557 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); 558 } 559 560 /* 561 * Resource selector pair 0 is always implemented and reserved. As 562 * such start at 2. 563 */ 564 for (i = 2; i < drvdata->nr_resource * 2; i++) 565 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); 566 567 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 568 /* always clear status bit on restart if using single-shot */ 569 if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) 570 config->ss_status[i] &= ~TRCSSCSRn_STATUS; 571 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); 572 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); 573 if (etm4x_sspcicrn_present(drvdata, i)) 574 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); 575 } 576 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 577 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); 578 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); 579 } 580 for (i = 0; i < drvdata->numcidc; i++) 581 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); 582 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); 583 if (drvdata->numcidc > 4) 584 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); 585 586 for (i = 0; i < drvdata->numvmidc; i++) 587 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); 588 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); 589 if (drvdata->numvmidc > 4) 590 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); 591 592 if (!drvdata->skip_power_up) { 593 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); 594 595 /* 596 * Request to keep the trace unit powered and also 597 * emulation of powerdown 598 */ 599 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); 600 } 601 602 if (!drvdata->paused) 603 rc = etm4_enable_trace_unit(drvdata); 604done: 605 etm4_cs_lock(drvdata, csa); 606 607 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", 608 drvdata->cpu, rc); 609 return rc; 610} 611 612static void etm4_enable_sysfs_smp_call(void *info) 613{ 614 struct etm4_enable_arg *arg = info; 615 struct coresight_device *csdev; 616 617 if (WARN_ON(!arg)) 618 return; 619 620 csdev = arg->drvdata->csdev; 621 if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { 622 /* Someone is already using the tracer */ 623 arg->rc = -EBUSY; 624 return; 625 } 626 627 arg->rc = etm4_enable_hw(arg->drvdata); 628 629 /* The tracer didn't start */ 630 if (arg->rc) 631 coresight_set_mode(csdev, CS_MODE_DISABLED); 632} 633 634/* 635 * The goal of function etm4_config_timestamp_event() is to configure a 636 * counter that will tell the tracer to emit a timestamp packet when it 637 * reaches zero. This is done in order to get a more fine grained idea 638 * of when instructions are executed so that they can be correlated 639 * with execution on other CPUs. 640 * 641 * To do this the counter itself is configured to self reload and 642 * TRCRSCTLR1 (always true) used to get the counter to decrement. From 643 * there a resource selector is configured with the counter and the 644 * timestamp control register to use the resource selector to trigger the 645 * event that will insert a timestamp packet in the stream. 646 */ 647static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) 648{ 649 int ctridx, ret = -EINVAL; 650 int counter, rselector; 651 u32 val = 0; 652 struct etmv4_config *config = &drvdata->config; 653 654 /* No point in trying if we don't have at least one counter */ 655 if (!drvdata->nr_cntr) 656 goto out; 657 658 /* Find a counter that hasn't been initialised */ 659 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) 660 if (config->cntr_val[ctridx] == 0) 661 break; 662 663 /* All the counters have been configured already, bail out */ 664 if (ctridx == drvdata->nr_cntr) { 665 pr_debug("%s: no available counter found\n", __func__); 666 ret = -ENOSPC; 667 goto out; 668 } 669 670 /* 671 * Searching for an available resource selector to use, starting at 672 * '2' since every implementation has at least 2 resource selector. 673 * ETMIDR4 gives the number of resource selector _pairs_, 674 * hence multiply by 2. 675 */ 676 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) 677 if (!config->res_ctrl[rselector]) 678 break; 679 680 if (rselector == drvdata->nr_resource * 2) { 681 pr_debug("%s: no available resource selector found\n", 682 __func__); 683 ret = -ENOSPC; 684 goto out; 685 } 686 687 /* Remember what counter we used */ 688 counter = 1 << ctridx; 689 690 /* 691 * Initialise original and reload counter value to the smallest 692 * possible value in order to get as much precision as we can. 693 */ 694 config->cntr_val[ctridx] = 1; 695 config->cntrldvr[ctridx] = 1; 696 697 /* Set the trace counter control register */ 698 val = 0x1 << 16 | /* Bit 16, reload counter automatically */ 699 0x0 << 7 | /* Select single resource selector */ 700 0x1; /* Resource selector 1, i.e always true */ 701 702 config->cntr_ctrl[ctridx] = val; 703 704 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ 705 counter << 0; /* Counter to use */ 706 707 config->res_ctrl[rselector] = val; 708 709 val = 0x0 << 7 | /* Select single resource selector */ 710 rselector; /* Resource selector */ 711 712 config->ts_ctrl = val; 713 714 ret = 0; 715out: 716 return ret; 717} 718 719static int etm4_parse_event_config(struct coresight_device *csdev, 720 struct perf_event *event) 721{ 722 int ret = 0; 723 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 724 struct etmv4_config *config = &drvdata->config; 725 struct perf_event_attr *attr = &event->attr; 726 unsigned long cfg_hash; 727 int preset, cc_threshold; 728 729 /* Clear configuration from previous run */ 730 memset(config, 0, sizeof(struct etmv4_config)); 731 732 if (attr->exclude_kernel) 733 config->mode = ETM_MODE_EXCL_KERN; 734 735 if (attr->exclude_user) 736 config->mode = ETM_MODE_EXCL_USER; 737 738 if (attr->exclude_host) 739 config->mode |= ETM_MODE_EXCL_HOST; 740 741 if (attr->exclude_guest) 742 config->mode |= ETM_MODE_EXCL_GUEST; 743 744 /* Always start from the default config */ 745 etm4_set_default_config(config); 746 747 /* Configure filters specified on the perf cmd line, if any. */ 748 ret = etm4_set_event_filters(drvdata, event); 749 if (ret) 750 goto out; 751 752 /* Go from generic option to ETMv4 specifics */ 753 if (attr->config & BIT(ETM_OPT_CYCACC)) { 754 config->cfg |= TRCCONFIGR_CCI; 755 /* TRM: Must program this for cycacc to work */ 756 cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; 757 if (!cc_threshold) 758 cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; 759 if (cc_threshold < drvdata->ccitmin) 760 cc_threshold = drvdata->ccitmin; 761 config->ccctlr = cc_threshold; 762 } 763 if (attr->config & BIT(ETM_OPT_TS)) { 764 /* 765 * Configure timestamps to be emitted at regular intervals in 766 * order to correlate instructions executed on different CPUs 767 * (CPU-wide trace scenarios). 768 */ 769 ret = etm4_config_timestamp_event(drvdata); 770 771 /* 772 * No need to go further if timestamp intervals can't 773 * be configured. 774 */ 775 if (ret) 776 goto out; 777 778 /* bit[11], Global timestamp tracing bit */ 779 config->cfg |= TRCCONFIGR_TS; 780 } 781 782 /* Only trace contextID when runs in root PID namespace */ 783 if ((attr->config & BIT(ETM_OPT_CTXTID)) && 784 task_is_in_init_pid_ns(current)) 785 /* bit[6], Context ID tracing bit */ 786 config->cfg |= TRCCONFIGR_CID; 787 788 /* 789 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID 790 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the 791 * kernel is not running in EL2. 792 */ 793 if (attr->config & BIT(ETM_OPT_CTXTID2)) { 794 if (!is_kernel_in_hyp_mode()) { 795 ret = -EINVAL; 796 goto out; 797 } 798 /* Only trace virtual contextID when runs in root PID namespace */ 799 if (task_is_in_init_pid_ns(current)) 800 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; 801 } 802 803 /* return stack - enable if selected and supported */ 804 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) 805 /* bit[12], Return stack enable bit */ 806 config->cfg |= TRCCONFIGR_RS; 807 808 /* 809 * Set any selected configuration and preset. 810 * 811 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset) 812 * in the perf attributes defined in coresight-etm-perf.c. 813 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config. 814 * A zero configid means no configuration active, preset = 0 means no preset selected. 815 */ 816 if (attr->config2 & GENMASK_ULL(63, 32)) { 817 cfg_hash = (u32)(attr->config2 >> 32); 818 preset = attr->config & 0xF; 819 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 820 } 821 822 /* branch broadcast - enable if selected and supported */ 823 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { 824 if (!drvdata->trcbb) { 825 /* 826 * Missing BB support could cause silent decode errors 827 * so fail to open if it's not supported. 828 */ 829 ret = -EINVAL; 830 goto out; 831 } else { 832 config->cfg |= BIT(ETM4_CFG_BIT_BB); 833 } 834 } 835 836out: 837 return ret; 838} 839 840static int etm4_enable_perf(struct coresight_device *csdev, 841 struct perf_event *event, 842 struct coresight_path *path) 843{ 844 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 845 int ret; 846 847 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 848 return -EINVAL; 849 850 if (!coresight_take_mode(csdev, CS_MODE_PERF)) 851 return -EBUSY; 852 853 /* Configure the tracer based on the session's specifics */ 854 ret = etm4_parse_event_config(csdev, event); 855 if (ret) 856 goto out; 857 858 drvdata->trcid = path->trace_id; 859 860 /* Populate pause state */ 861 drvdata->paused = !!READ_ONCE(event->hw.aux_paused); 862 863 /* And enable it */ 864 ret = etm4_enable_hw(drvdata); 865 866out: 867 /* Failed to start tracer; roll back to DISABLED mode */ 868 if (ret) 869 coresight_set_mode(csdev, CS_MODE_DISABLED); 870 return ret; 871} 872 873static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) 874{ 875 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 876 struct etm4_enable_arg arg = { }; 877 unsigned long cfg_hash; 878 int ret, preset; 879 880 /* enable any config activated by configfs */ 881 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); 882 if (cfg_hash) { 883 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 884 if (ret) 885 return ret; 886 } 887 888 raw_spin_lock(&drvdata->spinlock); 889 890 drvdata->trcid = path->trace_id; 891 892 /* Tracer will never be paused in sysfs mode */ 893 drvdata->paused = false; 894 895 /* 896 * Executing etm4_enable_hw on the cpu whose ETM is being enabled 897 * ensures that register writes occur when cpu is powered. 898 */ 899 arg.drvdata = drvdata; 900 ret = smp_call_function_single(drvdata->cpu, 901 etm4_enable_sysfs_smp_call, &arg, 1); 902 if (!ret) 903 ret = arg.rc; 904 if (!ret) 905 drvdata->sticky_enable = true; 906 907 if (ret) 908 etm4_release_trace_id(drvdata); 909 910 raw_spin_unlock(&drvdata->spinlock); 911 912 if (!ret) 913 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); 914 return ret; 915} 916 917static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, 918 enum cs_mode mode, struct coresight_path *path) 919{ 920 int ret; 921 922 switch (mode) { 923 case CS_MODE_SYSFS: 924 ret = etm4_enable_sysfs(csdev, path); 925 break; 926 case CS_MODE_PERF: 927 ret = etm4_enable_perf(csdev, event, path); 928 break; 929 default: 930 ret = -EINVAL; 931 } 932 933 return ret; 934} 935 936static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) 937{ 938 u32 control; 939 struct coresight_device *csdev = drvdata->csdev; 940 struct device *etm_dev = &csdev->dev; 941 struct csdev_access *csa = &csdev->access; 942 943 control = etm4x_relaxed_read32(csa, TRCPRGCTLR); 944 945 /* EN, bit[0] Trace unit enable bit */ 946 control &= ~0x1; 947 948 /* 949 * If the CPU supports v8.4 Trace filter Control, 950 * set the ETM to trace prohibited region. 951 */ 952 etm4x_prohibit_trace(drvdata); 953 /* 954 * Prevent being speculative at the point of disabling the trace unit, 955 * as recommended by section 7.3.77 ("TRCVICTLR, ViewInst Main Control 956 * Register, SSTATUS") of ARM IHI 0064D 957 */ 958 dsb(sy); 959 /* 960 * According to software usage VKHHY in Arm ARM (ARM DDI 0487 L.a), 961 * execute a Context synchronization event to guarantee no new 962 * program-flow trace is generated. 963 */ 964 isb(); 965 /* Trace synchronization barrier, is a nop if not supported */ 966 tsb_csync(); 967 etm4x_relaxed_write32(csa, control, TRCPRGCTLR); 968 969 /* 970 * As recommended by section 4.3.7 ("Synchronization when using system 971 * instructions to progrom the trace unit") of ARM IHI 0064H.b, the 972 * self-hosted trace analyzer must perform a Context synchronization 973 * event between writing to the TRCPRGCTLR and reading the TRCSTATR. 974 */ 975 if (!csa->io_mem) 976 isb(); 977 978 /* wait for TRCSTATR.PMSTABLE to go to '1' */ 979 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) 980 dev_err(etm_dev, 981 "timeout while waiting for PM stable Trace Status\n"); 982 /* 983 * As recommended in section 4.3.7 (Synchronization of register updates) 984 * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an 985 * ISB instruction after programming the trace unit registers. 986 * 987 * For the memory-mapped interface, the registers are mapped as Device 988 * type (Device-nGnRE). Reading back the value of any register in the 989 * trace unit ensures that all writes have completed. Therefore, polling 990 * on TRCSTATR guarantees that the writing TRCPRGCTLR is complete, and 991 * no explicit dsb() is required at here. 992 */ 993 isb(); 994} 995 996static void etm4_disable_hw(struct etmv4_drvdata *drvdata) 997{ 998 u32 control; 999 struct etmv4_config *config = &drvdata->config; 1000 struct coresight_device *csdev = drvdata->csdev; 1001 struct csdev_access *csa = &csdev->access; 1002 int i; 1003 1004 etm4_cs_unlock(drvdata, csa); 1005 etm4_disable_arch_specific(drvdata); 1006 1007 if (!drvdata->skip_power_up) { 1008 /* power can be removed from the trace unit now */ 1009 control = etm4x_relaxed_read32(csa, TRCPDCR); 1010 control &= ~TRCPDCR_PU; 1011 etm4x_relaxed_write32(csa, control, TRCPDCR); 1012 } 1013 1014 etm4_disable_trace_unit(drvdata); 1015 1016 /* read the status of the single shot comparators */ 1017 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1018 config->ss_status[i] = 1019 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 1020 } 1021 1022 /* read back the current counter values */ 1023 for (i = 0; i < drvdata->nr_cntr; i++) { 1024 config->cntr_val[i] = 1025 etm4x_relaxed_read32(csa, TRCCNTVRn(i)); 1026 } 1027 1028 coresight_disclaim_device_unlocked(csdev); 1029 etm4_cs_lock(drvdata, csa); 1030 1031 dev_dbg(&drvdata->csdev->dev, 1032 "cpu: %d disable smp call done\n", drvdata->cpu); 1033} 1034 1035static void etm4_disable_sysfs_smp_call(void *info) 1036{ 1037 struct etmv4_drvdata *drvdata = info; 1038 1039 etm4_disable_hw(drvdata); 1040 1041 coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); 1042} 1043 1044static int etm4_disable_perf(struct coresight_device *csdev, 1045 struct perf_event *event) 1046{ 1047 u32 control; 1048 struct etm_filters *filters = event->hw.addr_filters; 1049 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 1050 struct perf_event_attr *attr = &event->attr; 1051 1052 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 1053 return -EINVAL; 1054 1055 etm4_disable_hw(drvdata); 1056 /* 1057 * The config_id occupies bits 63:32 of the config2 perf event attr 1058 * field. If this is non-zero then we will have enabled a config. 1059 */ 1060 if (attr->config2 & GENMASK_ULL(63, 32)) 1061 cscfg_csdev_disable_active_config(csdev); 1062 1063 /* 1064 * Check if the start/stop logic was active when the unit was stopped. 1065 * That way we can re-enable the start/stop logic when the process is 1066 * scheduled again. Configuration of the start/stop logic happens in 1067 * function etm4_set_event_filters(). 1068 */ 1069 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); 1070 /* TRCVICTLR::SSSTATUS, bit[9] */ 1071 filters->ssstatus = (control & BIT(9)); 1072 1073 coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); 1074 1075 /* 1076 * perf will release trace ids when _free_aux() is 1077 * called at the end of the session. 1078 */ 1079 1080 return 0; 1081} 1082 1083static void etm4_disable_sysfs(struct coresight_device *csdev) 1084{ 1085 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 1086 1087 /* 1088 * Taking hotplug lock here protects from clocks getting disabled 1089 * with tracing being left on (crash scenario) if user disable occurs 1090 * after cpu online mask indicates the cpu is offline but before the 1091 * DYING hotplug callback is serviced by the ETM driver. 1092 */ 1093 cpus_read_lock(); 1094 raw_spin_lock(&drvdata->spinlock); 1095 1096 /* 1097 * Executing etm4_disable_hw on the cpu whose ETM is being disabled 1098 * ensures that register writes occur when cpu is powered. 1099 */ 1100 smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, 1101 drvdata, 1); 1102 1103 raw_spin_unlock(&drvdata->spinlock); 1104 1105 cscfg_csdev_disable_active_config(csdev); 1106 1107 cpus_read_unlock(); 1108 1109 /* 1110 * we only release trace IDs when resetting sysfs. 1111 * This permits sysfs users to read the trace ID after the trace 1112 * session has completed. This maintains operational behaviour with 1113 * prior trace id allocation method 1114 */ 1115 1116 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); 1117} 1118 1119static void etm4_disable(struct coresight_device *csdev, 1120 struct perf_event *event) 1121{ 1122 enum cs_mode mode; 1123 1124 /* 1125 * For as long as the tracer isn't disabled another entity can't 1126 * change its status. As such we can read the status here without 1127 * fearing it will change under us. 1128 */ 1129 mode = coresight_get_mode(csdev); 1130 1131 switch (mode) { 1132 case CS_MODE_DISABLED: 1133 break; 1134 case CS_MODE_SYSFS: 1135 etm4_disable_sysfs(csdev); 1136 break; 1137 case CS_MODE_PERF: 1138 etm4_disable_perf(csdev, event); 1139 break; 1140 } 1141} 1142 1143static int etm4_resume_perf(struct coresight_device *csdev) 1144{ 1145 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 1146 struct csdev_access *csa = &csdev->access; 1147 1148 if (coresight_get_mode(csdev) != CS_MODE_PERF) 1149 return -EINVAL; 1150 1151 etm4_cs_unlock(drvdata, csa); 1152 etm4_enable_trace_unit(drvdata); 1153 etm4_cs_lock(drvdata, csa); 1154 1155 drvdata->paused = false; 1156 return 0; 1157} 1158 1159static void etm4_pause_perf(struct coresight_device *csdev) 1160{ 1161 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 1162 struct csdev_access *csa = &csdev->access; 1163 1164 if (coresight_get_mode(csdev) != CS_MODE_PERF) 1165 return; 1166 1167 etm4_cs_unlock(drvdata, csa); 1168 etm4_disable_trace_unit(drvdata); 1169 etm4_cs_lock(drvdata, csa); 1170 1171 drvdata->paused = true; 1172} 1173 1174static const struct coresight_ops_source etm4_source_ops = { 1175 .cpu_id = etm4_cpu_id, 1176 .enable = etm4_enable, 1177 .disable = etm4_disable, 1178 .resume_perf = etm4_resume_perf, 1179 .pause_perf = etm4_pause_perf, 1180}; 1181 1182static const struct coresight_ops etm4_cs_ops = { 1183 .trace_id = coresight_etm_get_trace_id, 1184 .source_ops = &etm4_source_ops, 1185}; 1186 1187static bool cpu_supports_sysreg_trace(void) 1188{ 1189 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); 1190 1191 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0; 1192} 1193 1194static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, 1195 struct csdev_access *csa) 1196{ 1197 u32 devarch; 1198 1199 if (!cpu_supports_sysreg_trace()) 1200 return false; 1201 1202 /* 1203 * ETMs implementing sysreg access must implement TRCDEVARCH. 1204 */ 1205 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); 1206 switch (devarch & ETM_DEVARCH_ID_MASK) { 1207 case ETM_DEVARCH_ETMv4x_ARCH: 1208 *csa = (struct csdev_access) { 1209 .io_mem = false, 1210 .read = etm4x_sysreg_read, 1211 .write = etm4x_sysreg_write, 1212 }; 1213 break; 1214 case ETM_DEVARCH_ETE_ARCH: 1215 *csa = (struct csdev_access) { 1216 .io_mem = false, 1217 .read = ete_sysreg_read, 1218 .write = ete_sysreg_write, 1219 }; 1220 break; 1221 default: 1222 return false; 1223 } 1224 1225 drvdata->arch = etm_devarch_to_arch(devarch); 1226 return true; 1227} 1228 1229static bool is_devtype_cpu_trace(void __iomem *base) 1230{ 1231 u32 devtype = readl(base + TRCDEVTYPE); 1232 1233 return (devtype == CS_DEVTYPE_PE_TRACE); 1234} 1235 1236static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 1237 struct csdev_access *csa) 1238{ 1239 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); 1240 1241 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base)) 1242 return false; 1243 1244 /* 1245 * All ETMs must implement TRCDEVARCH to indicate that 1246 * the component is an ETMv4. Even though TRCIDR1 also 1247 * contains the information, it is part of the "Trace" 1248 * register and must be accessed with the OSLK cleared, 1249 * with MMIO. But we cannot touch the OSLK until we are 1250 * sure this is an ETM. So rely only on the TRCDEVARCH. 1251 */ 1252 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) { 1253 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); 1254 return false; 1255 } 1256 1257 drvdata->arch = etm_devarch_to_arch(devarch); 1258 *csa = CSDEV_ACCESS_IOMEM(drvdata->base); 1259 return true; 1260} 1261 1262static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, 1263 struct csdev_access *csa) 1264{ 1265 /* 1266 * Always choose the memory mapped io, if there is 1267 * a memory map to prevent sysreg access on broken 1268 * systems. 1269 */ 1270 if (drvdata->base) 1271 return etm4_init_iomem_access(drvdata, csa); 1272 1273 if (etm4_init_sysreg_access(drvdata, csa)) 1274 return true; 1275 1276 return false; 1277} 1278 1279static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) 1280{ 1281 u64 dfr0 = read_sysreg(id_aa64dfr0_el1); 1282 u64 trfcr; 1283 1284 drvdata->trfcr = 0; 1285 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) 1286 return; 1287 1288 /* 1289 * If the CPU supports v8.4 SelfHosted Tracing, enable 1290 * tracing at the kernel EL and EL0, forcing to use the 1291 * virtual time as the timestamp. 1292 */ 1293 trfcr = (FIELD_PREP(TRFCR_EL1_TS_MASK, TRFCR_EL1_TS_VIRTUAL) | 1294 TRFCR_EL1_ExTRE | 1295 TRFCR_EL1_E0TRE); 1296 1297 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ 1298 if (is_kernel_in_hyp_mode()) 1299 trfcr |= TRFCR_EL2_CX; 1300 1301 drvdata->trfcr = trfcr; 1302} 1303 1304/* 1305 * The following errata on applicable cpu ranges, affect the CCITMIN filed 1306 * in TCRIDR3 register. Software read for the field returns 0x100 limiting 1307 * the cycle threshold granularity, whereas the right value should have 1308 * been 0x4, which is well supported in the hardware. 1309 */ 1310static struct midr_range etm_wrong_ccitmin_cpus[] = { 1311 /* Erratum #1490853 - Cortex-A76 */ 1312 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), 1313 /* Erratum #1490853 - Neoverse-N1 */ 1314 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), 1315 /* Erratum #1491015 - Cortex-A77 */ 1316 MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), 1317 /* Erratum #1502854 - Cortex-X1 */ 1318 MIDR_REV(MIDR_CORTEX_X1, 0, 0), 1319 /* Erratum #1619801 - Neoverse-V1 */ 1320 MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), 1321 {}, 1322}; 1323 1324static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) 1325{ 1326 /* 1327 * Erratum affected cpus will read 256 as the minimum 1328 * instruction trace cycle counting threshold whereas 1329 * the correct value should be 4 instead. Override the 1330 * recorded value for 'drvdata->ccitmin' to workaround 1331 * this problem. 1332 */ 1333 if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) { 1334 if (drvdata->ccitmin == 256) 1335 drvdata->ccitmin = 4; 1336 } 1337} 1338 1339static void etm4_init_arch_data(void *info) 1340{ 1341 u32 etmidr0; 1342 u32 etmidr2; 1343 u32 etmidr3; 1344 u32 etmidr4; 1345 u32 etmidr5; 1346 struct etm4_init_arg *init_arg = info; 1347 struct etmv4_drvdata *drvdata; 1348 struct csdev_access *csa; 1349 struct device *dev = init_arg->dev; 1350 int i; 1351 1352 drvdata = dev_get_drvdata(init_arg->dev); 1353 csa = init_arg->csa; 1354 1355 /* 1356 * If we are unable to detect the access mechanism, 1357 * or unable to detect the trace unit type, fail 1358 * early. 1359 */ 1360 if (!etm4_init_csdev_access(drvdata, csa)) 1361 return; 1362 1363 if (!csa->io_mem || 1364 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) 1365 drvdata->skip_power_up = true; 1366 1367 /* Detect the support for OS Lock before we actually use it */ 1368 etm_detect_os_lock(drvdata, csa); 1369 1370 /* Make sure all registers are accessible */ 1371 etm4_os_unlock_csa(drvdata, csa); 1372 etm4_cs_unlock(drvdata, csa); 1373 1374 etm4_check_arch_features(drvdata, csa); 1375 1376 /* find all capabilities of the tracing unit */ 1377 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); 1378 1379 /* INSTP0, bits[2:1] P0 tracing support field */ 1380 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); 1381 /* TRCBB, bit[5] Branch broadcast tracing support bit */ 1382 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); 1383 /* TRCCOND, bit[6] Conditional instruction tracing support bit */ 1384 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); 1385 /* TRCCCI, bit[7] Cycle counting instruction bit */ 1386 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); 1387 /* RETSTACK, bit[9] Return stack bit */ 1388 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); 1389 /* NUMEVENT, bits[11:10] Number of events field */ 1390 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); 1391 /* QSUPP, bits[16:15] Q element support field */ 1392 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); 1393 if (drvdata->q_support) 1394 drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT); 1395 /* TSSIZE, bits[28:24] Global timestamp size field */ 1396 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); 1397 1398 /* maximum size of resources */ 1399 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); 1400 /* CIDSIZE, bits[9:5] Indicates the Context ID size */ 1401 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); 1402 /* VMIDSIZE, bits[14:10] Indicates the VMID size */ 1403 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); 1404 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ 1405 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); 1406 1407 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); 1408 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ 1409 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); 1410 etm4_fixup_wrong_ccitmin(drvdata); 1411 1412 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ 1413 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); 1414 drvdata->config.s_ex_level = drvdata->s_ex_level; 1415 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ 1416 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); 1417 /* 1418 * TRCERR, bit[24] whether a trace unit can trace a 1419 * system error exception. 1420 */ 1421 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); 1422 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ 1423 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); 1424 /* STALLCTL, bit[26] is stall control implemented? */ 1425 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); 1426 /* SYSSTALL, bit[27] implementation can support stall control? */ 1427 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); 1428 /* 1429 * NUMPROC - the number of PEs available for tracing, 5bits 1430 * = TRCIDR3.bits[13:12]bits[30:28] 1431 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) 1432 * bits[3:0] = TRCIDR3.bits[30:28] 1433 */ 1434 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | 1435 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); 1436 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ 1437 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW); 1438 1439 /* number of resources trace unit supports */ 1440 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); 1441 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ 1442 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); 1443 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ 1444 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); 1445 /* 1446 * NUMRSPAIR, bits[19:16] 1447 * The number of resource pairs conveyed by the HW starts at 0, i.e a 1448 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. 1449 * As such add 1 to the value of NUMRSPAIR for a better representation. 1450 * 1451 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available - 1452 * the default TRUE and FALSE resource selectors are omitted. 1453 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. 1454 */ 1455 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); 1456 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) 1457 drvdata->nr_resource += 1; 1458 /* 1459 * NUMSSCC, bits[23:20] the number of single-shot 1460 * comparator control for tracing. Read any status regs as these 1461 * also contain RO capability data. 1462 */ 1463 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); 1464 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1465 drvdata->config.ss_status[i] = 1466 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 1467 } 1468 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ 1469 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); 1470 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ 1471 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); 1472 1473 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); 1474 /* NUMEXTIN, bits[8:0] number of external inputs implemented */ 1475 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); 1476 drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); 1477 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ 1478 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); 1479 /* ATBTRIG, bit[22] implementation can support ATB triggers? */ 1480 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); 1481 /* 1482 * LPOVERRIDE, bit[23] implementation supports 1483 * low-power state override 1484 */ 1485 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); 1486 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ 1487 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); 1488 /* NUMCNTR, bits[30:28] number of counters available for tracing */ 1489 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); 1490 1491 coresight_clear_self_claim_tag_unlocked(csa); 1492 etm4_cs_lock(drvdata, csa); 1493 cpu_detect_trace_filtering(drvdata); 1494} 1495 1496static u32 etm4_get_victlr_access_type(struct etmv4_config *config) 1497{ 1498 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); 1499} 1500 1501/* Set ELx trace filter access in the TRCVICTLR register */ 1502static void etm4_set_victlr_access(struct etmv4_config *config) 1503{ 1504 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; 1505 config->vinst_ctrl |= etm4_get_victlr_access_type(config); 1506} 1507 1508static void etm4_set_default_config(struct etmv4_config *config) 1509{ 1510 /* disable all events tracing */ 1511 config->eventctrl0 = 0x0; 1512 config->eventctrl1 = 0x0; 1513 1514 /* disable stalling */ 1515 config->stall_ctrl = 0x0; 1516 1517 /* enable trace synchronization every 4096 bytes, if available */ 1518 config->syncfreq = 0xC; 1519 1520 /* disable timestamp event */ 1521 config->ts_ctrl = 0x0; 1522 1523 /* TRCVICTLR::EVENT = 0x01, select the always on logic */ 1524 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); 1525 1526 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ 1527 etm4_set_victlr_access(config); 1528} 1529 1530static u64 etm4_get_ns_access_type(struct etmv4_config *config) 1531{ 1532 u64 access_type = 0; 1533 1534 /* 1535 * EXLEVEL_NS, for NonSecure Exception levels. 1536 * The mask here is a generic value and must be 1537 * shifted to the corresponding field for the registers 1538 */ 1539 if (!is_kernel_in_hyp_mode()) { 1540 /* Stay away from hypervisor mode for non-VHE */ 1541 access_type = ETM_EXLEVEL_NS_HYP; 1542 if (config->mode & ETM_MODE_EXCL_KERN) 1543 access_type |= ETM_EXLEVEL_NS_OS; 1544 } else if (config->mode & ETM_MODE_EXCL_KERN) { 1545 access_type = ETM_EXLEVEL_NS_HYP; 1546 } 1547 1548 if (config->mode & ETM_MODE_EXCL_USER) 1549 access_type |= ETM_EXLEVEL_NS_APP; 1550 1551 return access_type; 1552} 1553 1554/* 1555 * Construct the exception level masks for a given config. 1556 * This must be shifted to the corresponding register field 1557 * for usage. 1558 */ 1559static u64 etm4_get_access_type(struct etmv4_config *config) 1560{ 1561 /* All Secure exception levels are excluded from the trace */ 1562 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; 1563} 1564 1565static u64 etm4_get_comparator_access_type(struct etmv4_config *config) 1566{ 1567 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; 1568} 1569 1570static void etm4_set_comparator_filter(struct etmv4_config *config, 1571 u64 start, u64 stop, int comparator) 1572{ 1573 u64 access_type = etm4_get_comparator_access_type(config); 1574 1575 /* First half of default address comparator */ 1576 config->addr_val[comparator] = start; 1577 config->addr_acc[comparator] = access_type; 1578 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE; 1579 1580 /* Second half of default address comparator */ 1581 config->addr_val[comparator + 1] = stop; 1582 config->addr_acc[comparator + 1] = access_type; 1583 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE; 1584 1585 /* 1586 * Configure the ViewInst function to include this address range 1587 * comparator. 1588 * 1589 * @comparator is divided by two since it is the index in the 1590 * etmv4_config::addr_val array but register TRCVIIECTLR deals with 1591 * address range comparator _pairs_. 1592 * 1593 * Therefore: 1594 * index 0 -> compatator pair 0 1595 * index 2 -> comparator pair 1 1596 * index 4 -> comparator pair 2 1597 * ... 1598 * index 14 -> comparator pair 7 1599 */ 1600 config->viiectlr |= BIT(comparator / 2); 1601} 1602 1603static void etm4_set_start_stop_filter(struct etmv4_config *config, 1604 u64 address, int comparator, 1605 enum etm_addr_type type) 1606{ 1607 int shift; 1608 u64 access_type = etm4_get_comparator_access_type(config); 1609 1610 /* Configure the comparator */ 1611 config->addr_val[comparator] = address; 1612 config->addr_acc[comparator] = access_type; 1613 config->addr_type[comparator] = type; 1614 1615 /* 1616 * Configure ViewInst Start-Stop control register. 1617 * Addresses configured to start tracing go from bit 0 to n-1, 1618 * while those configured to stop tracing from 16 to 16 + n-1. 1619 */ 1620 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16); 1621 config->vissctlr |= BIT(shift + comparator); 1622} 1623 1624static void etm4_set_default_filter(struct etmv4_config *config) 1625{ 1626 /* Trace everything 'default' filter achieved by no filtering */ 1627 config->viiectlr = 0x0; 1628 1629 /* 1630 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1631 * in the started state 1632 */ 1633 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1634 config->mode |= ETM_MODE_VIEWINST_STARTSTOP; 1635 1636 /* No start-stop filtering for ViewInst */ 1637 config->vissctlr = 0x0; 1638} 1639 1640static void etm4_set_default(struct etmv4_config *config) 1641{ 1642 if (WARN_ON_ONCE(!config)) 1643 return; 1644 1645 /* 1646 * Make default initialisation trace everything 1647 * 1648 * This is done by a minimum default config sufficient to enable 1649 * full instruction trace - with a default filter for trace all 1650 * achieved by having no filtering. 1651 */ 1652 etm4_set_default_config(config); 1653 etm4_set_default_filter(config); 1654} 1655 1656static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) 1657{ 1658 int nr_comparator, index = 0; 1659 struct etmv4_config *config = &drvdata->config; 1660 1661 /* 1662 * nr_addr_cmp holds the number of comparator _pair_, so time 2 1663 * for the total number of comparators. 1664 */ 1665 nr_comparator = drvdata->nr_addr_cmp * 2; 1666 1667 /* Go through the tally of comparators looking for a free one. */ 1668 while (index < nr_comparator) { 1669 switch (type) { 1670 case ETM_ADDR_TYPE_RANGE: 1671 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE && 1672 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE) 1673 return index; 1674 1675 /* Address range comparators go in pairs */ 1676 index += 2; 1677 break; 1678 case ETM_ADDR_TYPE_START: 1679 case ETM_ADDR_TYPE_STOP: 1680 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE) 1681 return index; 1682 1683 /* Start/stop address can have odd indexes */ 1684 index += 1; 1685 break; 1686 default: 1687 return -EINVAL; 1688 } 1689 } 1690 1691 /* If we are here all the comparators have been used. */ 1692 return -ENOSPC; 1693} 1694 1695static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 1696 struct perf_event *event) 1697{ 1698 int i, comparator, ret = 0; 1699 u64 address; 1700 struct etmv4_config *config = &drvdata->config; 1701 struct etm_filters *filters = event->hw.addr_filters; 1702 1703 if (!filters) 1704 goto default_filter; 1705 1706 /* Sync events with what Perf got */ 1707 perf_event_addr_filters_sync(event); 1708 1709 /* 1710 * If there are no filters to deal with simply go ahead with 1711 * the default filter, i.e the entire address range. 1712 */ 1713 if (!filters->nr_filters) 1714 goto default_filter; 1715 1716 for (i = 0; i < filters->nr_filters; i++) { 1717 struct etm_filter *filter = &filters->etm_filter[i]; 1718 enum etm_addr_type type = filter->type; 1719 1720 /* See if a comparator is free. */ 1721 comparator = etm4_get_next_comparator(drvdata, type); 1722 if (comparator < 0) { 1723 ret = comparator; 1724 goto out; 1725 } 1726 1727 switch (type) { 1728 case ETM_ADDR_TYPE_RANGE: 1729 etm4_set_comparator_filter(config, 1730 filter->start_addr, 1731 filter->stop_addr, 1732 comparator); 1733 /* 1734 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1735 * in the started state 1736 */ 1737 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1738 1739 /* No start-stop filtering for ViewInst */ 1740 config->vissctlr = 0x0; 1741 break; 1742 case ETM_ADDR_TYPE_START: 1743 case ETM_ADDR_TYPE_STOP: 1744 /* Get the right start or stop address */ 1745 address = (type == ETM_ADDR_TYPE_START ? 1746 filter->start_addr : 1747 filter->stop_addr); 1748 1749 /* Configure comparator */ 1750 etm4_set_start_stop_filter(config, address, 1751 comparator, type); 1752 1753 /* 1754 * If filters::ssstatus == 1, trace acquisition was 1755 * started but the process was yanked away before the 1756 * stop address was hit. As such the start/stop 1757 * logic needs to be re-started so that tracing can 1758 * resume where it left. 1759 * 1760 * The start/stop logic status when a process is 1761 * scheduled out is checked in function 1762 * etm4_disable_perf(). 1763 */ 1764 if (filters->ssstatus) 1765 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1766 1767 /* No include/exclude filtering for ViewInst */ 1768 config->viiectlr = 0x0; 1769 break; 1770 default: 1771 ret = -EINVAL; 1772 goto out; 1773 } 1774 } 1775 1776 goto out; 1777 1778 1779default_filter: 1780 etm4_set_default_filter(config); 1781 1782out: 1783 return ret; 1784} 1785 1786void etm4_config_trace_mode(struct etmv4_config *config) 1787{ 1788 u32 mode; 1789 1790 mode = config->mode; 1791 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); 1792 1793 /* excluding kernel AND user space doesn't make sense */ 1794 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); 1795 1796 /* nothing to do if neither flags are set */ 1797 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) 1798 return; 1799 1800 etm4_set_victlr_access(config); 1801} 1802 1803static int etm4_online_cpu(unsigned int cpu) 1804{ 1805 if (!etmdrvdata[cpu]) 1806 return etm4_probe_cpu(cpu); 1807 1808 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) 1809 coresight_enable_sysfs(etmdrvdata[cpu]->csdev); 1810 return 0; 1811} 1812 1813static int etm4_starting_cpu(unsigned int cpu) 1814{ 1815 if (!etmdrvdata[cpu]) 1816 return 0; 1817 1818 raw_spin_lock(&etmdrvdata[cpu]->spinlock); 1819 if (!etmdrvdata[cpu]->os_unlock) 1820 etm4_os_unlock(etmdrvdata[cpu]); 1821 1822 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) 1823 etm4_enable_hw(etmdrvdata[cpu]); 1824 raw_spin_unlock(&etmdrvdata[cpu]->spinlock); 1825 return 0; 1826} 1827 1828static int etm4_dying_cpu(unsigned int cpu) 1829{ 1830 if (!etmdrvdata[cpu]) 1831 return 0; 1832 1833 raw_spin_lock(&etmdrvdata[cpu]->spinlock); 1834 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) 1835 etm4_disable_hw(etmdrvdata[cpu]); 1836 raw_spin_unlock(&etmdrvdata[cpu]->spinlock); 1837 return 0; 1838} 1839 1840static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 1841{ 1842 int i, ret = 0; 1843 struct etmv4_save_state *state; 1844 struct coresight_device *csdev = drvdata->csdev; 1845 struct csdev_access *csa; 1846 struct device *etm_dev; 1847 1848 if (WARN_ON(!csdev)) 1849 return -ENODEV; 1850 1851 etm_dev = &csdev->dev; 1852 csa = &csdev->access; 1853 1854 /* 1855 * As recommended by 3.4.1 ("The procedure when powering down the PE") 1856 * of ARM IHI 0064D 1857 */ 1858 dsb(sy); 1859 isb(); 1860 1861 etm4_cs_unlock(drvdata, csa); 1862 /* Lock the OS lock to disable trace and external debugger access */ 1863 etm4_os_lock(drvdata); 1864 1865 /* wait for TRCSTATR.PMSTABLE to go up */ 1866 if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) { 1867 dev_err(etm_dev, 1868 "timeout while waiting for PM Stable Status\n"); 1869 etm4_os_unlock(drvdata); 1870 ret = -EBUSY; 1871 goto out; 1872 } 1873 1874 if (!drvdata->paused) 1875 etm4_disable_trace_unit(drvdata); 1876 1877 state = drvdata->save_state; 1878 1879 if (drvdata->nr_pe) 1880 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); 1881 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); 1882 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); 1883 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); 1884 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); 1885 if (drvdata->stallctl) 1886 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); 1887 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); 1888 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); 1889 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); 1890 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); 1891 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); 1892 if (drvdata->q_filt) 1893 state->trcqctlr = etm4x_read32(csa, TRCQCTLR); 1894 1895 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); 1896 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); 1897 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); 1898 if (drvdata->nr_pe_cmp) 1899 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); 1900 1901 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1902 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); 1903 1904 if (drvdata->nrseqstate) { 1905 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); 1906 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); 1907 } 1908 1909 if (drvdata->numextinsel) 1910 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1911 1912 for (i = 0; i < drvdata->nr_cntr; i++) { 1913 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); 1914 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); 1915 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); 1916 } 1917 1918 /* Resource selector pair 0 is reserved */ 1919 for (i = 2; i < drvdata->nr_resource * 2; i++) 1920 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); 1921 1922 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1923 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); 1924 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); 1925 if (etm4x_sspcicrn_present(drvdata, i)) 1926 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); 1927 } 1928 1929 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1930 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); 1931 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); 1932 } 1933 1934 /* 1935 * Data trace stream is architecturally prohibited for A profile cores 1936 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per 1937 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace 1938 * unit") of ARM IHI 0064D. 1939 */ 1940 1941 for (i = 0; i < drvdata->numcidc; i++) 1942 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); 1943 1944 for (i = 0; i < drvdata->numvmidc; i++) 1945 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); 1946 1947 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); 1948 if (drvdata->numcidc > 4) 1949 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); 1950 1951 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); 1952 if (drvdata->numvmidc > 4) 1953 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); 1954 1955 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); 1956 1957 if (!drvdata->skip_power_up) 1958 state->trcpdcr = etm4x_read32(csa, TRCPDCR); 1959 1960 /* wait for TRCSTATR.IDLE to go up */ 1961 if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) { 1962 dev_err(etm_dev, 1963 "timeout while waiting for Idle Trace Status\n"); 1964 etm4_os_unlock(drvdata); 1965 ret = -EBUSY; 1966 goto out; 1967 } 1968 1969 /* 1970 * Power can be removed from the trace unit now. We do this to 1971 * potentially save power on systems that respect the TRCPDCR_PU 1972 * despite requesting software to save/restore state. 1973 */ 1974 if (!drvdata->skip_power_up) 1975 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), 1976 TRCPDCR); 1977out: 1978 etm4_cs_lock(drvdata, csa); 1979 return ret; 1980} 1981 1982static int etm4_cpu_save(struct etmv4_drvdata *drvdata) 1983{ 1984 int ret = 0; 1985 1986 if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED) 1987 return 0; 1988 1989 /* 1990 * Save and restore the ETM Trace registers only if 1991 * the ETM is active. 1992 */ 1993 if (coresight_get_mode(drvdata->csdev)) 1994 ret = __etm4_cpu_save(drvdata); 1995 return ret; 1996} 1997 1998static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1999{ 2000 int i; 2001 struct etmv4_save_state *state = drvdata->save_state; 2002 struct csdev_access *csa = &drvdata->csdev->access; 2003 2004 if (WARN_ON(!drvdata->csdev)) 2005 return; 2006 2007 etm4_cs_unlock(drvdata, csa); 2008 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 2009 2010 if (drvdata->nr_pe) 2011 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); 2012 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); 2013 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); 2014 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); 2015 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); 2016 if (drvdata->stallctl) 2017 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); 2018 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); 2019 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); 2020 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); 2021 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); 2022 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); 2023 if (drvdata->q_filt) 2024 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); 2025 2026 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); 2027 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); 2028 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); 2029 if (drvdata->nr_pe_cmp) 2030 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); 2031 2032 for (i = 0; i < drvdata->nrseqstate - 1; i++) 2033 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); 2034 2035 if (drvdata->nrseqstate) { 2036 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); 2037 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); 2038 } 2039 if (drvdata->numextinsel) 2040 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 2041 2042 for (i = 0; i < drvdata->nr_cntr; i++) { 2043 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); 2044 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); 2045 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); 2046 } 2047 2048 /* Resource selector pair 0 is reserved */ 2049 for (i = 2; i < drvdata->nr_resource * 2; i++) 2050 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); 2051 2052 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 2053 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); 2054 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); 2055 if (etm4x_sspcicrn_present(drvdata, i)) 2056 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); 2057 } 2058 2059 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 2060 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); 2061 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); 2062 } 2063 2064 for (i = 0; i < drvdata->numcidc; i++) 2065 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); 2066 2067 for (i = 0; i < drvdata->numvmidc; i++) 2068 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); 2069 2070 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); 2071 if (drvdata->numcidc > 4) 2072 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); 2073 2074 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); 2075 if (drvdata->numvmidc > 4) 2076 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); 2077 2078 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 2079 2080 if (!drvdata->skip_power_up) 2081 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); 2082 2083 /* 2084 * As recommended by section 4.3.7 ("Synchronization when using the 2085 * memory-mapped interface") of ARM IHI 0064D 2086 */ 2087 dsb(sy); 2088 isb(); 2089 2090 /* Unlock the OS lock to re-enable trace and external debug access */ 2091 etm4_os_unlock(drvdata); 2092 2093 if (!drvdata->paused) 2094 etm4_enable_trace_unit(drvdata); 2095 2096 etm4_cs_lock(drvdata, csa); 2097} 2098 2099static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) 2100{ 2101 if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED) 2102 return; 2103 2104 if (coresight_get_mode(drvdata->csdev)) 2105 __etm4_cpu_restore(drvdata); 2106} 2107 2108static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, 2109 void *v) 2110{ 2111 struct etmv4_drvdata *drvdata; 2112 unsigned int cpu = smp_processor_id(); 2113 2114 if (!etmdrvdata[cpu]) 2115 return NOTIFY_OK; 2116 2117 drvdata = etmdrvdata[cpu]; 2118 2119 if (WARN_ON_ONCE(drvdata->cpu != cpu)) 2120 return NOTIFY_BAD; 2121 2122 switch (cmd) { 2123 case CPU_PM_ENTER: 2124 if (etm4_cpu_save(drvdata)) 2125 return NOTIFY_BAD; 2126 break; 2127 case CPU_PM_EXIT: 2128 case CPU_PM_ENTER_FAILED: 2129 etm4_cpu_restore(drvdata); 2130 break; 2131 default: 2132 return NOTIFY_DONE; 2133 } 2134 2135 return NOTIFY_OK; 2136} 2137 2138static struct notifier_block etm4_cpu_pm_nb = { 2139 .notifier_call = etm4_cpu_pm_notify, 2140}; 2141 2142/* Setup PM. Deals with error conditions and counts */ 2143static int __init etm4_pm_setup(void) 2144{ 2145 int ret; 2146 2147 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); 2148 if (ret) 2149 return ret; 2150 2151 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, 2152 "arm/coresight4:starting", 2153 etm4_starting_cpu, etm4_dying_cpu); 2154 2155 if (ret) 2156 goto unregister_notifier; 2157 2158 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, 2159 "arm/coresight4:online", 2160 etm4_online_cpu, NULL); 2161 2162 /* HP dyn state ID returned in ret on success */ 2163 if (ret > 0) { 2164 hp_online = ret; 2165 return 0; 2166 } 2167 2168 /* failed dyn state - remove others */ 2169 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 2170 2171unregister_notifier: 2172 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 2173 return ret; 2174} 2175 2176static void etm4_pm_clear(void) 2177{ 2178 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 2179 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 2180 if (hp_online) { 2181 cpuhp_remove_state_nocalls(hp_online); 2182 hp_online = 0; 2183 } 2184} 2185 2186static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) 2187{ 2188 int ret; 2189 struct coresight_platform_data *pdata = NULL; 2190 struct device *dev = init_arg->dev; 2191 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2192 struct coresight_desc desc = { 0 }; 2193 u8 major, minor; 2194 char *type_name; 2195 2196 if (!drvdata) 2197 return -EINVAL; 2198 2199 desc.access = *init_arg->csa; 2200 2201 if (!drvdata->arch) 2202 return -EINVAL; 2203 2204 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); 2205 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch); 2206 2207 if (etm4x_is_ete(drvdata)) { 2208 type_name = "ete"; 2209 /* ETE v1 has major version == 0b101. Adjust this for logging.*/ 2210 major -= 4; 2211 } else { 2212 type_name = "etm"; 2213 } 2214 2215 desc.name = devm_kasprintf(dev, GFP_KERNEL, 2216 "%s%d", type_name, drvdata->cpu); 2217 if (!desc.name) 2218 return -ENOMEM; 2219 2220 etm4_set_default(&drvdata->config); 2221 2222 pdata = coresight_get_platform_data(dev); 2223 if (IS_ERR(pdata)) 2224 return PTR_ERR(pdata); 2225 2226 dev->platform_data = pdata; 2227 2228 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 2229 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; 2230 desc.ops = &etm4_cs_ops; 2231 desc.pdata = pdata; 2232 desc.dev = dev; 2233 desc.groups = coresight_etmv4_groups; 2234 drvdata->csdev = coresight_register(&desc); 2235 if (IS_ERR(drvdata->csdev)) 2236 return PTR_ERR(drvdata->csdev); 2237 2238 ret = etm_perf_symlink(drvdata->csdev, true); 2239 if (ret) { 2240 coresight_unregister(drvdata->csdev); 2241 return ret; 2242 } 2243 2244 /* register with config infrastructure & load any current features */ 2245 ret = etm4_cscfg_register(drvdata->csdev); 2246 if (ret) { 2247 coresight_unregister(drvdata->csdev); 2248 return ret; 2249 } 2250 2251 etmdrvdata[drvdata->cpu] = drvdata; 2252 2253 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n", 2254 drvdata->cpu, type_name, major, minor); 2255 2256 if (boot_enable) { 2257 coresight_enable_sysfs(drvdata->csdev); 2258 drvdata->boot_enable = true; 2259 } 2260 2261 return 0; 2262} 2263 2264static int etm4_probe(struct device *dev) 2265{ 2266 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2267 struct csdev_access access = { 0 }; 2268 struct etm4_init_arg init_arg = { 0 }; 2269 struct etm4_init_arg *delayed; 2270 int ret; 2271 2272 if (WARN_ON(!drvdata)) 2273 return -ENOMEM; 2274 2275 ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); 2276 if (ret) 2277 return ret; 2278 2279 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) 2280 pm_save_enable = coresight_loses_context_with_cpu(dev) ? 2281 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; 2282 2283 if (pm_save_enable != PARAM_PM_SAVE_NEVER) { 2284 drvdata->save_state = devm_kmalloc(dev, 2285 sizeof(struct etmv4_save_state), GFP_KERNEL); 2286 if (!drvdata->save_state) 2287 return -ENOMEM; 2288 } 2289 2290 raw_spin_lock_init(&drvdata->spinlock); 2291 2292 drvdata->cpu = coresight_get_cpu(dev); 2293 if (drvdata->cpu < 0) 2294 return drvdata->cpu; 2295 2296 init_arg.dev = dev; 2297 init_arg.csa = &access; 2298 2299 /* 2300 * Serialize against CPUHP callbacks to avoid race condition 2301 * between the smp call and saving the delayed probe. 2302 */ 2303 cpus_read_lock(); 2304 if (smp_call_function_single(drvdata->cpu, 2305 etm4_init_arch_data, &init_arg, 1)) { 2306 /* The CPU was offline, try again once it comes online. */ 2307 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); 2308 if (!delayed) { 2309 cpus_read_unlock(); 2310 return -ENOMEM; 2311 } 2312 2313 *delayed = init_arg; 2314 2315 per_cpu(delayed_probe, drvdata->cpu) = delayed; 2316 2317 cpus_read_unlock(); 2318 return 0; 2319 } 2320 cpus_read_unlock(); 2321 2322 return etm4_add_coresight_dev(&init_arg); 2323} 2324 2325static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) 2326{ 2327 struct etmv4_drvdata *drvdata; 2328 void __iomem *base; 2329 struct device *dev = &adev->dev; 2330 struct resource *res = &adev->res; 2331 int ret; 2332 2333 /* Validity for the resource is already checked by the AMBA core */ 2334 base = devm_ioremap_resource(dev, res); 2335 if (IS_ERR(base)) 2336 return PTR_ERR(base); 2337 2338 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 2339 if (!drvdata) 2340 return -ENOMEM; 2341 2342 drvdata->base = base; 2343 dev_set_drvdata(dev, drvdata); 2344 ret = etm4_probe(dev); 2345 if (!ret) 2346 pm_runtime_put(&adev->dev); 2347 2348 return ret; 2349} 2350 2351static int etm4_probe_platform_dev(struct platform_device *pdev) 2352{ 2353 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2354 struct etmv4_drvdata *drvdata; 2355 int ret; 2356 2357 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); 2358 if (!drvdata) 2359 return -ENOMEM; 2360 2361 if (res) { 2362 drvdata->base = devm_ioremap_resource(&pdev->dev, res); 2363 if (IS_ERR(drvdata->base)) 2364 return PTR_ERR(drvdata->base); 2365 } 2366 2367 dev_set_drvdata(&pdev->dev, drvdata); 2368 pm_runtime_get_noresume(&pdev->dev); 2369 pm_runtime_set_active(&pdev->dev); 2370 pm_runtime_enable(&pdev->dev); 2371 2372 ret = etm4_probe(&pdev->dev); 2373 2374 pm_runtime_put(&pdev->dev); 2375 if (ret) 2376 pm_runtime_disable(&pdev->dev); 2377 2378 return ret; 2379} 2380 2381static int etm4_probe_cpu(unsigned int cpu) 2382{ 2383 int ret; 2384 struct etm4_init_arg init_arg; 2385 struct csdev_access access = { 0 }; 2386 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); 2387 2388 if (!iap) 2389 return 0; 2390 2391 init_arg = *iap; 2392 devm_kfree(init_arg.dev, iap); 2393 *this_cpu_ptr(&delayed_probe) = NULL; 2394 2395 ret = pm_runtime_resume_and_get(init_arg.dev); 2396 if (ret < 0) { 2397 dev_err(init_arg.dev, "Failed to get PM runtime!\n"); 2398 return 0; 2399 } 2400 2401 init_arg.csa = &access; 2402 etm4_init_arch_data(&init_arg); 2403 2404 etm4_add_coresight_dev(&init_arg); 2405 2406 pm_runtime_put(init_arg.dev); 2407 return 0; 2408} 2409 2410static struct amba_cs_uci_id uci_id_etm4[] = { 2411 { 2412 /* ETMv4 UCI data */ 2413 .devarch = ETM_DEVARCH_ETMv4x_ARCH, 2414 .devarch_mask = ETM_DEVARCH_ID_MASK, 2415 .devtype = CS_DEVTYPE_PE_TRACE, 2416 } 2417}; 2418 2419static void clear_etmdrvdata(void *info) 2420{ 2421 int cpu = *(int *)info; 2422 2423 etmdrvdata[cpu] = NULL; 2424 per_cpu(delayed_probe, cpu) = NULL; 2425} 2426 2427static void etm4_remove_dev(struct etmv4_drvdata *drvdata) 2428{ 2429 bool had_delayed_probe; 2430 /* 2431 * Taking hotplug lock here to avoid racing between etm4_remove_dev() 2432 * and CPU hotplug call backs. 2433 */ 2434 cpus_read_lock(); 2435 2436 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu); 2437 2438 /* 2439 * The readers for etmdrvdata[] are CPU hotplug call backs 2440 * and PM notification call backs. Change etmdrvdata[i] on 2441 * CPU i ensures these call backs has consistent view 2442 * inside one call back function. 2443 */ 2444 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) 2445 clear_etmdrvdata(&drvdata->cpu); 2446 2447 cpus_read_unlock(); 2448 2449 if (!had_delayed_probe) { 2450 etm_perf_symlink(drvdata->csdev, false); 2451 cscfg_unregister_csdev(drvdata->csdev); 2452 coresight_unregister(drvdata->csdev); 2453 } 2454} 2455 2456static void etm4_remove_amba(struct amba_device *adev) 2457{ 2458 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); 2459 2460 if (drvdata) 2461 etm4_remove_dev(drvdata); 2462} 2463 2464static void etm4_remove_platform_dev(struct platform_device *pdev) 2465{ 2466 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 2467 2468 if (drvdata) 2469 etm4_remove_dev(drvdata); 2470 pm_runtime_disable(&pdev->dev); 2471} 2472 2473static const struct amba_id etm4_ids[] = { 2474 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 2475 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 2476 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 2477 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ 2478 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ 2479 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ 2480 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ 2481 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ 2482 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */ 2483 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ 2484 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ 2485 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ 2486 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ 2487 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ 2488 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ 2489 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ 2490 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ 2491 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ 2492 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ 2493 /* 2494 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new 2495 * CPUs to the list here. 2496 */ 2497 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), 2498 {}, 2499}; 2500 2501MODULE_DEVICE_TABLE(amba, etm4_ids); 2502 2503static struct amba_driver etm4x_amba_driver = { 2504 .drv = { 2505 .name = "coresight-etm4x", 2506 .suppress_bind_attrs = true, 2507 }, 2508 .probe = etm4_probe_amba, 2509 .remove = etm4_remove_amba, 2510 .id_table = etm4_ids, 2511}; 2512 2513#ifdef CONFIG_PM 2514static int etm4_runtime_suspend(struct device *dev) 2515{ 2516 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2517 2518 clk_disable_unprepare(drvdata->atclk); 2519 clk_disable_unprepare(drvdata->pclk); 2520 2521 return 0; 2522} 2523 2524static int etm4_runtime_resume(struct device *dev) 2525{ 2526 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2527 int ret; 2528 2529 ret = clk_prepare_enable(drvdata->pclk); 2530 if (ret) 2531 return ret; 2532 2533 ret = clk_prepare_enable(drvdata->atclk); 2534 if (ret) 2535 clk_disable_unprepare(drvdata->pclk); 2536 2537 return ret; 2538} 2539#endif 2540 2541static const struct dev_pm_ops etm4_dev_pm_ops = { 2542 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL) 2543}; 2544 2545static const struct of_device_id etm4_sysreg_match[] = { 2546 { .compatible = "arm,coresight-etm4x-sysreg" }, 2547 { .compatible = "arm,embedded-trace-extension" }, 2548 {} 2549}; 2550 2551#ifdef CONFIG_ACPI 2552static const struct acpi_device_id etm4x_acpi_ids[] = { 2553 {"ARMHC500", 0, 0, 0}, /* ARM CoreSight ETM4x */ 2554 {} 2555}; 2556MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids); 2557#endif 2558 2559static struct platform_driver etm4_platform_driver = { 2560 .probe = etm4_probe_platform_dev, 2561 .remove = etm4_remove_platform_dev, 2562 .driver = { 2563 .name = "coresight-etm4x", 2564 .of_match_table = etm4_sysreg_match, 2565 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids), 2566 .suppress_bind_attrs = true, 2567 .pm = &etm4_dev_pm_ops, 2568 }, 2569}; 2570 2571static int __init etm4x_init(void) 2572{ 2573 int ret; 2574 2575 ret = etm4_pm_setup(); 2576 2577 /* etm4_pm_setup() does its own cleanup - exit on error */ 2578 if (ret) 2579 return ret; 2580 2581 ret = amba_driver_register(&etm4x_amba_driver); 2582 if (ret) { 2583 pr_err("Error registering etm4x AMBA driver\n"); 2584 goto clear_pm; 2585 } 2586 2587 ret = platform_driver_register(&etm4_platform_driver); 2588 if (!ret) 2589 return 0; 2590 2591 pr_err("Error registering etm4x platform driver\n"); 2592 amba_driver_unregister(&etm4x_amba_driver); 2593 2594clear_pm: 2595 etm4_pm_clear(); 2596 return ret; 2597} 2598 2599static void __exit etm4x_exit(void) 2600{ 2601 amba_driver_unregister(&etm4x_amba_driver); 2602 platform_driver_unregister(&etm4_platform_driver); 2603 etm4_pm_clear(); 2604} 2605 2606module_init(etm4x_init); 2607module_exit(etm4x_exit); 2608 2609MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 2610MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>"); 2611MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver"); 2612MODULE_LICENSE("GPL v2");
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