spd5118.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Driver for Jedec 5118 compliant temperature sensors
  4 *
  5 * Derived from https://github.com/Steve-Tech/SPD5118-DKMS
  6 * Originally from T/2 driver at https://t2sde.org/packages/linux
  7 *	Copyright (c) 2023 René Rebe, ExactCODE GmbH; Germany.
  8 *
  9 * Copyright (c) 2024 Guenter Roeck
 10 *
 11 * Inspired by ee1004.c and jc42.c.
 12 *
 13 * SPD5118 compliant temperature sensors are typically used on DDR5
 14 * memory modules.
 15 */
 16
 17#include <linux/bitops.h>
 18#include <linux/bits.h>
 19#include <linux/err.h>
 20#include <linux/i2c.h>
 21#include <linux/hwmon.h>
 22#include <linux/module.h>
 23#include <linux/mutex.h>
 24#include <linux/nvmem-provider.h>
 25#include <linux/pm.h>
 26#include <linux/regmap.h>
 27#include <linux/units.h>
 28
 29/* Addresses to scan */
 30static const unsigned short normal_i2c[] = {
 31	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, I2C_CLIENT_END };
 32
 33/* SPD5118 registers. */
 34#define SPD5118_REG_TYPE		0x00	/* MR0:MR1 */
 35#define SPD5118_REG_REVISION		0x02	/* MR2 */
 36#define SPD5118_REG_VENDOR		0x03	/* MR3:MR4 */
 37#define SPD5118_REG_CAPABILITY		0x05	/* MR5 */
 38#define SPD5118_REG_I2C_LEGACY_MODE	0x0B	/* MR11 */
 39#define SPD5118_REG_TEMP_CLR		0x13	/* MR19 */
 40#define SPD5118_REG_ERROR_CLR		0x14	/* MR20 */
 41#define SPD5118_REG_TEMP_CONFIG		0x1A	/* MR26 */
 42#define SPD5118_REG_TEMP_MAX		0x1c	/* MR28:MR29 */
 43#define SPD5118_REG_TEMP_MIN		0x1e	/* MR30:MR31 */
 44#define SPD5118_REG_TEMP_CRIT		0x20	/* MR32:MR33 */
 45#define SPD5118_REG_TEMP_LCRIT		0x22	/* MR34:MR35 */
 46#define SPD5118_REG_TEMP		0x31	/* MR49:MR50 */
 47#define SPD5118_REG_TEMP_STATUS		0x33	/* MR51 */
 48
 49#define SPD5118_TEMP_STATUS_HIGH	BIT(0)
 50#define SPD5118_TEMP_STATUS_LOW		BIT(1)
 51#define SPD5118_TEMP_STATUS_CRIT	BIT(2)
 52#define SPD5118_TEMP_STATUS_LCRIT	BIT(3)
 53
 54#define SPD5118_CAP_TS_SUPPORT		BIT(1)	/* temperature sensor support */
 55
 56#define SPD5118_TS_DISABLE		BIT(0)	/* temperature sensor disable */
 57
 58#define SPD5118_LEGACY_MODE_ADDR	BIT(3)
 59#define SPD5118_LEGACY_PAGE_MASK	GENMASK(2, 0)
 60#define SPD5118_LEGACY_MODE_MASK	(SPD5118_LEGACY_MODE_ADDR | SPD5118_LEGACY_PAGE_MASK)
 61
 62#define SPD5118_NUM_PAGES		8
 63#define SPD5118_PAGE_SIZE		128
 64#define SPD5118_PAGE_SHIFT		7
 65#define SPD5118_PAGE_MASK		GENMASK(6, 0)
 66#define SPD5118_EEPROM_BASE		0x80
 67#define SPD5118_EEPROM_SIZE		(SPD5118_PAGE_SIZE * SPD5118_NUM_PAGES)
 68
 69#define PAGE_ADDR0(page)		(((page) & BIT(0)) << 6)
 70#define PAGE_ADDR1_4(page)		(((page) & GENMASK(4, 1)) >> 1)
 71
 72/* Temperature unit in millicelsius */
 73#define SPD5118_TEMP_UNIT		(MILLIDEGREE_PER_DEGREE / 4)
 74/* Representable temperature range in millicelsius */
 75#define SPD5118_TEMP_RANGE_MIN		-256000
 76#define SPD5118_TEMP_RANGE_MAX		255750
 77
 78struct spd5118_data {
 79	struct regmap *regmap;
 80	struct mutex nvmem_lock;
 81	bool is_16bit;
 82};
 83
 84/* hwmon */
 85
 86static int spd5118_temp_from_reg(u16 reg)
 87{
 88	int temp = sign_extend32(reg >> 2, 10);
 89
 90	return temp * SPD5118_TEMP_UNIT;
 91}
 92
 93static u16 spd5118_temp_to_reg(long temp)
 94{
 95	temp = clamp_val(temp, SPD5118_TEMP_RANGE_MIN, SPD5118_TEMP_RANGE_MAX);
 96	return (DIV_ROUND_CLOSEST(temp, SPD5118_TEMP_UNIT) & 0x7ff) << 2;
 97}
 98
 99static int spd5118_read_temp(struct regmap *regmap, u32 attr, long *val)
100{
101	int reg, err;
102	u8 regval[2];
103	u16 temp;
104
105	switch (attr) {
106	case hwmon_temp_input:
107		reg = SPD5118_REG_TEMP;
108		break;
109	case hwmon_temp_max:
110		reg = SPD5118_REG_TEMP_MAX;
111		break;
112	case hwmon_temp_min:
113		reg = SPD5118_REG_TEMP_MIN;
114		break;
115	case hwmon_temp_crit:
116		reg = SPD5118_REG_TEMP_CRIT;
117		break;
118	case hwmon_temp_lcrit:
119		reg = SPD5118_REG_TEMP_LCRIT;
120		break;
121	default:
122		return -EOPNOTSUPP;
123	}
124
125	err = regmap_bulk_read(regmap, reg, regval, 2);
126	if (err)
127		return err;
128
129	temp = (regval[1] << 8) | regval[0];
130
131	*val = spd5118_temp_from_reg(temp);
132	return 0;
133}
134
135static int spd5118_read_alarm(struct regmap *regmap, u32 attr, long *val)
136{
137	unsigned int mask, regval;
138	int err;
139
140	switch (attr) {
141	case hwmon_temp_max_alarm:
142		mask = SPD5118_TEMP_STATUS_HIGH;
143		break;
144	case hwmon_temp_min_alarm:
145		mask = SPD5118_TEMP_STATUS_LOW;
146		break;
147	case hwmon_temp_crit_alarm:
148		mask = SPD5118_TEMP_STATUS_CRIT;
149		break;
150	case hwmon_temp_lcrit_alarm:
151		mask = SPD5118_TEMP_STATUS_LCRIT;
152		break;
153	default:
154		return -EOPNOTSUPP;
155	}
156
157	err = regmap_read(regmap, SPD5118_REG_TEMP_STATUS, &regval);
158	if (err < 0)
159		return err;
160	*val = !!(regval & mask);
161	if (*val)
162		return regmap_write(regmap, SPD5118_REG_TEMP_CLR, mask);
163	return 0;
164}
165
166static int spd5118_read_enable(struct regmap *regmap, long *val)
167{
168	u32 regval;
169	int err;
170
171	err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval);
172	if (err < 0)
173		return err;
174	*val = !(regval & SPD5118_TS_DISABLE);
175	return 0;
176}
177
178static int spd5118_read(struct device *dev, enum hwmon_sensor_types type,
179			u32 attr, int channel, long *val)
180{
181	struct regmap *regmap = dev_get_drvdata(dev);
182
183	if (type != hwmon_temp)
184		return -EOPNOTSUPP;
185
186	switch (attr) {
187	case hwmon_temp_input:
188	case hwmon_temp_max:
189	case hwmon_temp_min:
190	case hwmon_temp_crit:
191	case hwmon_temp_lcrit:
192		return spd5118_read_temp(regmap, attr, val);
193	case hwmon_temp_max_alarm:
194	case hwmon_temp_min_alarm:
195	case hwmon_temp_crit_alarm:
196	case hwmon_temp_lcrit_alarm:
197		return spd5118_read_alarm(regmap, attr, val);
198	case hwmon_temp_enable:
199		return spd5118_read_enable(regmap, val);
200	default:
201		return -EOPNOTSUPP;
202	}
203}
204
205static int spd5118_write_temp(struct regmap *regmap, u32 attr, long val)
206{
207	u8 regval[2];
208	u16 temp;
209	int reg;
210
211	switch (attr) {
212	case hwmon_temp_max:
213		reg = SPD5118_REG_TEMP_MAX;
214		break;
215	case hwmon_temp_min:
216		reg = SPD5118_REG_TEMP_MIN;
217		break;
218	case hwmon_temp_crit:
219		reg = SPD5118_REG_TEMP_CRIT;
220		break;
221	case hwmon_temp_lcrit:
222		reg = SPD5118_REG_TEMP_LCRIT;
223		break;
224	default:
225		return -EOPNOTSUPP;
226	}
227
228	temp = spd5118_temp_to_reg(val);
229	regval[0] = temp & 0xff;
230	regval[1] = temp >> 8;
231
232	return regmap_bulk_write(regmap, reg, regval, 2);
233}
234
235static int spd5118_write_enable(struct regmap *regmap, long val)
236{
237	if (val && val != 1)
238		return -EINVAL;
239
240	return regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG,
241				  SPD5118_TS_DISABLE,
242				  val ? 0 : SPD5118_TS_DISABLE);
243}
244
245static int spd5118_temp_write(struct regmap *regmap, u32 attr, long val)
246{
247	switch (attr) {
248	case hwmon_temp_max:
249	case hwmon_temp_min:
250	case hwmon_temp_crit:
251	case hwmon_temp_lcrit:
252		return spd5118_write_temp(regmap, attr, val);
253	case hwmon_temp_enable:
254		return spd5118_write_enable(regmap, val);
255	default:
256		return -EOPNOTSUPP;
257	}
258}
259
260static int spd5118_write(struct device *dev, enum hwmon_sensor_types type,
261			 u32 attr, int channel, long val)
262{
263	struct regmap *regmap = dev_get_drvdata(dev);
264
265	switch (type) {
266	case hwmon_temp:
267		return spd5118_temp_write(regmap, attr, val);
268	default:
269		return -EOPNOTSUPP;
270	}
271}
272
273static umode_t spd5118_is_visible(const void *_data, enum hwmon_sensor_types type,
274				  u32 attr, int channel)
275{
276	if (type != hwmon_temp)
277		return 0;
278
279	switch (attr) {
280	case hwmon_temp_input:
281		return 0444;
282	case hwmon_temp_min:
283	case hwmon_temp_max:
284	case hwmon_temp_lcrit:
285	case hwmon_temp_crit:
286	case hwmon_temp_enable:
287		return 0644;
288	case hwmon_temp_min_alarm:
289	case hwmon_temp_max_alarm:
290	case hwmon_temp_crit_alarm:
291	case hwmon_temp_lcrit_alarm:
292		return 0444;
293	default:
294		return 0;
295	}
296}
297
298/*
299 * Bank and vendor id are 8-bit fields with seven data bits and odd parity.
300 * Vendor IDs 0 and 0x7f are invalid.
301 * See Jedec standard JEP106BJ for details and a list of assigned vendor IDs.
302 */
303static bool spd5118_vendor_valid(u8 bank, u8 id)
304{
305	if (parity8(bank) == 0 || parity8(id) == 0)
306		return false;
307
308	id &= 0x7f;
309	return id && id != 0x7f;
310}
311
312static const struct hwmon_channel_info *spd5118_info[] = {
313	HWMON_CHANNEL_INFO(chip,
314			   HWMON_C_REGISTER_TZ),
315	HWMON_CHANNEL_INFO(temp,
316			   HWMON_T_INPUT |
317			   HWMON_T_LCRIT | HWMON_T_LCRIT_ALARM |
318			   HWMON_T_MIN | HWMON_T_MIN_ALARM |
319			   HWMON_T_MAX | HWMON_T_MAX_ALARM |
320			   HWMON_T_CRIT | HWMON_T_CRIT_ALARM |
321			   HWMON_T_ENABLE),
322	NULL
323};
324
325static const struct hwmon_ops spd5118_hwmon_ops = {
326	.is_visible = spd5118_is_visible,
327	.read = spd5118_read,
328	.write = spd5118_write,
329};
330
331static const struct hwmon_chip_info spd5118_chip_info = {
332	.ops = &spd5118_hwmon_ops,
333	.info = spd5118_info,
334};
335
336/* nvmem */
337
338static ssize_t spd5118_nvmem_read_page(struct spd5118_data *data, char *buf,
339				       unsigned int offset, size_t count)
340{
341	int page = offset >> SPD5118_PAGE_SHIFT;
342	struct regmap *regmap = data->regmap;
343	int err, addr;
344
345	offset &= SPD5118_PAGE_MASK;
346
347	/* Can't cross page boundaries */
348	if (offset + count > SPD5118_PAGE_SIZE)
349		count = SPD5118_PAGE_SIZE - offset;
350
351	if (data->is_16bit) {
352		addr = SPD5118_EEPROM_BASE | PAGE_ADDR0(page) |
353		  (PAGE_ADDR1_4(page) << 8);
354	} else {
355		addr = page * 0x100 + SPD5118_EEPROM_BASE;
356	}
357	err = regmap_bulk_read(regmap, addr + offset, buf, count);
358	if (err)
359		return err;
360
361	return count;
362}
363
364static int spd5118_nvmem_read(void *priv, unsigned int off, void *val, size_t count)
365{
366	struct spd5118_data *data = priv;
367	char *buf = val;
368	int ret;
369
370	if (unlikely(!count))
371		return count;
372
373	if (off + count > SPD5118_EEPROM_SIZE)
374		return -EINVAL;
375
376	mutex_lock(&data->nvmem_lock);
377
378	while (count) {
379		ret = spd5118_nvmem_read_page(data, buf, off, count);
380		if (ret < 0) {
381			mutex_unlock(&data->nvmem_lock);
382			return ret;
383		}
384		buf += ret;
385		off += ret;
386		count -= ret;
387	}
388	mutex_unlock(&data->nvmem_lock);
389	return 0;
390}
391
392static int spd5118_nvmem_init(struct device *dev, struct spd5118_data *data)
393{
394	struct nvmem_config nvmem_config = {
395		.type = NVMEM_TYPE_EEPROM,
396		.name = dev_name(dev),
397		.id = NVMEM_DEVID_NONE,
398		.dev = dev,
399		.base_dev = dev,
400		.read_only = true,
401		.root_only = false,
402		.owner = THIS_MODULE,
403		.compat = true,
404		.reg_read = spd5118_nvmem_read,
405		.priv = data,
406		.stride = 1,
407		.word_size = 1,
408		.size = SPD5118_EEPROM_SIZE,
409	};
410	struct nvmem_device *nvmem;
411
412	nvmem = devm_nvmem_register(dev, &nvmem_config);
413	return PTR_ERR_OR_ZERO(nvmem);
414}
415
416/* regmap */
417
418static bool spd5118_writeable_reg(struct device *dev, unsigned int reg)
419{
420	switch (reg) {
421	case SPD5118_REG_I2C_LEGACY_MODE:
422	case SPD5118_REG_TEMP_CLR:
423	case SPD5118_REG_TEMP_CONFIG:
424	case SPD5118_REG_TEMP_MAX:
425	case SPD5118_REG_TEMP_MAX + 1:
426	case SPD5118_REG_TEMP_MIN:
427	case SPD5118_REG_TEMP_MIN + 1:
428	case SPD5118_REG_TEMP_CRIT:
429	case SPD5118_REG_TEMP_CRIT + 1:
430	case SPD5118_REG_TEMP_LCRIT:
431	case SPD5118_REG_TEMP_LCRIT + 1:
432		return true;
433	default:
434		return false;
435	}
436}
437
438static bool spd5118_volatile_reg(struct device *dev, unsigned int reg)
439{
440	switch (reg) {
441	case SPD5118_REG_TEMP_CLR:
442	case SPD5118_REG_ERROR_CLR:
443	case SPD5118_REG_TEMP:
444	case SPD5118_REG_TEMP + 1:
445	case SPD5118_REG_TEMP_STATUS:
446		return true;
447	default:
448		return false;
449	}
450}
451
452static const struct regmap_range_cfg spd5118_i2c_regmap_range_cfg[] = {
453	{
454	.selector_reg   = SPD5118_REG_I2C_LEGACY_MODE,
455	.selector_mask  = SPD5118_LEGACY_PAGE_MASK,
456	.selector_shift = 0,
457	.window_start   = 0,
458	.window_len     = 0x100,
459	.range_min      = 0,
460	.range_max      = 0x7ff,
461	},
462};
463
464static const struct regmap_config spd5118_regmap8_config = {
465	.reg_bits = 8,
466	.val_bits = 8,
467	.max_register = 0x7ff,
468	.writeable_reg = spd5118_writeable_reg,
469	.volatile_reg = spd5118_volatile_reg,
470	.cache_type = REGCACHE_MAPLE,
471
472	.ranges = spd5118_i2c_regmap_range_cfg,
473	.num_ranges = ARRAY_SIZE(spd5118_i2c_regmap_range_cfg),
474};
475
476static const struct regmap_config spd5118_regmap16_config = {
477	.reg_bits = 16,
478	.val_bits = 8,
479	.max_register = 0x7ff,
480	.writeable_reg = spd5118_writeable_reg,
481	.volatile_reg = spd5118_volatile_reg,
482	.cache_type = REGCACHE_MAPLE,
483};
484
485static int spd5118_suspend(struct device *dev)
486{
487	struct spd5118_data *data = dev_get_drvdata(dev);
488	struct regmap *regmap = data->regmap;
489	u32 regval;
490	int err;
491
492	/*
493	 * Make sure the configuration register in the regmap cache is current
494	 * before bypassing it.
495	 */
496	err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, &regval);
497	if (err < 0)
498		return err;
499
500	regcache_cache_bypass(regmap, true);
501	regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE,
502			   SPD5118_TS_DISABLE);
503	regcache_cache_bypass(regmap, false);
504
505	regcache_cache_only(regmap, true);
506	regcache_mark_dirty(regmap);
507
508	return 0;
509}
510
511static int spd5118_resume(struct device *dev)
512{
513	struct spd5118_data *data = dev_get_drvdata(dev);
514	struct regmap *regmap = data->regmap;
515
516	regcache_cache_only(regmap, false);
517	return regcache_sync(regmap);
518}
519
520static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume);
521
522static int spd5118_common_probe(struct device *dev, struct regmap *regmap,
523				bool is_16bit)
524{
525	unsigned int capability, revision, vendor, bank;
526	struct spd5118_data *data;
527	struct device *hwmon_dev;
528	int err;
529
530	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
531	if (!data)
532		return -ENOMEM;
533
534	err = regmap_read(regmap, SPD5118_REG_CAPABILITY, &capability);
535	if (err)
536		return err;
537	if (!(capability & SPD5118_CAP_TS_SUPPORT))
538		return -ENODEV;
539
540	data->is_16bit = is_16bit;
541
542	err = regmap_read(regmap, SPD5118_REG_REVISION, &revision);
543	if (err)
544		return err;
545
546	err = regmap_read(regmap, SPD5118_REG_VENDOR, &bank);
547	if (err)
548		return err;
549	err = regmap_read(regmap, SPD5118_REG_VENDOR + 1, &vendor);
550	if (err)
551		return err;
552	if (!spd5118_vendor_valid(bank, vendor))
553		return -ENODEV;
554
555	data->regmap = regmap;
556	mutex_init(&data->nvmem_lock);
557	dev_set_drvdata(dev, data);
558
559	err = spd5118_nvmem_init(dev, data);
560	/* Ignore if NVMEM support is disabled */
561	if (err && err != -EOPNOTSUPP) {
562		dev_err_probe(dev, err, "failed to register nvmem\n");
563		return err;
564	}
565
566	hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118",
567							 regmap, &spd5118_chip_info,
568							 NULL);
569	if (IS_ERR(hwmon_dev))
570		return PTR_ERR(hwmon_dev);
571
572	/*
573	 * From JESD300-5B
574	 *   MR2 bits [5:4]: Major revision, 1..4
575	 *   MR2 bits [3:1]: Minor revision, 0..8? Probably a typo, assume 1..8
576	 */
577	dev_info(dev, "DDR5 temperature sensor: vendor 0x%02x:0x%02x revision %d.%d\n",
578		 bank & 0x7f, vendor, ((revision >> 4) & 0x03) + 1, ((revision >> 1) & 0x07) + 1);
579
580	return 0;
581}
582
583/* I2C */
584
585/* Return 0 if detection is successful, -ENODEV otherwise */
586static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info)
587{
588	struct i2c_adapter *adapter = client->adapter;
589	int regval;
590
591	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
592				     I2C_FUNC_SMBUS_WORD_DATA))
593		return -ENODEV;
594
595	regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);
596	if (regval != 0x5118)
597		return -ENODEV;
598
599	regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR);
600	if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8))
601		return -ENODEV;
602
603	regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY);
604	if (regval < 0)
605		return -ENODEV;
606	if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc))
607		return -ENODEV;
608
609	regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR);
610	if (regval)
611		return -ENODEV;
612	regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR);
613	if (regval)
614		return -ENODEV;
615
616	regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION);
617	if (regval < 0 || (regval & 0xc1))
618		return -ENODEV;
619
620	regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG);
621	if (regval < 0)
622		return -ENODEV;
623	if (regval & ~SPD5118_TS_DISABLE)
624		return -ENODEV;
625
626	strscpy(info->type, "spd5118", I2C_NAME_SIZE);
627	return 0;
628}
629
630static int spd5118_i2c_init(struct i2c_client *client)
631{
632	struct i2c_adapter *adapter = client->adapter;
633	int err, regval, mode;
634
635	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
636				     I2C_FUNC_SMBUS_WORD_DATA))
637		return -ENODEV;
638
639	regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);
640	if (regval < 0 || (regval && regval != 0x5118))
641		return -ENODEV;
642
643	/*
644	 * If the device type registers return 0, it is possible that the chip
645	 * has a non-zero page selected and takes the specification literally,
646	 * i.e. disables access to volatile registers besides the page register
647	 * if the page is not 0. The Renesas/ITD SPD5118 Hub Controller is known
648	 * to show this behavior. Try to identify such chips.
649	 */
650	if (!regval) {
651		/* Vendor ID registers must also be 0 */
652		regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR);
653		if (regval)
654			return -ENODEV;
655
656		/* The selected page in MR11 must not be 0 */
657		mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE);
658		if (mode < 0 || (mode & ~SPD5118_LEGACY_MODE_MASK) ||
659		    !(mode & SPD5118_LEGACY_PAGE_MASK))
660			return -ENODEV;
661
662		err = i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE,
663						mode & SPD5118_LEGACY_MODE_ADDR);
664		if (err)
665			return -ENODEV;
666
667		/*
668		 * If the device type registers are still bad after selecting
669		 * page 0, this is not a SPD5118 device. Restore original
670		 * legacy mode register value and abort.
671		 */
672		regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE);
673		if (regval != 0x5118) {
674			i2c_smbus_write_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE, mode);
675			return -ENODEV;
676		}
677	}
678
679	/* We are reasonably sure that this is really a SPD5118 hub controller */
680	return 0;
681}
682
683/*
684 * 16-bit addressing note:
685 *
686 * If I2C_FUNC_I2C is not supported by an I2C adapter driver, regmap uses
687 * SMBus operations as alternative. To simulate a read operation with a 16-bit
688 * address, it writes the address using i2c_smbus_write_byte_data(), followed
689 * by one or more calls to i2c_smbus_read_byte() to read the data.
690 * Per spd5118 standard, a read operation after writing the address must start
691 * with <Sr> (Repeat Start). However, a SMBus read byte operation starts with
692 * <S> (Start). This resets the register address in the spd5118 chip. As result,
693 * i2c_smbus_read_byte() always returns data from register address 0x00.
694 *
695 * A working alternative to access chips with 16-bit register addresses in the
696 * absence of I2C_FUNC_I2C support is not known.
697 *
698 * For this reason, 16-bit addressing can only be supported with I2C if the
699 * adapter supports I2C_FUNC_I2C.
700 *
701 * For I2C, the addressing mode selected by the BIOS must not be changed.
702 * Experiments show that at least some PC BIOS versions will not change the
703 * addressing mode on a soft reboot and end up in setup, claiming that some
704 * configuration change happened. This will happen again after a power cycle,
705 * which does reset the addressing mode. To prevent this from happening,
706 * detect if 16-bit addressing is enabled and always use the currently
707 * configured addressing mode.
708 */
709
710static int spd5118_i2c_probe(struct i2c_client *client)
711{
712	const struct regmap_config *config;
713	struct device *dev = &client->dev;
714	struct regmap *regmap;
715	int err, mode;
716	bool is_16bit;
717
718	err = spd5118_i2c_init(client);
719	if (err)
720		return err;
721
722	mode = i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE);
723	if (mode < 0)
724		return mode;
725
726	is_16bit = mode & SPD5118_LEGACY_MODE_ADDR;
727	if (is_16bit) {
728		/*
729		 * See 16-bit addressing note above explaining why it is
730		 * necessary to check for I2C_FUNC_I2C support here.
731		 */
732		if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
733			dev_err(dev, "Adapter does not support 16-bit register addresses\n");
734			return -ENODEV;
735		}
736		config = &spd5118_regmap16_config;
737	} else {
738		config = &spd5118_regmap8_config;
739	}
740
741	regmap = devm_regmap_init_i2c(client, config);
742	if (IS_ERR(regmap))
743		return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n");
744
745	return spd5118_common_probe(dev, regmap, is_16bit);
746}
747
748static const struct i2c_device_id spd5118_i2c_id[] = {
749	{ "spd5118" },
750	{ }
751};
752MODULE_DEVICE_TABLE(i2c, spd5118_i2c_id);
753
754static const struct of_device_id spd5118_of_ids[] = {
755	{ .compatible = "jedec,spd5118", },
756	{ }
757};
758MODULE_DEVICE_TABLE(of, spd5118_of_ids);
759
760static struct i2c_driver spd5118_i2c_driver = {
761	.class		= I2C_CLASS_HWMON,
762	.driver = {
763		.name	= "spd5118",
764		.of_match_table = spd5118_of_ids,
765		.pm = pm_sleep_ptr(&spd5118_pm_ops),
766	},
767	.probe		= spd5118_i2c_probe,
768	.id_table	= spd5118_i2c_id,
769	.detect		= IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? spd5118_detect : NULL,
770	.address_list	= IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? normal_i2c : NULL,
771};
772
773module_i2c_driver(spd5118_i2c_driver);
774
775MODULE_AUTHOR("René Rebe <rene@exactcode.de>");
776MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
777MODULE_DESCRIPTION("SPD 5118 driver");
778MODULE_LICENSE("GPL");