cputemp.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2// Copyright (c) 2018-2021 Intel Corporation
  3
  4#include <linux/auxiliary_bus.h>
  5#include <linux/bitfield.h>
  6#include <linux/bitops.h>
  7#include <linux/hwmon.h>
  8#include <linux/jiffies.h>
  9#include <linux/module.h>
 10#include <linux/peci.h>
 11#include <linux/peci-cpu.h>
 12#include <linux/units.h>
 13
 14#include "common.h"
 15
 16#define CORE_NUMS_MAX		64
 17
 18#define BASE_CHANNEL_NUMS	5
 19#define CPUTEMP_CHANNEL_NUMS	(BASE_CHANNEL_NUMS + CORE_NUMS_MAX)
 20
 21#define TEMP_TARGET_FAN_TEMP_MASK	GENMASK(15, 8)
 22#define TEMP_TARGET_REF_TEMP_MASK	GENMASK(23, 16)
 23#define TEMP_TARGET_TJ_OFFSET_MASK	GENMASK(29, 24)
 24
 25#define DTS_MARGIN_MASK		GENMASK(15, 0)
 26#define PCS_MODULE_TEMP_MASK	GENMASK(15, 0)
 27
 28struct resolved_cores_reg {
 29	u8 bus;
 30	u8 dev;
 31	u8 func;
 32	u8 offset;
 33};
 34
 35struct cpu_info {
 36	struct resolved_cores_reg *reg;
 37	u8 min_peci_revision;
 38	s32 (*thermal_margin_to_millidegree)(u16 val);
 39};
 40
 41struct peci_temp_target {
 42	s32 tcontrol;
 43	s32 tthrottle;
 44	s32 tjmax;
 45	struct peci_sensor_state state;
 46};
 47
 48enum peci_temp_target_type {
 49	tcontrol_type,
 50	tthrottle_type,
 51	tjmax_type,
 52	crit_hyst_type,
 53};
 54
 55struct peci_cputemp {
 56	struct peci_device *peci_dev;
 57	struct device *dev;
 58	const char *name;
 59	const struct cpu_info *gen_info;
 60	struct {
 61		struct peci_temp_target target;
 62		struct peci_sensor_data die;
 63		struct peci_sensor_data dts;
 64		struct peci_sensor_data core[CORE_NUMS_MAX];
 65	} temp;
 66	const char **coretemp_label;
 67	DECLARE_BITMAP(core_mask, CORE_NUMS_MAX);
 68};
 69
 70enum cputemp_channels {
 71	channel_die,
 72	channel_dts,
 73	channel_tcontrol,
 74	channel_tthrottle,
 75	channel_tjmax,
 76	channel_core,
 77};
 78
 79static const char * const cputemp_label[BASE_CHANNEL_NUMS] = {
 80	"Die",
 81	"DTS",
 82	"Tcontrol",
 83	"Tthrottle",
 84	"Tjmax",
 85};
 86
 87static int update_temp_target(struct peci_cputemp *priv)
 88{
 89	s32 tthrottle_offset, tcontrol_margin;
 90	u32 pcs;
 91	int ret;
 92
 93	if (!peci_sensor_need_update(&priv->temp.target.state))
 94		return 0;
 95
 96	ret = peci_pcs_read(priv->peci_dev, PECI_PCS_TEMP_TARGET, 0, &pcs);
 97	if (ret)
 98		return ret;
 99
100	priv->temp.target.tjmax =
101		FIELD_GET(TEMP_TARGET_REF_TEMP_MASK, pcs) * MILLIDEGREE_PER_DEGREE;
102
103	tcontrol_margin = FIELD_GET(TEMP_TARGET_FAN_TEMP_MASK, pcs);
104	tcontrol_margin = sign_extend32(tcontrol_margin, 7) * MILLIDEGREE_PER_DEGREE;
105	priv->temp.target.tcontrol = priv->temp.target.tjmax - tcontrol_margin;
106
107	tthrottle_offset = FIELD_GET(TEMP_TARGET_TJ_OFFSET_MASK, pcs) * MILLIDEGREE_PER_DEGREE;
108	priv->temp.target.tthrottle = priv->temp.target.tjmax - tthrottle_offset;
109
110	peci_sensor_mark_updated(&priv->temp.target.state);
111
112	return 0;
113}
114
115static int get_temp_target(struct peci_cputemp *priv, enum peci_temp_target_type type, long *val)
116{
117	int ret;
118
119	ret = update_temp_target(priv);
120	if (ret)
121		return ret;
122
123	switch (type) {
124	case tcontrol_type:
125		*val = priv->temp.target.tcontrol;
126		break;
127	case tthrottle_type:
128		*val = priv->temp.target.tthrottle;
129		break;
130	case tjmax_type:
131		*val = priv->temp.target.tjmax;
132		break;
133	case crit_hyst_type:
134		*val = priv->temp.target.tcontrol;
135		break;
136	default:
137		ret = -EOPNOTSUPP;
138		break;
139	}
140	return ret;
141}
142
143/*
144 * Error codes:
145 *   0x8000: General sensor error
146 *   0x8001: Reserved
147 *   0x8002: Underflow on reading value
148 *   0x8003-0x81ff: Reserved
149 */
150static bool dts_valid(u16 val)
151{
152	return val < 0x8000 || val > 0x81ff;
153}
154
155/*
156 * Processors return a value of DTS reading in S10.6 fixed point format
157 * (16 bits: 10-bit signed magnitude, 6-bit fraction).
158 */
159static s32 dts_ten_dot_six_to_millidegree(u16 val)
160{
161	return sign_extend32(val, 15) * MILLIDEGREE_PER_DEGREE / 64;
162}
163
164/*
165 * For older processors, thermal margin reading is returned in S8.8 fixed
166 * point format (16 bits: 8-bit signed magnitude, 8-bit fraction).
167 */
168static s32 dts_eight_dot_eight_to_millidegree(u16 val)
169{
170	return sign_extend32(val, 15) * MILLIDEGREE_PER_DEGREE / 256;
171}
172
173static int get_die_temp(struct peci_cputemp *priv, long *val)
174{
175	long tjmax;
176	u16 temp;
177	int ret;
178
179	if (!peci_sensor_need_update(&priv->temp.die.state))
180		goto skip_update;
181
182	ret = peci_temp_read(priv->peci_dev, &temp);
183	if (ret)
184		return ret;
185
186	if (!dts_valid(temp))
187		return -EIO;
188
189	ret = get_temp_target(priv, tjmax_type, &tjmax);
190	if (ret)
191		return ret;
192
193	priv->temp.die.value = (s32)tjmax + dts_ten_dot_six_to_millidegree(temp);
194
195	peci_sensor_mark_updated(&priv->temp.die.state);
196
197skip_update:
198	*val = priv->temp.die.value;
199	return 0;
200}
201
202static int get_dts(struct peci_cputemp *priv, long *val)
203{
204	u16 thermal_margin;
205	long tcontrol;
206	u32 pcs;
207	int ret;
208
209	if (!peci_sensor_need_update(&priv->temp.dts.state))
210		goto skip_update;
211
212	ret = peci_pcs_read(priv->peci_dev, PECI_PCS_THERMAL_MARGIN, 0, &pcs);
213	if (ret)
214		return ret;
215
216	thermal_margin = FIELD_GET(DTS_MARGIN_MASK, pcs);
217	if (!dts_valid(thermal_margin))
218		return -EIO;
219
220	ret = get_temp_target(priv, tcontrol_type, &tcontrol);
221	if (ret)
222		return ret;
223
224	/* Note that the tcontrol should be available before calling it */
225	priv->temp.dts.value =
226		(s32)tcontrol - priv->gen_info->thermal_margin_to_millidegree(thermal_margin);
227
228	peci_sensor_mark_updated(&priv->temp.dts.state);
229
230skip_update:
231	*val = priv->temp.dts.value;
232	return 0;
233}
234
235static int get_core_temp(struct peci_cputemp *priv, int core_index, long *val)
236{
237	u16 core_dts_margin;
238	long tjmax;
239	u32 pcs;
240	int ret;
241
242	if (!peci_sensor_need_update(&priv->temp.core[core_index].state))
243		goto skip_update;
244
245	ret = peci_pcs_read(priv->peci_dev, PECI_PCS_MODULE_TEMP, core_index, &pcs);
246	if (ret)
247		return ret;
248
249	core_dts_margin = FIELD_GET(PCS_MODULE_TEMP_MASK, pcs);
250	if (!dts_valid(core_dts_margin))
251		return -EIO;
252
253	ret = get_temp_target(priv, tjmax_type, &tjmax);
254	if (ret)
255		return ret;
256
257	/* Note that the tjmax should be available before calling it */
258	priv->temp.core[core_index].value =
259		(s32)tjmax + dts_ten_dot_six_to_millidegree(core_dts_margin);
260
261	peci_sensor_mark_updated(&priv->temp.core[core_index].state);
262
263skip_update:
264	*val = priv->temp.core[core_index].value;
265	return 0;
266}
267
268static int cputemp_read_string(struct device *dev, enum hwmon_sensor_types type,
269			       u32 attr, int channel, const char **str)
270{
271	struct peci_cputemp *priv = dev_get_drvdata(dev);
272
273	if (attr != hwmon_temp_label)
274		return -EOPNOTSUPP;
275
276	*str = channel < channel_core ?
277		cputemp_label[channel] : priv->coretemp_label[channel - channel_core];
278
279	return 0;
280}
281
282static int cputemp_read(struct device *dev, enum hwmon_sensor_types type,
283			u32 attr, int channel, long *val)
284{
285	struct peci_cputemp *priv = dev_get_drvdata(dev);
286
287	switch (attr) {
288	case hwmon_temp_input:
289		switch (channel) {
290		case channel_die:
291			return get_die_temp(priv, val);
292		case channel_dts:
293			return get_dts(priv, val);
294		case channel_tcontrol:
295			return get_temp_target(priv, tcontrol_type, val);
296		case channel_tthrottle:
297			return get_temp_target(priv, tthrottle_type, val);
298		case channel_tjmax:
299			return get_temp_target(priv, tjmax_type, val);
300		default:
301			return get_core_temp(priv, channel - channel_core, val);
302		}
303		break;
304	case hwmon_temp_max:
305		return get_temp_target(priv, tcontrol_type, val);
306	case hwmon_temp_crit:
307		return get_temp_target(priv, tjmax_type, val);
308	case hwmon_temp_crit_hyst:
309		return get_temp_target(priv, crit_hyst_type, val);
310	default:
311		return -EOPNOTSUPP;
312	}
313
314	return 0;
315}
316
317static umode_t cputemp_is_visible(const void *data, enum hwmon_sensor_types type,
318				  u32 attr, int channel)
319{
320	const struct peci_cputemp *priv = data;
321
322	if (channel >= CPUTEMP_CHANNEL_NUMS)
323		return 0;
324
325	if (channel < channel_core)
326		return 0444;
327
328	if (test_bit(channel - channel_core, priv->core_mask))
329		return 0444;
330
331	return 0;
332}
333
334static int init_core_mask(struct peci_cputemp *priv)
335{
336	struct peci_device *peci_dev = priv->peci_dev;
337	struct resolved_cores_reg *reg = priv->gen_info->reg;
338	u64 core_mask;
339	u32 data;
340	int ret;
341
342	/* Get the RESOLVED_CORES register value */
343	switch (peci_dev->info.x86_vfm) {
344	case INTEL_ICELAKE_X:
345	case INTEL_ICELAKE_D:
346	case INTEL_SAPPHIRERAPIDS_X:
347	case INTEL_EMERALDRAPIDS_X:
348		ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
349					     reg->func, reg->offset + 4, &data);
350		if (ret)
351			return ret;
352
353		core_mask = (u64)data << 32;
354
355		ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
356					     reg->func, reg->offset, &data);
357		if (ret)
358			return ret;
359
360		core_mask |= data;
361
362		break;
363	default:
364		ret = peci_pci_local_read(peci_dev, reg->bus, reg->dev,
365					  reg->func, reg->offset, &data);
366		if (ret)
367			return ret;
368
369		core_mask = data;
370
371		break;
372	}
373
374	if (!core_mask)
375		return -EIO;
376
377	bitmap_from_u64(priv->core_mask, core_mask);
378
379	return 0;
380}
381
382static int create_temp_label(struct peci_cputemp *priv)
383{
384	unsigned long core_max = find_last_bit(priv->core_mask, CORE_NUMS_MAX);
385	int i;
386
387	priv->coretemp_label = devm_kzalloc(priv->dev, (core_max + 1) * sizeof(char *), GFP_KERNEL);
388	if (!priv->coretemp_label)
389		return -ENOMEM;
390
391	for_each_set_bit(i, priv->core_mask, CORE_NUMS_MAX) {
392		priv->coretemp_label[i] = devm_kasprintf(priv->dev, GFP_KERNEL, "Core %d", i);
393		if (!priv->coretemp_label[i])
394			return -ENOMEM;
395	}
396
397	return 0;
398}
399
400static void check_resolved_cores(struct peci_cputemp *priv)
401{
402	/*
403	 * Failure to resolve cores is non-critical, we're still able to
404	 * provide other sensor data.
405	 */
406
407	if (init_core_mask(priv))
408		return;
409
410	if (create_temp_label(priv))
411		bitmap_zero(priv->core_mask, CORE_NUMS_MAX);
412}
413
414static const struct hwmon_ops peci_cputemp_ops = {
415	.is_visible = cputemp_is_visible,
416	.read_string = cputemp_read_string,
417	.read = cputemp_read,
418};
419
420static const struct hwmon_channel_info * const peci_cputemp_info[] = {
421	HWMON_CHANNEL_INFO(temp,
422			   /* Die temperature */
423			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX |
424			   HWMON_T_CRIT | HWMON_T_CRIT_HYST,
425			   /* DTS margin */
426			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX |
427			   HWMON_T_CRIT | HWMON_T_CRIT_HYST,
428			   /* Tcontrol temperature */
429			   HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_CRIT,
430			   /* Tthrottle temperature */
431			   HWMON_T_LABEL | HWMON_T_INPUT,
432			   /* Tjmax temperature */
433			   HWMON_T_LABEL | HWMON_T_INPUT,
434			   /* Core temperature - for all core channels */
435			   [channel_core ... CPUTEMP_CHANNEL_NUMS - 1] =
436						HWMON_T_LABEL | HWMON_T_INPUT),
437	NULL
438};
439
440static const struct hwmon_chip_info peci_cputemp_chip_info = {
441	.ops = &peci_cputemp_ops,
442	.info = peci_cputemp_info,
443};
444
445static int peci_cputemp_probe(struct auxiliary_device *adev,
446			      const struct auxiliary_device_id *id)
447{
448	struct device *dev = &adev->dev;
449	struct peci_device *peci_dev = to_peci_device(dev->parent);
450	struct peci_cputemp *priv;
451	struct device *hwmon_dev;
452
453	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
454	if (!priv)
455		return -ENOMEM;
456
457	priv->name = devm_kasprintf(dev, GFP_KERNEL, "peci_cputemp.cpu%d",
458				    peci_dev->info.socket_id);
459	if (!priv->name)
460		return -ENOMEM;
461
462	priv->dev = dev;
463	priv->peci_dev = peci_dev;
464	priv->gen_info = (const struct cpu_info *)id->driver_data;
465
466	/*
467	 * This is just a sanity check. Since we're using commands that are
468	 * guaranteed to be supported on a given platform, we should never see
469	 * revision lower than expected.
470	 */
471	if (peci_dev->info.peci_revision < priv->gen_info->min_peci_revision)
472		dev_warn(priv->dev,
473			 "Unexpected PECI revision %#x, some features may be unavailable\n",
474			 peci_dev->info.peci_revision);
475
476	check_resolved_cores(priv);
477
478	hwmon_dev = devm_hwmon_device_register_with_info(priv->dev, priv->name,
479							 priv, &peci_cputemp_chip_info, NULL);
480
481	return PTR_ERR_OR_ZERO(hwmon_dev);
482}
483
484/*
485 * RESOLVED_CORES PCI configuration register may have different location on
486 * different platforms.
487 */
488static struct resolved_cores_reg resolved_cores_reg_hsx = {
489	.bus = 1,
490	.dev = 30,
491	.func = 3,
492	.offset = 0xb4,
493};
494
495static struct resolved_cores_reg resolved_cores_reg_icx = {
496	.bus = 14,
497	.dev = 30,
498	.func = 3,
499	.offset = 0xd0,
500};
501
502static struct resolved_cores_reg resolved_cores_reg_spr = {
503	.bus = 31,
504	.dev = 30,
505	.func = 6,
506	.offset = 0x80,
507};
508
509static struct resolved_cores_reg resolved_cores_reg_emr = {
510	.bus = 31,
511	.dev = 30,
512	.func = 6,
513	.offset = 0x80,
514};
515
516static const struct cpu_info cpu_hsx = {
517	.reg		= &resolved_cores_reg_hsx,
518	.min_peci_revision = 0x33,
519	.thermal_margin_to_millidegree = &dts_eight_dot_eight_to_millidegree,
520};
521
522static const struct cpu_info cpu_skx = {
523	.reg		= &resolved_cores_reg_hsx,
524	.min_peci_revision = 0x33,
525	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
526};
527
528static const struct cpu_info cpu_icx = {
529	.reg		= &resolved_cores_reg_icx,
530	.min_peci_revision = 0x40,
531	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
532};
533
534static const struct cpu_info cpu_spr = {
535	.reg		= &resolved_cores_reg_spr,
536	.min_peci_revision = 0x40,
537	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
538};
539
540static const struct cpu_info cpu_emr = {
541	.reg    = &resolved_cores_reg_emr,
542	.min_peci_revision = 0x40,
543	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
544};
545
546static const struct auxiliary_device_id peci_cputemp_ids[] = {
547	{
548		.name = "peci_cpu.cputemp.hsx",
549		.driver_data = (kernel_ulong_t)&cpu_hsx,
550	},
551	{
552		.name = "peci_cpu.cputemp.bdx",
553		.driver_data = (kernel_ulong_t)&cpu_hsx,
554	},
555	{
556		.name = "peci_cpu.cputemp.bdxd",
557		.driver_data = (kernel_ulong_t)&cpu_hsx,
558	},
559	{
560		.name = "peci_cpu.cputemp.skx",
561		.driver_data = (kernel_ulong_t)&cpu_skx,
562	},
563	{
564		.name = "peci_cpu.cputemp.icx",
565		.driver_data = (kernel_ulong_t)&cpu_icx,
566	},
567	{
568		.name = "peci_cpu.cputemp.icxd",
569		.driver_data = (kernel_ulong_t)&cpu_icx,
570	},
571	{
572		.name = "peci_cpu.cputemp.spr",
573		.driver_data = (kernel_ulong_t)&cpu_spr,
574	},
575	{
576		.name = "peci_cpu.cputemp.emr",
577		.driver_data = (kernel_ulong_t)&cpu_emr,
578	},
579	{ }
580};
581MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
582
583static struct auxiliary_driver peci_cputemp_driver = {
584	.probe		= peci_cputemp_probe,
585	.id_table	= peci_cputemp_ids,
586};
587
588module_auxiliary_driver(peci_cputemp_driver);
589
590MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>");
591MODULE_AUTHOR("Iwona Winiarska <iwona.winiarska@intel.com>");
592MODULE_DESCRIPTION("PECI cputemp driver");
593MODULE_LICENSE("GPL");
594MODULE_IMPORT_NS("PECI_CPU");