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npcm750-pwm-fan.c
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linux-6.19.14/drivers/hwmon/npcm750-pwm-fan.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2014-2018 Nuvoton Technology corporation. 3 4#include <linux/clk.h> 5#include <linux/device.h> 6#include <linux/hwmon.h> 7#include <linux/interrupt.h> 8#include <linux/kernel.h> 9#include <linux/module.h> 10#include <linux/of_address.h> 11#include <linux/of_irq.h> 12#include <linux/platform_device.h> 13#include <linux/spinlock.h> 14#include <linux/sysfs.h> 15#include <linux/thermal.h> 16 17/* NPCM7XX PWM registers */ 18#define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 19 20#define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) 21#define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) 22#define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) 23#define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ 24 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) 25#define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ 26 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) 27#define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ 28 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) 29#define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C) 30#define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40) 31 32#define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3) 33#define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11) 34#define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15) 35#define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19) 36 37#define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2) 38#define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10) 39#define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14) 40#define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18) 41 42#define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0) 43#define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8) 44#define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12) 45#define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16) 46 47/* Define the maximum PWM channel number */ 48#define NPCM7XX_PWM_MAX_CHN_NUM 12 49#define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4 50#define NPCM7XX_PWM_MAX_MODULES 3 51 52/* Define the Counter Register, value = 100 for match 100% */ 53#define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255 54#define NPCM7XX_PWM_CMR_DEFAULT_NUM 255 55#define NPCM7XX_PWM_CMR_MAX 255 56 57/* default all PWM channels PRESCALE2 = 1 */ 58#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4 59#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40 60#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400 61#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000 62 63#define PWM_OUTPUT_FREQ_25KHZ 25000 64#define PWN_CNT_DEFAULT 256 65#define MIN_PRESCALE1 2 66#define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8 67 68#define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \ 69 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \ 70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \ 71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3) 72 73#define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \ 74 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \ 75 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \ 76 NPCM7XX_PWM_CTRL_CH3_MODE_BIT) 77 78/* NPCM7XX FAN Tacho registers */ 79#define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 80 81#define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00) 82#define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02) 83#define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04) 84#define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06) 85#define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08) 86#define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A) 87#define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C) 88#define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E) 89#define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10) 90#define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12) 91#define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14) 92#define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16) 93#define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18) 94#define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A) 95#define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C) 96 97#define NPCM7XX_FAN_TCKC_CLKX_NONE 0 98#define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0) 99#define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3) 100 101#define NPCM7XX_FAN_TMCTRL_TBEN BIT(6) 102#define NPCM7XX_FAN_TMCTRL_TAEN BIT(5) 103#define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4) 104#define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3) 105#define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2) 106 107#define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0) 108#define NPCM7XX_FAN_TICLR_TFCLR BIT(5) 109#define NPCM7XX_FAN_TICLR_TECLR BIT(4) 110#define NPCM7XX_FAN_TICLR_TDCLR BIT(3) 111#define NPCM7XX_FAN_TICLR_TCCLR BIT(2) 112#define NPCM7XX_FAN_TICLR_TBCLR BIT(1) 113#define NPCM7XX_FAN_TICLR_TACLR BIT(0) 114 115#define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0) 116#define NPCM7XX_FAN_TIEN_TFIEN BIT(5) 117#define NPCM7XX_FAN_TIEN_TEIEN BIT(4) 118#define NPCM7XX_FAN_TIEN_TDIEN BIT(3) 119#define NPCM7XX_FAN_TIEN_TCIEN BIT(2) 120#define NPCM7XX_FAN_TIEN_TBIEN BIT(1) 121#define NPCM7XX_FAN_TIEN_TAIEN BIT(0) 122 123#define NPCM7XX_FAN_TICTRL_TFPND BIT(5) 124#define NPCM7XX_FAN_TICTRL_TEPND BIT(4) 125#define NPCM7XX_FAN_TICTRL_TDPND BIT(3) 126#define NPCM7XX_FAN_TICTRL_TCPND BIT(2) 127#define NPCM7XX_FAN_TICTRL_TBPND BIT(1) 128#define NPCM7XX_FAN_TICTRL_TAPND BIT(0) 129 130#define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7) 131#define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6) 132#define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5) 133#define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4) 134#define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3) 135#define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2) 136#define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1) 137#define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0) 138 139/* FAN General Definition */ 140/* Define the maximum FAN channel number */ 141#define NPCM7XX_FAN_MAX_MODULE 8 142#define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2 143#define NPCM7XX_FAN_MAX_CHN_NUM 16 144 145/* 146 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us) 147 * Timeout 94ms ~= 0x5000 148 * (The minimum FAN speed could to support ~640RPM/pulse 1, 149 * 320RPM/pulse 2, ...-- 10.6Hz) 150 */ 151#define NPCM7XX_FAN_TIMEOUT 0x5000 152#define NPCM7XX_FAN_TCNT 0xFFFF 153#define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 154#define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 155 156#define NPCM7XX_FAN_POLL_TIMER_200MS 200 157#define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2 158#define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0 159#define NPCM7XX_FAN_CLK_PRESCALE 255 160 161#define NPCM7XX_FAN_CMPA 0 162#define NPCM7XX_FAN_CMPB 1 163 164/* Obtain the fan number */ 165#define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp)) 166 167/* fan sample status */ 168#define FAN_DISABLE 0xFF 169#define FAN_INIT 0x00 170#define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01 171#define FAN_ENOUGH_SAMPLE 0x02 172 173struct npcm_hwmon_info { 174 u32 pwm_max_channel; 175}; 176 177struct npcm7xx_fan_dev { 178 u8 fan_st_flg; 179 u8 fan_pls_per_rev; 180 u16 fan_cnt; 181 u32 fan_cnt_tmp; 182}; 183 184struct npcm7xx_cooling_device { 185 char name[THERMAL_NAME_LENGTH]; 186 struct npcm7xx_pwm_fan_data *data; 187 struct thermal_cooling_device *tcdev; 188 int pwm_port; 189 u8 *cooling_levels; 190 u8 max_state; 191 u8 cur_state; 192}; 193 194struct npcm7xx_pwm_fan_data { 195 void __iomem *pwm_base; 196 void __iomem *fan_base; 197 int pwm_modules; 198 struct clk *pwm_clk; 199 struct clk *fan_clk; 200 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE]; 201 int fan_irq[NPCM7XX_FAN_MAX_MODULE]; 202 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM]; 203 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM]; 204 u32 input_clk_freq; 205 struct timer_list fan_timer; 206 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM]; 207 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM]; 208 const struct npcm_hwmon_info *info; 209 u8 fan_select; 210}; 211 212static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data, 213 int channel, u16 val) 214{ 215 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 216 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 217 u32 tmp_buf, ctrl_en_bit, env_bit; 218 219 /* 220 * Config PWM Comparator register for setting duty cycle 221 */ 222 223 /* write new CMR value */ 224 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); 225 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 226 227 switch (pwm_ch) { 228 case 0: 229 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT; 230 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT; 231 break; 232 case 1: 233 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT; 234 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT; 235 break; 236 case 2: 237 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT; 238 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT; 239 break; 240 case 3: 241 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT; 242 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT; 243 break; 244 default: 245 return -ENODEV; 246 } 247 248 if (val == 0) { 249 /* Disable PWM */ 250 tmp_buf &= ~ctrl_en_bit; 251 tmp_buf |= env_bit; 252 } else { 253 /* Enable PWM */ 254 tmp_buf |= ctrl_en_bit; 255 tmp_buf &= ~env_bit; 256 } 257 258 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 259 return 0; 260} 261 262static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data, 263 u8 fan, u8 cmp) 264{ 265 u8 fan_id; 266 u8 reg_mode; 267 u8 reg_int; 268 unsigned long flags; 269 270 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 271 272 /* to check whether any fan tach is enable */ 273 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) { 274 /* reset status */ 275 spin_lock_irqsave(&data->fan_lock[fan], flags); 276 277 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 278 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 279 280 /* 281 * the interrupt enable bits do not need to be cleared before 282 * it sets, the interrupt enable bits are cleared only on reset. 283 * the clock unit control register is behaving in the same 284 * manner that the interrupt enable register behave. 285 */ 286 if (cmp == NPCM7XX_FAN_CMPA) { 287 /* enable interrupt */ 288 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN | 289 NPCM7XX_FAN_TIEN_TEIEN), 290 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 291 292 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB 293 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 294 fan)); 295 296 /* start to Capture */ 297 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base, 298 fan)); 299 } else { 300 /* enable interrupt */ 301 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN | 302 NPCM7XX_FAN_TIEN_TFIEN), 303 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 304 305 reg_mode = 306 NPCM7XX_FAN_TCKC_CLK2_APB 307 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 308 fan)); 309 310 /* start to Capture */ 311 iowrite8(reg_mode, 312 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 313 } 314 315 spin_unlock_irqrestore(&data->fan_lock[fan], flags); 316 } 317} 318 319/* 320 * Enable a background timer to poll fan tach value, (200ms * 4) 321 * to polling all fan 322 */ 323static void npcm7xx_fan_polling(struct timer_list *t) 324{ 325 struct npcm7xx_pwm_fan_data *data; 326 int i; 327 328 data = timer_container_of(data, t, fan_timer); 329 330 /* 331 * Polling two module per one round, 332 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415 333 */ 334 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE; 335 i = i + 4) { 336 /* clear the flag and reset the counter (TCNT) */ 337 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 338 NPCM7XX_FAN_REG_TICLR(data->fan_base, i)); 339 340 if (data->fan_present[i * 2]) { 341 iowrite16(NPCM7XX_FAN_TCNT, 342 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i)); 343 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA); 344 } 345 if (data->fan_present[(i * 2) + 1]) { 346 iowrite16(NPCM7XX_FAN_TCNT, 347 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i)); 348 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB); 349 } 350 } 351 352 data->fan_select++; 353 data->fan_select &= 0x3; 354 355 /* reset the timer interval */ 356 data->fan_timer.expires = jiffies + 357 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 358 add_timer(&data->fan_timer); 359} 360 361static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data, 362 u8 fan, u8 cmp, u8 fan_id, u8 flag_int, 363 u8 flag_mode, u8 flag_clear) 364{ 365 u8 reg_int; 366 u8 reg_mode; 367 u16 fan_cap; 368 369 if (cmp == NPCM7XX_FAN_CMPA) 370 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan)); 371 else 372 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan)); 373 374 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */ 375 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 376 377 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) { 378 /* First capture, drop it */ 379 data->fan_dev[fan_id].fan_st_flg = 380 FAN_PREPARE_TO_GET_FIRST_CAPTURE; 381 382 /* reset counter */ 383 data->fan_dev[fan_id].fan_cnt_tmp = 0; 384 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) { 385 /* 386 * collect the enough sample, 387 * (ex: 2 pulse fan need to get 2 sample) 388 */ 389 data->fan_dev[fan_id].fan_cnt_tmp += 390 (NPCM7XX_FAN_TCNT - fan_cap); 391 392 data->fan_dev[fan_id].fan_st_flg++; 393 } else { 394 /* get enough sample or fan disable */ 395 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) { 396 data->fan_dev[fan_id].fan_cnt_tmp += 397 (NPCM7XX_FAN_TCNT - fan_cap); 398 399 /* compute finial average cnt per pulse */ 400 data->fan_dev[fan_id].fan_cnt = 401 data->fan_dev[fan_id].fan_cnt_tmp / 402 FAN_ENOUGH_SAMPLE; 403 404 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 405 } 406 407 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 408 409 /* disable interrupt */ 410 iowrite8((reg_int & ~flag_int), 411 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 412 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 413 414 /* stop capturing */ 415 iowrite8((reg_mode & ~flag_mode), 416 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 417 } 418} 419 420static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data, 421 u8 fan, u8 cmp, u8 flag) 422{ 423 u8 reg_int; 424 u8 reg_mode; 425 u8 flag_timeout; 426 u8 flag_cap; 427 u8 flag_clear; 428 u8 flag_int; 429 u8 flag_mode; 430 u8 fan_id; 431 432 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 433 434 if (cmp == NPCM7XX_FAN_CMPA) { 435 flag_cap = NPCM7XX_FAN_TICTRL_TAPND; 436 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND; 437 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN; 438 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB; 439 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR; 440 } else { 441 flag_cap = NPCM7XX_FAN_TICTRL_TBPND; 442 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND; 443 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN; 444 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB; 445 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR; 446 } 447 448 if (flag & flag_timeout) { 449 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 450 451 /* disable interrupt */ 452 iowrite8((reg_int & ~flag_int), 453 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 454 455 /* clear interrupt flag */ 456 iowrite8(flag_clear, 457 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 458 459 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 460 461 /* stop capturing */ 462 iowrite8((reg_mode & ~flag_mode), 463 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 464 465 /* 466 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't 467 * connect or speed is lower than 10.6Hz (320RPM/pulse2). 468 * In these situation, the RPM output should be zero. 469 */ 470 data->fan_dev[fan_id].fan_cnt = 0; 471 } else { 472 /* input capture is occurred */ 473 if (flag & flag_cap) 474 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int, 475 flag_mode, flag_clear); 476 } 477} 478 479static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id) 480{ 481 struct npcm7xx_pwm_fan_data *data = dev_id; 482 unsigned long flags; 483 int module; 484 u8 flag; 485 486 module = irq - data->fan_irq[0]; 487 spin_lock_irqsave(&data->fan_lock[module], flags); 488 489 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module)); 490 if (flag > 0) { 491 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag); 492 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag); 493 spin_unlock_irqrestore(&data->fan_lock[module], flags); 494 return IRQ_HANDLED; 495 } 496 497 spin_unlock_irqrestore(&data->fan_lock[module], flags); 498 499 return IRQ_NONE; 500} 501 502static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel, 503 long *val) 504{ 505 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 506 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 507 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 508 509 switch (attr) { 510 case hwmon_pwm_input: 511 *val = ioread32 512 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch)); 513 return 0; 514 default: 515 return -EOPNOTSUPP; 516 } 517} 518 519static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel, 520 long val) 521{ 522 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 523 int err; 524 525 switch (attr) { 526 case hwmon_pwm_input: 527 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX) 528 return -EINVAL; 529 err = npcm7xx_pwm_config_set(data, channel, (u16)val); 530 break; 531 default: 532 err = -EOPNOTSUPP; 533 break; 534 } 535 536 return err; 537} 538 539static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel) 540{ 541 const struct npcm7xx_pwm_fan_data *data = _data; 542 543 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel) 544 return 0; 545 546 switch (attr) { 547 case hwmon_pwm_input: 548 return 0644; 549 default: 550 return 0; 551 } 552} 553 554static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel, 555 long *val) 556{ 557 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 558 559 switch (attr) { 560 case hwmon_fan_input: 561 *val = 0; 562 if (data->fan_dev[channel].fan_cnt <= 0) 563 return data->fan_dev[channel].fan_cnt; 564 565 /* Convert the raw reading to RPM */ 566 if (data->fan_dev[channel].fan_cnt > 0 && 567 data->fan_dev[channel].fan_pls_per_rev > 0) 568 *val = ((data->input_clk_freq * 60) / 569 (data->fan_dev[channel].fan_cnt * 570 data->fan_dev[channel].fan_pls_per_rev)); 571 return 0; 572 default: 573 return -EOPNOTSUPP; 574 } 575} 576 577static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel) 578{ 579 const struct npcm7xx_pwm_fan_data *data = _data; 580 581 if (!data->fan_present[channel]) 582 return 0; 583 584 switch (attr) { 585 case hwmon_fan_input: 586 return 0444; 587 default: 588 return 0; 589 } 590} 591 592static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type, 593 u32 attr, int channel, long *val) 594{ 595 switch (type) { 596 case hwmon_pwm: 597 return npcm7xx_read_pwm(dev, attr, channel, val); 598 case hwmon_fan: 599 return npcm7xx_read_fan(dev, attr, channel, val); 600 default: 601 return -EOPNOTSUPP; 602 } 603} 604 605static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type, 606 u32 attr, int channel, long val) 607{ 608 switch (type) { 609 case hwmon_pwm: 610 return npcm7xx_write_pwm(dev, attr, channel, val); 611 default: 612 return -EOPNOTSUPP; 613 } 614} 615 616static umode_t npcm7xx_is_visible(const void *data, 617 enum hwmon_sensor_types type, 618 u32 attr, int channel) 619{ 620 switch (type) { 621 case hwmon_pwm: 622 return npcm7xx_pwm_is_visible(data, attr, channel); 623 case hwmon_fan: 624 return npcm7xx_fan_is_visible(data, attr, channel); 625 default: 626 return 0; 627 } 628} 629 630static const struct hwmon_channel_info * const npcm7xx_info[] = { 631 HWMON_CHANNEL_INFO(pwm, 632 HWMON_PWM_INPUT, 633 HWMON_PWM_INPUT, 634 HWMON_PWM_INPUT, 635 HWMON_PWM_INPUT, 636 HWMON_PWM_INPUT, 637 HWMON_PWM_INPUT, 638 HWMON_PWM_INPUT, 639 HWMON_PWM_INPUT, 640 HWMON_PWM_INPUT, 641 HWMON_PWM_INPUT, 642 HWMON_PWM_INPUT, 643 HWMON_PWM_INPUT), 644 HWMON_CHANNEL_INFO(fan, 645 HWMON_F_INPUT, 646 HWMON_F_INPUT, 647 HWMON_F_INPUT, 648 HWMON_F_INPUT, 649 HWMON_F_INPUT, 650 HWMON_F_INPUT, 651 HWMON_F_INPUT, 652 HWMON_F_INPUT, 653 HWMON_F_INPUT, 654 HWMON_F_INPUT, 655 HWMON_F_INPUT, 656 HWMON_F_INPUT, 657 HWMON_F_INPUT, 658 HWMON_F_INPUT, 659 HWMON_F_INPUT, 660 HWMON_F_INPUT), 661 NULL 662}; 663 664static const struct hwmon_ops npcm7xx_hwmon_ops = { 665 .is_visible = npcm7xx_is_visible, 666 .read = npcm7xx_read, 667 .write = npcm7xx_write, 668}; 669 670static const struct hwmon_chip_info npcm7xx_chip_info = { 671 .ops = &npcm7xx_hwmon_ops, 672 .info = npcm7xx_info, 673}; 674 675static const struct npcm_hwmon_info npxm7xx_hwmon_info = { 676 .pwm_max_channel = 8, 677}; 678 679static const struct npcm_hwmon_info npxm8xx_hwmon_info = { 680 .pwm_max_channel = 12, 681}; 682 683static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data) 684{ 685 int m, ch; 686 u32 prescale_val, output_freq; 687 unsigned long pwm_clk_freq; 688 689 pwm_clk_freq = clk_get_rate(data->pwm_clk); 690 691 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */ 692 output_freq = pwm_clk_freq / PWN_CNT_DEFAULT; 693 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ); 694 695 /* If prescale_val = 0, then the prescale output clock is stopped */ 696 if (prescale_val < MIN_PRESCALE1) 697 prescale_val = MIN_PRESCALE1; 698 /* 699 * prescale_val need to decrement in one because in the PWM Prescale 700 * register the Prescale value increment by one 701 */ 702 prescale_val--; 703 704 /* Setting PWM Prescale Register value register to both modules */ 705 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01); 706 707 for (m = 0; m < data->pwm_modules; m++) { 708 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m)); 709 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT, 710 NPCM7XX_PWM_REG_CSR(data->pwm_base, m)); 711 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT, 712 NPCM7XX_PWM_REG_CR(data->pwm_base, m)); 713 714 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) { 715 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM, 716 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch)); 717 } 718 } 719 720 return output_freq / ((prescale_val & 0xf) + 1); 721} 722 723static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data) 724{ 725 int md; 726 int ch; 727 int i; 728 u32 apb_clk_freq; 729 730 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) { 731 /* stop FAN0~7 clock */ 732 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE, 733 NPCM7XX_FAN_REG_TCKC(data->fan_base, md)); 734 735 /* disable all interrupt */ 736 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md)); 737 738 /* clear all interrupt */ 739 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 740 NPCM7XX_FAN_REG_TICLR(data->fan_base, md)); 741 742 /* set FAN0~7 clock prescaler */ 743 iowrite8(NPCM7XX_FAN_CLK_PRESCALE, 744 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md)); 745 746 /* set FAN0~7 mode (high-to-low transition) */ 747 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN | 748 NPCM7XX_FAN_TMCTRL_TAEN), 749 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md)); 750 751 /* set FAN0~7 Initial Count/Cap */ 752 iowrite16(NPCM7XX_FAN_TCNT, 753 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md)); 754 iowrite16(NPCM7XX_FAN_TCNT, 755 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md)); 756 757 /* set FAN0~7 compare (equal to count) */ 758 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN), 759 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md)); 760 761 /* set FAN0~7 compare value */ 762 iowrite16(NPCM7XX_FAN_TCPA, 763 NPCM7XX_FAN_REG_TCPA(data->fan_base, md)); 764 iowrite16(NPCM7XX_FAN_TCPB, 765 NPCM7XX_FAN_REG_TCPB(data->fan_base, md)); 766 767 /* set FAN0~7 fan input FANIN 0~15 */ 768 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 769 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md)); 770 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 771 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md)); 772 773 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) { 774 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i; 775 data->fan_dev[ch].fan_st_flg = FAN_DISABLE; 776 data->fan_dev[ch].fan_pls_per_rev = 777 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION; 778 data->fan_dev[ch].fan_cnt = 0; 779 } 780 } 781 782 apb_clk_freq = clk_get_rate(data->fan_clk); 783 784 /* Fan tach input clock = APB clock / prescalar, default is 255. */ 785 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1); 786} 787 788static int 789npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 790 unsigned long *state) 791{ 792 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 793 794 *state = cdev->max_state; 795 796 return 0; 797} 798 799static int 800npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 801 unsigned long *state) 802{ 803 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 804 805 *state = cdev->cur_state; 806 807 return 0; 808} 809 810static int 811npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 812 unsigned long state) 813{ 814 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 815 int ret; 816 817 if (state > cdev->max_state) 818 return -EINVAL; 819 820 cdev->cur_state = state; 821 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port, 822 cdev->cooling_levels[cdev->cur_state]); 823 824 return ret; 825} 826 827static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = { 828 .get_max_state = npcm7xx_pwm_cz_get_max_state, 829 .get_cur_state = npcm7xx_pwm_cz_get_cur_state, 830 .set_cur_state = npcm7xx_pwm_cz_set_cur_state, 831}; 832 833static int npcm7xx_create_pwm_cooling(struct device *dev, 834 struct device_node *child, 835 struct npcm7xx_pwm_fan_data *data, 836 u32 pwm_port, u8 num_levels) 837{ 838 int ret; 839 struct npcm7xx_cooling_device *cdev; 840 841 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 842 if (!cdev) 843 return -ENOMEM; 844 845 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 846 if (!cdev->cooling_levels) 847 return -ENOMEM; 848 849 cdev->max_state = num_levels - 1; 850 ret = of_property_read_u8_array(child, "cooling-levels", 851 cdev->cooling_levels, 852 num_levels); 853 if (ret) { 854 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 855 return ret; 856 } 857 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child, 858 pwm_port); 859 860 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 861 cdev->name, cdev, &npcm7xx_pwm_cool_ops); 862 if (IS_ERR(cdev->tcdev)) 863 return PTR_ERR(cdev->tcdev); 864 865 cdev->data = data; 866 cdev->pwm_port = pwm_port; 867 868 data->cdev[pwm_port] = cdev; 869 870 return 0; 871} 872 873static int npcm7xx_en_pwm_fan(struct device *dev, 874 struct device_node *child, 875 struct npcm7xx_pwm_fan_data *data) 876{ 877 u8 *fan_ch; 878 u32 pwm_port; 879 int ret, fan_cnt; 880 u8 index, ch; 881 882 ret = of_property_read_u32(child, "reg", &pwm_port); 883 if (ret) 884 return ret; 885 886 data->pwm_present[pwm_port] = true; 887 ret = npcm7xx_pwm_config_set(data, pwm_port, 888 NPCM7XX_PWM_CMR_DEFAULT_NUM); 889 if (ret) 890 return ret; 891 892 ret = of_property_count_u8_elems(child, "cooling-levels"); 893 if (ret > 0) { 894 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port, 895 ret); 896 if (ret) 897 return ret; 898 } 899 900 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch"); 901 if (fan_cnt < 1) 902 return -EINVAL; 903 904 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL); 905 if (!fan_ch) 906 return -ENOMEM; 907 908 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt); 909 if (ret) 910 return ret; 911 912 for (ch = 0; ch < fan_cnt; ch++) { 913 index = fan_ch[ch]; 914 data->fan_present[index] = true; 915 data->fan_dev[index].fan_st_flg = FAN_INIT; 916 } 917 918 return 0; 919} 920 921static int npcm7xx_pwm_fan_probe(struct platform_device *pdev) 922{ 923 struct device *dev = &pdev->dev; 924 struct device_node *np; 925 struct npcm7xx_pwm_fan_data *data; 926 struct resource *res; 927 struct device *hwmon; 928 char name[20]; 929 u32 output_freq; 930 int ret; 931 u32 i; 932 933 np = dev->of_node; 934 935 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 936 if (!data) 937 return -ENOMEM; 938 939 data->info = device_get_match_data(dev); 940 if (!data->info) 941 return -EINVAL; 942 943 data->pwm_modules = data->info->pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; 944 945 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); 946 if (!res) { 947 dev_err(dev, "pwm resource not found\n"); 948 return -ENODEV; 949 } 950 951 data->pwm_base = devm_ioremap_resource(dev, res); 952 dev_dbg(dev, "pwm base resource is %pR\n", res); 953 if (IS_ERR(data->pwm_base)) 954 return PTR_ERR(data->pwm_base); 955 956 data->pwm_clk = devm_clk_get(dev, "pwm"); 957 if (IS_ERR(data->pwm_clk)) { 958 dev_err(dev, "couldn't get pwm clock\n"); 959 return PTR_ERR(data->pwm_clk); 960 } 961 962 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan"); 963 if (!res) { 964 dev_err(dev, "fan resource not found\n"); 965 return -ENODEV; 966 } 967 968 data->fan_base = devm_ioremap_resource(dev, res); 969 dev_dbg(dev, "fan base resource is %pR\n", res); 970 if (IS_ERR(data->fan_base)) 971 return PTR_ERR(data->fan_base); 972 973 data->fan_clk = devm_clk_get(dev, "fan"); 974 if (IS_ERR(data->fan_clk)) { 975 dev_err(dev, "couldn't get fan clock\n"); 976 return PTR_ERR(data->fan_clk); 977 } 978 979 output_freq = npcm7xx_pwm_init(data); 980 npcm7xx_fan_init(data); 981 982 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) { 983 spin_lock_init(&data->fan_lock[i]); 984 985 data->fan_irq[i] = platform_get_irq(pdev, i); 986 if (data->fan_irq[i] < 0) 987 return data->fan_irq[i]; 988 989 sprintf(name, "NPCM7XX-FAN-MD%d", i); 990 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr, 991 0, name, (void *)data); 992 if (ret) { 993 dev_err(dev, "register IRQ fan%d failed\n", i); 994 return ret; 995 } 996 } 997 998 for_each_child_of_node_scoped(np, child) { 999 ret = npcm7xx_en_pwm_fan(dev, child, data); 1000 if (ret) { 1001 dev_err(dev, "enable pwm and fan failed\n"); 1002 return ret; 1003 } 1004 } 1005 1006 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan", 1007 data, &npcm7xx_chip_info, 1008 NULL); 1009 if (IS_ERR(hwmon)) { 1010 dev_err(dev, "unable to register hwmon device\n"); 1011 return PTR_ERR(hwmon); 1012 } 1013 1014 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) { 1015 if (data->fan_present[i]) { 1016 /* fan timer initialization */ 1017 data->fan_timer.expires = jiffies + 1018 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 1019 timer_setup(&data->fan_timer, 1020 npcm7xx_fan_polling, 0); 1021 add_timer(&data->fan_timer); 1022 break; 1023 } 1024 } 1025 1026 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n", 1027 output_freq, data->input_clk_freq); 1028 1029 return 0; 1030} 1031 1032static const struct of_device_id of_pwm_fan_match_table[] = { 1033 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info}, 1034 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info}, 1035 {}, 1036}; 1037MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table); 1038 1039static struct platform_driver npcm7xx_pwm_fan_driver = { 1040 .probe = npcm7xx_pwm_fan_probe, 1041 .driver = { 1042 .name = "npcm7xx_pwm_fan", 1043 .of_match_table = of_pwm_fan_match_table, 1044 }, 1045}; 1046 1047module_platform_driver(npcm7xx_pwm_fan_driver); 1048 1049MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver"); 1050MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 1051MODULE_LICENSE("GPL v2");
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