max31827.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * max31827.c - Support for Maxim Low-Power Switch
  4 *
  5 * Copyright (c) 2023 Daniel Matyas <daniel.matyas@analog.com>
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/bitops.h>
 10#include <linux/delay.h>
 11#include <linux/hwmon.h>
 12#include <linux/i2c.h>
 13#include <linux/of_device.h>
 14#include <linux/regmap.h>
 15#include <linux/regulator/consumer.h>
 16
 17#define MAX31827_T_REG			0x0
 18#define MAX31827_CONFIGURATION_REG	0x2
 19#define MAX31827_TH_REG			0x4
 20#define MAX31827_TL_REG			0x6
 21#define MAX31827_TH_HYST_REG		0x8
 22#define MAX31827_TL_HYST_REG		0xA
 23
 24#define MAX31827_CONFIGURATION_1SHOT_MASK	BIT(0)
 25#define MAX31827_CONFIGURATION_CNV_RATE_MASK	GENMASK(3, 1)
 26#define MAX31827_CONFIGURATION_PEC_EN_MASK	BIT(4)
 27#define MAX31827_CONFIGURATION_TIMEOUT_MASK	BIT(5)
 28#define MAX31827_CONFIGURATION_RESOLUTION_MASK	GENMASK(7, 6)
 29#define MAX31827_CONFIGURATION_ALRM_POL_MASK	BIT(8)
 30#define MAX31827_CONFIGURATION_COMP_INT_MASK	BIT(9)
 31#define MAX31827_CONFIGURATION_FLT_Q_MASK	GENMASK(11, 10)
 32#define MAX31827_CONFIGURATION_U_TEMP_STAT_MASK	BIT(14)
 33#define MAX31827_CONFIGURATION_O_TEMP_STAT_MASK	BIT(15)
 34
 35#define MAX31827_ALRM_POL_LOW	0x0
 36#define MAX31827_ALRM_POL_HIGH	0x1
 37#define MAX31827_FLT_Q_1	0x0
 38#define MAX31827_FLT_Q_4	0x2
 39
 40#define MAX31827_8_BIT_CNV_TIME		9
 41#define MAX31827_9_BIT_CNV_TIME		18
 42#define MAX31827_10_BIT_CNV_TIME	35
 43#define MAX31827_12_BIT_CNV_TIME	140
 44
 45#define MAX31827_16_BIT_TO_M_DGR(x)	(sign_extend32(x, 15) * 1000 / 16)
 46#define MAX31827_M_DGR_TO_16_BIT(x)	(((x) << 4) / 1000)
 47#define MAX31827_DEVICE_ENABLE(x)	((x) ? 0xA : 0x0)
 48
 49/*
 50 * The enum passed in the .data pointer of struct of_device_id must
 51 * start with a value != 0 since that is a requirement for using
 52 * device_get_match_data().
 53 */
 54enum chips { max31827 = 1, max31828, max31829 };
 55
 56enum max31827_cnv {
 57	MAX31827_CNV_1_DIV_64_HZ = 1,
 58	MAX31827_CNV_1_DIV_32_HZ,
 59	MAX31827_CNV_1_DIV_16_HZ,
 60	MAX31827_CNV_1_DIV_4_HZ,
 61	MAX31827_CNV_1_HZ,
 62	MAX31827_CNV_4_HZ,
 63	MAX31827_CNV_8_HZ,
 64};
 65
 66static const u16 max31827_conversions[] = {
 67	[MAX31827_CNV_1_DIV_64_HZ] = 64000,
 68	[MAX31827_CNV_1_DIV_32_HZ] = 32000,
 69	[MAX31827_CNV_1_DIV_16_HZ] = 16000,
 70	[MAX31827_CNV_1_DIV_4_HZ] = 4000,
 71	[MAX31827_CNV_1_HZ] = 1000,
 72	[MAX31827_CNV_4_HZ] = 250,
 73	[MAX31827_CNV_8_HZ] = 125,
 74};
 75
 76enum max31827_resolution {
 77	MAX31827_RES_8_BIT = 0,
 78	MAX31827_RES_9_BIT,
 79	MAX31827_RES_10_BIT,
 80	MAX31827_RES_12_BIT,
 81};
 82
 83static const u16 max31827_resolutions[] = {
 84	[MAX31827_RES_8_BIT] = 1000,
 85	[MAX31827_RES_9_BIT] = 500,
 86	[MAX31827_RES_10_BIT] = 250,
 87	[MAX31827_RES_12_BIT] = 62,
 88};
 89
 90static const u16 max31827_conv_times[] = {
 91	[MAX31827_RES_8_BIT] = MAX31827_8_BIT_CNV_TIME,
 92	[MAX31827_RES_9_BIT] = MAX31827_9_BIT_CNV_TIME,
 93	[MAX31827_RES_10_BIT] = MAX31827_10_BIT_CNV_TIME,
 94	[MAX31827_RES_12_BIT] = MAX31827_12_BIT_CNV_TIME,
 95};
 96
 97struct max31827_state {
 98	/*
 99	 * Prevent simultaneous access to the i2c client.
100	 */
101	struct regmap *regmap;
102	bool enable;
103	unsigned int resolution;
104	unsigned int update_interval;
105};
106
107static const struct regmap_config max31827_regmap = {
108	.reg_bits = 8,
109	.val_bits = 16,
110	.max_register = 0xA,
111};
112
113static int shutdown_write(struct max31827_state *st, unsigned int reg,
114			  unsigned int mask, unsigned int val)
115{
116	unsigned int cfg;
117	unsigned int cnv_rate;
118	int ret;
119
120	/*
121	 * Before the Temperature Threshold Alarm, Alarm Hysteresis Threshold
122	 * and Resolution bits from Configuration register are changed over I2C,
123	 * the part must be in shutdown mode.
124	 */
125	if (!st->enable) {
126		if (!mask)
127			return regmap_write(st->regmap, reg, val);
128		return regmap_update_bits(st->regmap, reg, mask, val);
129	}
130
131	ret = regmap_read(st->regmap, MAX31827_CONFIGURATION_REG, &cfg);
132	if (ret)
133		return ret;
134
135	cnv_rate = MAX31827_CONFIGURATION_CNV_RATE_MASK & cfg;
136	cfg = cfg & ~(MAX31827_CONFIGURATION_1SHOT_MASK |
137		      MAX31827_CONFIGURATION_CNV_RATE_MASK);
138	ret = regmap_write(st->regmap, MAX31827_CONFIGURATION_REG, cfg);
139	if (ret)
140		return ret;
141
142	if (!mask)
143		ret = regmap_write(st->regmap, reg, val);
144	else
145		ret = regmap_update_bits(st->regmap, reg, mask, val);
146
147	if (ret)
148		return ret;
149
150	return regmap_update_bits(st->regmap, MAX31827_CONFIGURATION_REG,
151				  MAX31827_CONFIGURATION_CNV_RATE_MASK,
152				  cnv_rate);
153}
154
155static int write_alarm_val(struct max31827_state *st, unsigned int reg,
156			   long val)
157{
158	val = MAX31827_M_DGR_TO_16_BIT(val);
159
160	return shutdown_write(st, reg, 0, val);
161}
162
163static umode_t max31827_is_visible(const void *state,
164				   enum hwmon_sensor_types type, u32 attr,
165				   int channel)
166{
167	if (type == hwmon_temp) {
168		switch (attr) {
169		case hwmon_temp_enable:
170		case hwmon_temp_max:
171		case hwmon_temp_min:
172		case hwmon_temp_max_hyst:
173		case hwmon_temp_min_hyst:
174			return 0644;
175		case hwmon_temp_input:
176		case hwmon_temp_min_alarm:
177		case hwmon_temp_max_alarm:
178			return 0444;
179		default:
180			return 0;
181		}
182	} else if (type == hwmon_chip) {
183		if (attr == hwmon_chip_update_interval)
184			return 0644;
185	}
186
187	return 0;
188}
189
190static int max31827_read(struct device *dev, enum hwmon_sensor_types type,
191			 u32 attr, int channel, long *val)
192{
193	struct max31827_state *st = dev_get_drvdata(dev);
194	unsigned int uval;
195	int ret = 0;
196
197	switch (type) {
198	case hwmon_temp:
199		switch (attr) {
200		case hwmon_temp_enable:
201			ret = regmap_read(st->regmap,
202					  MAX31827_CONFIGURATION_REG, &uval);
203			if (ret)
204				break;
205
206			uval = FIELD_GET(MAX31827_CONFIGURATION_1SHOT_MASK |
207					 MAX31827_CONFIGURATION_CNV_RATE_MASK,
208					 uval);
209			*val = !!uval;
210
211			break;
212		case hwmon_temp_input:
213			if (!st->enable) {
214				ret = regmap_update_bits(st->regmap,
215							 MAX31827_CONFIGURATION_REG,
216							 MAX31827_CONFIGURATION_1SHOT_MASK,
217							 1);
218				if (ret)
219					return ret;
220				msleep(max31827_conv_times[st->resolution]);
221			}
222
223			/*
224			 * For 12-bit resolution the conversion time is 140 ms,
225			 * thus an additional 15 ms is needed to complete the
226			 * conversion: 125 ms + 15 ms = 140 ms
227			 */
228			if (max31827_resolutions[st->resolution] == 12 &&
229			    st->update_interval == 125)
230				usleep_range(15000, 20000);
231
232			ret = regmap_read(st->regmap, MAX31827_T_REG, &uval);
233
234			if (ret)
235				break;
236
237			*val = MAX31827_16_BIT_TO_M_DGR(uval);
238
239			break;
240		case hwmon_temp_max:
241			ret = regmap_read(st->regmap, MAX31827_TH_REG, &uval);
242			if (ret)
243				break;
244
245			*val = MAX31827_16_BIT_TO_M_DGR(uval);
246			break;
247		case hwmon_temp_max_hyst:
248			ret = regmap_read(st->regmap, MAX31827_TH_HYST_REG,
249					  &uval);
250			if (ret)
251				break;
252
253			*val = MAX31827_16_BIT_TO_M_DGR(uval);
254			break;
255		case hwmon_temp_max_alarm:
256			ret = regmap_read(st->regmap,
257					  MAX31827_CONFIGURATION_REG, &uval);
258			if (ret)
259				break;
260
261			*val = FIELD_GET(MAX31827_CONFIGURATION_O_TEMP_STAT_MASK,
262					 uval);
263			break;
264		case hwmon_temp_min:
265			ret = regmap_read(st->regmap, MAX31827_TL_REG, &uval);
266			if (ret)
267				break;
268
269			*val = MAX31827_16_BIT_TO_M_DGR(uval);
270			break;
271		case hwmon_temp_min_hyst:
272			ret = regmap_read(st->regmap, MAX31827_TL_HYST_REG,
273					  &uval);
274			if (ret)
275				break;
276
277			*val = MAX31827_16_BIT_TO_M_DGR(uval);
278			break;
279		case hwmon_temp_min_alarm:
280			ret = regmap_read(st->regmap,
281					  MAX31827_CONFIGURATION_REG, &uval);
282			if (ret)
283				break;
284
285			*val = FIELD_GET(MAX31827_CONFIGURATION_U_TEMP_STAT_MASK,
286					 uval);
287			break;
288		default:
289			ret = -EOPNOTSUPP;
290			break;
291		}
292
293		break;
294
295	case hwmon_chip:
296		if (attr == hwmon_chip_update_interval) {
297			ret = regmap_read(st->regmap,
298					  MAX31827_CONFIGURATION_REG, &uval);
299			if (ret)
300				break;
301
302			uval = FIELD_GET(MAX31827_CONFIGURATION_CNV_RATE_MASK,
303					 uval);
304			*val = max31827_conversions[uval];
305		}
306		break;
307
308	default:
309		ret = -EOPNOTSUPP;
310		break;
311	}
312
313	return ret;
314}
315
316static int max31827_write(struct device *dev, enum hwmon_sensor_types type,
317			  u32 attr, int channel, long val)
318{
319	struct max31827_state *st = dev_get_drvdata(dev);
320	int res = 1;
321	int ret;
322
323	switch (type) {
324	case hwmon_temp:
325		switch (attr) {
326		case hwmon_temp_enable:
327			if (val >> 1)
328				return -EINVAL;
329
330			/**
331			 * The chip should not be enabled while a conversion is
332			 * performed. Neither should the chip be enabled when
333			 * the alarm values are changed.
334			 */
335
336			st->enable = val;
337
338			return regmap_update_bits(st->regmap,
339						  MAX31827_CONFIGURATION_REG,
340						  MAX31827_CONFIGURATION_1SHOT_MASK |
341						  MAX31827_CONFIGURATION_CNV_RATE_MASK,
342						  MAX31827_DEVICE_ENABLE(val));
343
344		case hwmon_temp_max:
345			return write_alarm_val(st, MAX31827_TH_REG, val);
346
347		case hwmon_temp_max_hyst:
348			return write_alarm_val(st, MAX31827_TH_HYST_REG, val);
349
350		case hwmon_temp_min:
351			return write_alarm_val(st, MAX31827_TL_REG, val);
352
353		case hwmon_temp_min_hyst:
354			return write_alarm_val(st, MAX31827_TL_HYST_REG, val);
355
356		default:
357			return -EOPNOTSUPP;
358		}
359
360	case hwmon_chip:
361		switch (attr) {
362		case hwmon_chip_update_interval:
363			if (!st->enable)
364				return -EINVAL;
365
366			/*
367			 * Convert the desired conversion rate into register
368			 * bits. res is already initialized with 1.
369			 *
370			 * This was inspired by lm73 driver.
371			 */
372			while (res < ARRAY_SIZE(max31827_conversions) &&
373			       val < max31827_conversions[res])
374				res++;
375
376			if (res == ARRAY_SIZE(max31827_conversions))
377				res = ARRAY_SIZE(max31827_conversions) - 1;
378
379			res = FIELD_PREP(MAX31827_CONFIGURATION_CNV_RATE_MASK,
380					 res);
381
382			ret = regmap_update_bits(st->regmap,
383						 MAX31827_CONFIGURATION_REG,
384						 MAX31827_CONFIGURATION_CNV_RATE_MASK,
385						 res);
386			if (ret)
387				return ret;
388
389			st->update_interval = val;
390
391			return 0;
392		case hwmon_chip_pec:
393			return regmap_update_bits(st->regmap, MAX31827_CONFIGURATION_REG,
394						  MAX31827_CONFIGURATION_PEC_EN_MASK,
395						  val ? MAX31827_CONFIGURATION_PEC_EN_MASK : 0);
396		default:
397			return -EOPNOTSUPP;
398		}
399	default:
400		return -EOPNOTSUPP;
401	}
402}
403
404static ssize_t temp1_resolution_show(struct device *dev,
405				     struct device_attribute *devattr,
406				     char *buf)
407{
408	struct max31827_state *st = dev_get_drvdata(dev);
409	unsigned int val;
410	int ret;
411
412	ret = regmap_read(st->regmap, MAX31827_CONFIGURATION_REG, &val);
413	if (ret)
414		return ret;
415
416	val = FIELD_GET(MAX31827_CONFIGURATION_RESOLUTION_MASK, val);
417
418	return sysfs_emit(buf, "%u\n", max31827_resolutions[val]);
419}
420
421static ssize_t temp1_resolution_store(struct device *dev,
422				      struct device_attribute *devattr,
423				      const char *buf, size_t count)
424{
425	struct max31827_state *st = dev_get_drvdata(dev);
426	unsigned int idx = 0;
427	unsigned int val;
428	int ret;
429
430	ret = kstrtouint(buf, 10, &val);
431	if (ret)
432		return ret;
433
434	/*
435	 * Convert the desired resolution into register
436	 * bits. idx is already initialized with 0.
437	 *
438	 * This was inspired by lm73 driver.
439	 */
440	while (idx < ARRAY_SIZE(max31827_resolutions) &&
441	       val < max31827_resolutions[idx])
442		idx++;
443
444	if (idx == ARRAY_SIZE(max31827_resolutions))
445		idx = ARRAY_SIZE(max31827_resolutions) - 1;
446
447	st->resolution = idx;
448
449	ret = shutdown_write(st, MAX31827_CONFIGURATION_REG,
450			     MAX31827_CONFIGURATION_RESOLUTION_MASK,
451			     FIELD_PREP(MAX31827_CONFIGURATION_RESOLUTION_MASK,
452					idx));
453
454	return ret ? ret : count;
455}
456
457static DEVICE_ATTR_RW(temp1_resolution);
458
459static struct attribute *max31827_attrs[] = {
460	&dev_attr_temp1_resolution.attr,
461	NULL
462};
463ATTRIBUTE_GROUPS(max31827);
464
465static const struct i2c_device_id max31827_i2c_ids[] = {
466	{ "max31827", max31827 },
467	{ "max31828", max31828 },
468	{ "max31829", max31829 },
469	{ }
470};
471MODULE_DEVICE_TABLE(i2c, max31827_i2c_ids);
472
473static int max31827_init_client(struct max31827_state *st,
474				struct device *dev)
475{
476	struct fwnode_handle *fwnode;
477	unsigned int res = 0;
478	u32 data, lsb_idx;
479	enum chips type;
480	bool prop;
481	int ret;
482
483	fwnode = dev_fwnode(dev);
484
485	st->enable = true;
486	res |= MAX31827_DEVICE_ENABLE(1);
487
488	res |= MAX31827_CONFIGURATION_RESOLUTION_MASK;
489
490	prop = fwnode_property_read_bool(fwnode, "adi,comp-int");
491	res |= FIELD_PREP(MAX31827_CONFIGURATION_COMP_INT_MASK, prop);
492
493	prop = fwnode_property_read_bool(fwnode, "adi,timeout-enable");
494	res |= FIELD_PREP(MAX31827_CONFIGURATION_TIMEOUT_MASK, !prop);
495
496	type = (enum chips)(uintptr_t)device_get_match_data(dev);
497
498	if (fwnode_property_present(fwnode, "adi,alarm-pol")) {
499		ret = fwnode_property_read_u32(fwnode, "adi,alarm-pol", &data);
500		if (ret)
501			return ret;
502
503		res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK, !!data);
504	} else {
505		/*
506		 * Set default value.
507		 */
508		switch (type) {
509		case max31827:
510		case max31828:
511			res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,
512					  MAX31827_ALRM_POL_LOW);
513			break;
514		case max31829:
515			res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,
516					  MAX31827_ALRM_POL_HIGH);
517			break;
518		default:
519			return -EOPNOTSUPP;
520		}
521	}
522
523	if (fwnode_property_present(fwnode, "adi,fault-q")) {
524		ret = fwnode_property_read_u32(fwnode, "adi,fault-q", &data);
525		if (ret)
526			return ret;
527
528		/*
529		 * Convert the desired fault queue into register bits.
530		 */
531		if (data != 0)
532			lsb_idx = __ffs(data);
533
534		if (hweight32(data) != 1 || lsb_idx > 4) {
535			dev_err(dev, "Invalid data in adi,fault-q\n");
536			return -EINVAL;
537		}
538
539		res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK, lsb_idx);
540	} else {
541		/*
542		 * Set default value.
543		 */
544		switch (type) {
545		case max31827:
546			res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,
547					  MAX31827_FLT_Q_1);
548			break;
549		case max31828:
550		case max31829:
551			res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,
552					  MAX31827_FLT_Q_4);
553			break;
554		default:
555			return -EOPNOTSUPP;
556		}
557	}
558
559	return regmap_write(st->regmap, MAX31827_CONFIGURATION_REG, res);
560}
561
562static const struct hwmon_channel_info *max31827_info[] = {
563	HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT | HWMON_T_MIN |
564					 HWMON_T_MIN_HYST | HWMON_T_MIN_ALARM |
565					 HWMON_T_MAX | HWMON_T_MAX_HYST |
566					 HWMON_T_MAX_ALARM),
567	HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL | HWMON_C_PEC),
568	NULL,
569};
570
571static const struct hwmon_ops max31827_hwmon_ops = {
572	.is_visible = max31827_is_visible,
573	.read = max31827_read,
574	.write = max31827_write,
575};
576
577static const struct hwmon_chip_info max31827_chip_info = {
578	.ops = &max31827_hwmon_ops,
579	.info = max31827_info,
580};
581
582static int max31827_probe(struct i2c_client *client)
583{
584	struct device *dev = &client->dev;
585	struct device *hwmon_dev;
586	struct max31827_state *st;
587	int err;
588
589	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
590		return -EOPNOTSUPP;
591
592	st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
593	if (!st)
594		return -ENOMEM;
595
596	st->regmap = devm_regmap_init_i2c(client, &max31827_regmap);
597	if (IS_ERR(st->regmap))
598		return dev_err_probe(dev, PTR_ERR(st->regmap),
599				     "Failed to allocate regmap.\n");
600
601	err = devm_regulator_get_enable(dev, "vref");
602	if (err)
603		return dev_err_probe(dev, err, "failed to enable regulator\n");
604
605	err = max31827_init_client(st, dev);
606	if (err)
607		return err;
608
609	hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, st,
610							 &max31827_chip_info,
611							 max31827_groups);
612
613	return PTR_ERR_OR_ZERO(hwmon_dev);
614}
615
616static const struct of_device_id max31827_of_match[] = {
617	{
618		.compatible = "adi,max31827",
619		.data = (void *)max31827
620	},
621	{
622		.compatible = "adi,max31828",
623		.data = (void *)max31828
624	},
625	{
626		.compatible = "adi,max31829",
627		.data = (void *)max31829
628	},
629	{ }
630};
631MODULE_DEVICE_TABLE(of, max31827_of_match);
632
633static struct i2c_driver max31827_driver = {
634	.driver = {
635		.name = "max31827",
636		.of_match_table = max31827_of_match,
637	},
638	.probe = max31827_probe,
639	.id_table = max31827_i2c_ids,
640};
641module_i2c_driver(max31827_driver);
642
643MODULE_AUTHOR("Daniel Matyas <daniel.matyas@analog.com>");
644MODULE_DESCRIPTION("Maxim MAX31827 low-power temperature switch driver");
645MODULE_LICENSE("GPL");