ltc2992.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2/*
  3 * LTC2992 - Dual Wide Range Power Monitor
  4 *
  5 * Copyright 2020 Analog Devices Inc.
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/bitops.h>
 10#include <linux/err.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/hwmon.h>
 13#include <linux/i2c.h>
 14#include <linux/kernel.h>
 15#include <linux/module.h>
 16#include <linux/property.h>
 17#include <linux/regmap.h>
 18
 19#define LTC2992_CTRLB			0x01
 20#define LTC2992_FAULT1			0x03
 21#define LTC2992_POWER1			0x05
 22#define LTC2992_POWER1_MAX		0x08
 23#define LTC2992_POWER1_MIN		0x0B
 24#define LTC2992_POWER1_MAX_THRESH	0x0E
 25#define LTC2992_POWER1_MIN_THRESH	0x11
 26#define LTC2992_DSENSE1			0x14
 27#define LTC2992_DSENSE1_MAX		0x16
 28#define LTC2992_DSENSE1_MIN		0x18
 29#define LTC2992_DSENSE1_MAX_THRESH	0x1A
 30#define LTC2992_DSENSE1_MIN_THRESH	0x1C
 31#define LTC2992_SENSE1			0x1E
 32#define LTC2992_SENSE1_MAX		0x20
 33#define LTC2992_SENSE1_MIN		0x22
 34#define LTC2992_SENSE1_MAX_THRESH	0x24
 35#define LTC2992_SENSE1_MIN_THRESH	0x26
 36#define LTC2992_G1			0x28
 37#define LTC2992_G1_MAX			0x2A
 38#define LTC2992_G1_MIN			0x2C
 39#define LTC2992_G1_MAX_THRESH		0x2E
 40#define LTC2992_G1_MIN_THRESH		0x30
 41#define LTC2992_FAULT2			0x35
 42#define LTC2992_G2			0x5A
 43#define LTC2992_G2_MAX			0x5C
 44#define LTC2992_G2_MIN			0x5E
 45#define LTC2992_G2_MAX_THRESH		0x60
 46#define LTC2992_G2_MIN_THRESH		0x62
 47#define LTC2992_G3			0x64
 48#define LTC2992_G3_MAX			0x66
 49#define LTC2992_G3_MIN			0x68
 50#define LTC2992_G3_MAX_THRESH		0x6A
 51#define LTC2992_G3_MIN_THRESH		0x6C
 52#define LTC2992_G4			0x6E
 53#define LTC2992_G4_MAX			0x70
 54#define LTC2992_G4_MIN			0x72
 55#define LTC2992_G4_MAX_THRESH		0x74
 56#define LTC2992_G4_MIN_THRESH		0x76
 57#define LTC2992_FAULT3			0x92
 58#define LTC2992_GPIO_STATUS		0x95
 59#define LTC2992_GPIO_IO_CTRL		0x96
 60#define LTC2992_GPIO_CTRL		0x97
 61
 62#define LTC2992_POWER(x)		(LTC2992_POWER1 + ((x) * 0x32))
 63#define LTC2992_POWER_MAX(x)		(LTC2992_POWER1_MAX + ((x) * 0x32))
 64#define LTC2992_POWER_MIN(x)		(LTC2992_POWER1_MIN + ((x) * 0x32))
 65#define LTC2992_POWER_MAX_THRESH(x)	(LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
 66#define LTC2992_POWER_MIN_THRESH(x)	(LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
 67#define LTC2992_DSENSE(x)		(LTC2992_DSENSE1 + ((x) * 0x32))
 68#define LTC2992_DSENSE_MAX(x)		(LTC2992_DSENSE1_MAX + ((x) * 0x32))
 69#define LTC2992_DSENSE_MIN(x)		(LTC2992_DSENSE1_MIN + ((x) * 0x32))
 70#define LTC2992_DSENSE_MAX_THRESH(x)	(LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
 71#define LTC2992_DSENSE_MIN_THRESH(x)	(LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
 72#define LTC2992_SENSE(x)		(LTC2992_SENSE1 + ((x) * 0x32))
 73#define LTC2992_SENSE_MAX(x)		(LTC2992_SENSE1_MAX + ((x) * 0x32))
 74#define LTC2992_SENSE_MIN(x)		(LTC2992_SENSE1_MIN + ((x) * 0x32))
 75#define LTC2992_SENSE_MAX_THRESH(x)	(LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
 76#define LTC2992_SENSE_MIN_THRESH(x)	(LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
 77#define LTC2992_POWER_FAULT(x)		(LTC2992_FAULT1 + ((x) * 0x32))
 78#define LTC2992_SENSE_FAULT(x)		(LTC2992_FAULT1 + ((x) * 0x32))
 79#define LTC2992_DSENSE_FAULT(x)		(LTC2992_FAULT1 + ((x) * 0x32))
 80
 81/* CTRLB register bitfields */
 82#define LTC2992_RESET_HISTORY		BIT(3)
 83
 84/* FAULT1 FAULT2 registers common bitfields */
 85#define LTC2992_POWER_FAULT_MSK(x)	(BIT(6) << (x))
 86#define LTC2992_DSENSE_FAULT_MSK(x)	(BIT(4) << (x))
 87#define LTC2992_SENSE_FAULT_MSK(x)	(BIT(2) << (x))
 88
 89/* FAULT1 bitfields */
 90#define LTC2992_GPIO1_FAULT_MSK(x)	(BIT(0) << (x))
 91
 92/* FAULT2 bitfields */
 93#define LTC2992_GPIO2_FAULT_MSK(x)	(BIT(0) << (x))
 94
 95/* FAULT3 bitfields */
 96#define LTC2992_GPIO3_FAULT_MSK(x)	(BIT(6) << (x))
 97#define LTC2992_GPIO4_FAULT_MSK(x)	(BIT(4) << (x))
 98
 99#define LTC2992_IADC_NANOV_LSB		12500
100#define LTC2992_VADC_UV_LSB		25000
101#define LTC2992_VADC_GPIO_UV_LSB	500
102
103#define LTC2992_GPIO_NR		4
104#define LTC2992_GPIO1_BIT	7
105#define LTC2992_GPIO2_BIT	6
106#define LTC2992_GPIO3_BIT	0
107#define LTC2992_GPIO4_BIT	6
108#define LTC2992_GPIO_BIT(x)	(LTC2992_GPIO_NR - (x) - 1)
109
110struct ltc2992_state {
111	struct i2c_client		*client;
112	struct gpio_chip		gc;
113	struct mutex			gpio_mutex; /* lock for gpio access */
114	const char			*gpio_names[LTC2992_GPIO_NR];
115	struct regmap			*regmap;
116	u32				r_sense_uohm[2];
117};
118
119struct ltc2992_gpio_regs {
120	u8	data;
121	u8	max;
122	u8	min;
123	u8	max_thresh;
124	u8	min_thresh;
125	u8	alarm;
126	u8	min_alarm_msk;
127	u8	max_alarm_msk;
128	u8	ctrl;
129	u8	ctrl_bit;
130};
131
132static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
133	{
134		.data = LTC2992_G1,
135		.max = LTC2992_G1_MAX,
136		.min = LTC2992_G1_MIN,
137		.max_thresh = LTC2992_G1_MAX_THRESH,
138		.min_thresh = LTC2992_G1_MIN_THRESH,
139		.alarm = LTC2992_FAULT1,
140		.min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
141		.max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
142		.ctrl = LTC2992_GPIO_IO_CTRL,
143		.ctrl_bit = LTC2992_GPIO1_BIT,
144	},
145	{
146		.data = LTC2992_G2,
147		.max = LTC2992_G2_MAX,
148		.min = LTC2992_G2_MIN,
149		.max_thresh = LTC2992_G2_MAX_THRESH,
150		.min_thresh = LTC2992_G2_MIN_THRESH,
151		.alarm = LTC2992_FAULT2,
152		.min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
153		.max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
154		.ctrl = LTC2992_GPIO_IO_CTRL,
155		.ctrl_bit = LTC2992_GPIO2_BIT,
156	},
157	{
158		.data = LTC2992_G3,
159		.max = LTC2992_G3_MAX,
160		.min = LTC2992_G3_MIN,
161		.max_thresh = LTC2992_G3_MAX_THRESH,
162		.min_thresh = LTC2992_G3_MIN_THRESH,
163		.alarm = LTC2992_FAULT3,
164		.min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
165		.max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
166		.ctrl = LTC2992_GPIO_IO_CTRL,
167		.ctrl_bit = LTC2992_GPIO3_BIT,
168	},
169	{
170		.data = LTC2992_G4,
171		.max = LTC2992_G4_MAX,
172		.min = LTC2992_G4_MIN,
173		.max_thresh = LTC2992_G4_MAX_THRESH,
174		.min_thresh = LTC2992_G4_MIN_THRESH,
175		.alarm = LTC2992_FAULT3,
176		.min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
177		.max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
178		.ctrl = LTC2992_GPIO_CTRL,
179		.ctrl_bit = LTC2992_GPIO4_BIT,
180	},
181};
182
183static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
184	"GPIO1", "GPIO2", "GPIO3", "GPIO4",
185};
186
187static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
188{
189	u8 regvals[4];
190	int val;
191	int ret;
192	int i;
193
194	ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
195	if (ret < 0)
196		return ret;
197
198	val = 0;
199	for (i = 0; i < reg_len; i++)
200		val |= regvals[reg_len - i - 1] << (i * 8);
201
202	return val;
203}
204
205static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
206{
207	u8 regvals[4];
208	int i;
209
210	for (i = 0; i < reg_len; i++)
211		regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
212
213	return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
214}
215
216static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
217{
218	struct ltc2992_state *st = gpiochip_get_data(chip);
219	unsigned long gpio_status;
220	int reg;
221
222	mutex_lock(&st->gpio_mutex);
223	reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
224	mutex_unlock(&st->gpio_mutex);
225
226	if (reg < 0)
227		return reg;
228
229	gpio_status = reg;
230
231	return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
232}
233
234static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
235				     unsigned long *bits)
236{
237	struct ltc2992_state *st = gpiochip_get_data(chip);
238	unsigned long gpio_status;
239	unsigned int gpio_nr;
240	int reg;
241
242	mutex_lock(&st->gpio_mutex);
243	reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
244	mutex_unlock(&st->gpio_mutex);
245
246	if (reg < 0)
247		return reg;
248
249	gpio_status = reg;
250
251	for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
252		if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
253			set_bit(gpio_nr, bits);
254	}
255
256	return 0;
257}
258
259static int ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset,
260			    int value)
261{
262	struct ltc2992_state *st = gpiochip_get_data(chip);
263	unsigned long gpio_ctrl;
264	int reg, ret;
265
266	mutex_lock(&st->gpio_mutex);
267	reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
268	if (reg < 0) {
269		mutex_unlock(&st->gpio_mutex);
270		return reg;
271	}
272
273	gpio_ctrl = reg;
274	assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
275
276	ret = ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1,
277				gpio_ctrl);
278	mutex_unlock(&st->gpio_mutex);
279
280	return ret;
281}
282
283static int ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
284				     unsigned long *bits)
285{
286	struct ltc2992_state *st = gpiochip_get_data(chip);
287	unsigned long gpio_ctrl_io = 0;
288	unsigned long gpio_ctrl = 0;
289	unsigned int gpio_nr;
290	int ret;
291
292	for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
293		if (gpio_nr < 3)
294			assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
295
296		if (gpio_nr == 3)
297			assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
298	}
299
300	mutex_lock(&st->gpio_mutex);
301	ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
302	if (ret)
303		goto out;
304
305	ret = ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
306out:
307	mutex_unlock(&st->gpio_mutex);
308	return ret;
309}
310
311static int ltc2992_config_gpio(struct ltc2992_state *st)
312{
313	const char *name = dev_name(&st->client->dev);
314	char *gpio_name;
315	int ret;
316	int i;
317
318	ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
319	if (ret < 0)
320		return ret;
321
322	mutex_init(&st->gpio_mutex);
323
324	for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
325		gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
326					   st->client->addr, ltc2992_gpio_names[i]);
327		if (!gpio_name)
328			return -ENOMEM;
329
330		st->gpio_names[i] = gpio_name;
331	}
332
333	st->gc.label = name;
334	st->gc.parent = &st->client->dev;
335	st->gc.owner = THIS_MODULE;
336	st->gc.can_sleep = true;
337	st->gc.base = -1;
338	st->gc.names = st->gpio_names;
339	st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
340	st->gc.get = ltc2992_gpio_get;
341	st->gc.get_multiple = ltc2992_gpio_get_multiple;
342	st->gc.set = ltc2992_gpio_set;
343	st->gc.set_multiple = ltc2992_gpio_set_multiple;
344
345	ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
346	if (ret)
347		dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
348
349	return ret;
350}
351
352static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
353				  int channel)
354{
355	const struct ltc2992_state *st = data;
356
357	switch (type) {
358	case hwmon_chip:
359		switch (attr) {
360		case hwmon_chip_in_reset_history:
361			return 0200;
362		}
363		break;
364	case hwmon_in:
365		switch (attr) {
366		case hwmon_in_input:
367		case hwmon_in_lowest:
368		case hwmon_in_highest:
369		case hwmon_in_min_alarm:
370		case hwmon_in_max_alarm:
371			return 0444;
372		case hwmon_in_min:
373		case hwmon_in_max:
374			return 0644;
375		}
376		break;
377	case hwmon_curr:
378		switch (attr) {
379		case hwmon_curr_input:
380		case hwmon_curr_lowest:
381		case hwmon_curr_highest:
382		case hwmon_curr_min_alarm:
383		case hwmon_curr_max_alarm:
384			if (st->r_sense_uohm[channel])
385				return 0444;
386			break;
387		case hwmon_curr_min:
388		case hwmon_curr_max:
389			if (st->r_sense_uohm[channel])
390				return 0644;
391			break;
392		}
393		break;
394	case hwmon_power:
395		switch (attr) {
396		case hwmon_power_input:
397		case hwmon_power_input_lowest:
398		case hwmon_power_input_highest:
399		case hwmon_power_min_alarm:
400		case hwmon_power_max_alarm:
401			if (st->r_sense_uohm[channel])
402				return 0444;
403			break;
404		case hwmon_power_min:
405		case hwmon_power_max:
406			if (st->r_sense_uohm[channel])
407				return 0644;
408			break;
409		}
410		break;
411	default:
412		break;
413	}
414
415	return 0;
416}
417
418static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
419{
420	int reg_val;
421
422	reg_val = ltc2992_read_reg(st, reg, 2);
423	if (reg_val < 0)
424		return reg_val;
425
426	reg_val = reg_val >> 4;
427	*val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
428
429	return 0;
430}
431
432static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
433{
434	val = DIV_ROUND_CLOSEST(val * 1000, scale);
435	val = val << 4;
436
437	return ltc2992_write_reg(st, reg, 2, val);
438}
439
440static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
441{
442	int reg_val;
443	u32 mask;
444
445	if (attr == hwmon_in_max_alarm)
446		mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
447	else
448		mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
449
450	reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
451	if (reg_val < 0)
452		return reg_val;
453
454	*val = !!(reg_val & mask);
455	reg_val &= ~mask;
456
457	return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
458}
459
460static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
461{
462	struct ltc2992_state *st = dev_get_drvdata(dev);
463	u32 reg;
464
465	switch (attr) {
466	case hwmon_in_input:
467		reg = ltc2992_gpio_addr_map[nr_gpio].data;
468		break;
469	case hwmon_in_lowest:
470		reg = ltc2992_gpio_addr_map[nr_gpio].min;
471		break;
472	case hwmon_in_highest:
473		reg = ltc2992_gpio_addr_map[nr_gpio].max;
474		break;
475	case hwmon_in_min:
476		reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
477		break;
478	case hwmon_in_max:
479		reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
480		break;
481	case hwmon_in_min_alarm:
482	case hwmon_in_max_alarm:
483		return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
484	default:
485		return -EOPNOTSUPP;
486	}
487
488	return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
489}
490
491static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
492{
493	int reg_val;
494	u32 mask;
495
496	if (attr == hwmon_in_max_alarm)
497		mask = LTC2992_SENSE_FAULT_MSK(1);
498	else
499		mask = LTC2992_SENSE_FAULT_MSK(0);
500
501	reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
502	if (reg_val < 0)
503		return reg_val;
504
505	*val = !!(reg_val & mask);
506	reg_val &= ~mask;
507
508	return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
509}
510
511static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
512{
513	struct ltc2992_state *st = dev_get_drvdata(dev);
514	u32 reg;
515
516	if (channel > 1)
517		return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
518
519	switch (attr) {
520	case hwmon_in_input:
521		reg = LTC2992_SENSE(channel);
522		break;
523	case hwmon_in_lowest:
524		reg = LTC2992_SENSE_MIN(channel);
525		break;
526	case hwmon_in_highest:
527		reg = LTC2992_SENSE_MAX(channel);
528		break;
529	case hwmon_in_min:
530		reg = LTC2992_SENSE_MIN_THRESH(channel);
531		break;
532	case hwmon_in_max:
533		reg = LTC2992_SENSE_MAX_THRESH(channel);
534		break;
535	case hwmon_in_min_alarm:
536	case hwmon_in_max_alarm:
537		return ltc2992_read_in_alarm(st, channel, val, attr);
538	default:
539		return -EOPNOTSUPP;
540	}
541
542	return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
543}
544
545static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
546{
547	int reg_val;
548
549	reg_val = ltc2992_read_reg(st, reg, 2);
550	if (reg_val < 0)
551		return reg_val;
552
553	reg_val = reg_val >> 4;
554	*val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
555
556	return 0;
557}
558
559static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
560{
561	u32 reg_val;
562
563	reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);
564	reg_val = reg_val << 4;
565
566	return ltc2992_write_reg(st, reg, 2, reg_val);
567}
568
569static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
570{
571	int reg_val;
572	u32 mask;
573
574	if (attr == hwmon_curr_max_alarm)
575		mask = LTC2992_DSENSE_FAULT_MSK(1);
576	else
577		mask = LTC2992_DSENSE_FAULT_MSK(0);
578
579	reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
580	if (reg_val < 0)
581		return reg_val;
582
583	*val = !!(reg_val & mask);
584
585	reg_val &= ~mask;
586	return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
587}
588
589static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
590{
591	struct ltc2992_state *st = dev_get_drvdata(dev);
592	u32 reg;
593
594	switch (attr) {
595	case hwmon_curr_input:
596		reg = LTC2992_DSENSE(channel);
597		break;
598	case hwmon_curr_lowest:
599		reg = LTC2992_DSENSE_MIN(channel);
600		break;
601	case hwmon_curr_highest:
602		reg = LTC2992_DSENSE_MAX(channel);
603		break;
604	case hwmon_curr_min:
605		reg = LTC2992_DSENSE_MIN_THRESH(channel);
606		break;
607	case hwmon_curr_max:
608		reg = LTC2992_DSENSE_MAX_THRESH(channel);
609		break;
610	case hwmon_curr_min_alarm:
611	case hwmon_curr_max_alarm:
612		return ltc2992_read_curr_alarm(st, channel, val, attr);
613	default:
614		return -EOPNOTSUPP;
615	}
616
617	return ltc2992_get_current(st, reg, channel, val);
618}
619
620static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
621{
622	int reg_val;
623
624	reg_val = ltc2992_read_reg(st, reg, 3);
625	if (reg_val < 0)
626		return reg_val;
627
628	*val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,
629			       st->r_sense_uohm[channel] * 1000);
630
631	return 0;
632}
633
634static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
635{
636	u32 reg_val;
637
638	reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,
639				  LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB);
640
641	return ltc2992_write_reg(st, reg, 3, reg_val);
642}
643
644static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
645{
646	int reg_val;
647	u32 mask;
648
649	if (attr == hwmon_power_max_alarm)
650		mask = LTC2992_POWER_FAULT_MSK(1);
651	else
652		mask = LTC2992_POWER_FAULT_MSK(0);
653
654	reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
655	if (reg_val < 0)
656		return reg_val;
657
658	*val = !!(reg_val & mask);
659	reg_val &= ~mask;
660
661	return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
662}
663
664static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
665{
666	struct ltc2992_state *st = dev_get_drvdata(dev);
667	u32 reg;
668
669	switch (attr) {
670	case hwmon_power_input:
671		reg = LTC2992_POWER(channel);
672		break;
673	case hwmon_power_input_lowest:
674		reg = LTC2992_POWER_MIN(channel);
675		break;
676	case hwmon_power_input_highest:
677		reg = LTC2992_POWER_MAX(channel);
678		break;
679	case hwmon_power_min:
680		reg = LTC2992_POWER_MIN_THRESH(channel);
681		break;
682	case hwmon_power_max:
683		reg = LTC2992_POWER_MAX_THRESH(channel);
684		break;
685	case hwmon_power_min_alarm:
686	case hwmon_power_max_alarm:
687		return ltc2992_read_power_alarm(st, channel, val, attr);
688	default:
689		return -EOPNOTSUPP;
690	}
691
692	return ltc2992_get_power(st, reg, channel, val);
693}
694
695static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
696			long *val)
697{
698	switch (type) {
699	case hwmon_in:
700		return ltc2992_read_in(dev, attr, channel, val);
701	case hwmon_curr:
702		return ltc2992_read_curr(dev, attr, channel, val);
703	case hwmon_power:
704		return ltc2992_read_power(dev, attr, channel, val);
705	default:
706		return -EOPNOTSUPP;
707	}
708}
709
710static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
711{
712	struct ltc2992_state *st = dev_get_drvdata(dev);
713	u32 reg;
714
715	switch (attr) {
716	case hwmon_curr_min:
717		reg = LTC2992_DSENSE_MIN_THRESH(channel);
718		break;
719	case hwmon_curr_max:
720		reg = LTC2992_DSENSE_MAX_THRESH(channel);
721		break;
722	default:
723		return -EOPNOTSUPP;
724	}
725
726	return ltc2992_set_current(st, reg, channel, val);
727}
728
729static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
730{
731	struct ltc2992_state *st = dev_get_drvdata(dev);
732	u32 reg;
733
734	switch (attr) {
735	case hwmon_in_min:
736		reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
737		break;
738	case hwmon_in_max:
739		reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
740		break;
741	default:
742		return -EOPNOTSUPP;
743	}
744
745	return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
746}
747
748static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
749{
750	struct ltc2992_state *st = dev_get_drvdata(dev);
751	u32 reg;
752
753	if (channel > 1)
754		return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
755
756	switch (attr) {
757	case hwmon_in_min:
758		reg = LTC2992_SENSE_MIN_THRESH(channel);
759		break;
760	case hwmon_in_max:
761		reg = LTC2992_SENSE_MAX_THRESH(channel);
762		break;
763	default:
764		return -EOPNOTSUPP;
765	}
766
767	return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
768}
769
770static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
771{
772	struct ltc2992_state *st = dev_get_drvdata(dev);
773	u32 reg;
774
775	switch (attr) {
776	case hwmon_power_min:
777		reg = LTC2992_POWER_MIN_THRESH(channel);
778		break;
779	case hwmon_power_max:
780		reg = LTC2992_POWER_MAX_THRESH(channel);
781		break;
782	default:
783		return -EOPNOTSUPP;
784	}
785
786	return ltc2992_set_power(st, reg, channel, val);
787}
788
789static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
790{
791	struct ltc2992_state *st = dev_get_drvdata(dev);
792
793	switch (attr) {
794	case hwmon_chip_in_reset_history:
795		return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
796					  LTC2992_RESET_HISTORY);
797	default:
798		return -EOPNOTSUPP;
799	}
800}
801
802static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
803			 long val)
804{
805	switch (type) {
806	case hwmon_chip:
807		return ltc2992_write_chip(dev, attr, channel, val);
808	case hwmon_in:
809		return ltc2992_write_in(dev, attr, channel, val);
810	case hwmon_curr:
811		return ltc2992_write_curr(dev, attr, channel, val);
812	case hwmon_power:
813		return ltc2992_write_power(dev, attr, channel, val);
814	default:
815		return -EOPNOTSUPP;
816	}
817}
818
819static const struct hwmon_ops ltc2992_hwmon_ops = {
820	.is_visible = ltc2992_is_visible,
821	.read = ltc2992_read,
822	.write = ltc2992_write,
823};
824
825static const struct hwmon_channel_info * const ltc2992_info[] = {
826	HWMON_CHANNEL_INFO(chip,
827			   HWMON_C_IN_RESET_HISTORY),
828	HWMON_CHANNEL_INFO(in,
829			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
830			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
831			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
832			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
833			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
834			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
835			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
836			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
837			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
838			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
839			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
840			   HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM),
841	HWMON_CHANNEL_INFO(curr,
842			   HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
843			   HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
844			   HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
845			   HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM),
846	HWMON_CHANNEL_INFO(power,
847			   HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
848			   HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
849			   HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
850			   HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM),
851	NULL
852};
853
854static const struct hwmon_chip_info ltc2992_chip_info = {
855	.ops = &ltc2992_hwmon_ops,
856	.info = ltc2992_info,
857};
858
859static const struct regmap_config ltc2992_regmap_config = {
860	.reg_bits = 8,
861	.val_bits = 8,
862	.max_register = 0xE8,
863};
864
865static int ltc2992_parse_dt(struct ltc2992_state *st)
866{
867	u32 addr;
868	u32 val;
869	int ret;
870
871	device_for_each_child_node_scoped(&st->client->dev, child) {
872		ret = fwnode_property_read_u32(child, "reg", &addr);
873		if (ret < 0)
874			return ret;
875
876		if (addr > 1)
877			return -EINVAL;
878
879		ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
880		if (!ret) {
881			if (!val)
882				return dev_err_probe(&st->client->dev, -EINVAL,
883						     "shunt resistor value cannot be zero\n");
884
885			st->r_sense_uohm[addr] = val;
886		}
887	}
888
889	return 0;
890}
891
892static int ltc2992_i2c_probe(struct i2c_client *client)
893{
894	struct device *hwmon_dev;
895	struct ltc2992_state *st;
896	int ret;
897
898	st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
899	if (!st)
900		return -ENOMEM;
901
902	st->client = client;
903	st->regmap = devm_regmap_init_i2c(client, &ltc2992_regmap_config);
904	if (IS_ERR(st->regmap))
905		return PTR_ERR(st->regmap);
906
907	ret = ltc2992_parse_dt(st);
908	if (ret < 0)
909		return ret;
910
911	ret = ltc2992_config_gpio(st);
912	if (ret < 0)
913		return ret;
914
915	hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
916							 &ltc2992_chip_info, NULL);
917
918	return PTR_ERR_OR_ZERO(hwmon_dev);
919}
920
921static const struct of_device_id ltc2992_of_match[] = {
922	{ .compatible = "adi,ltc2992" },
923	{ }
924};
925MODULE_DEVICE_TABLE(of, ltc2992_of_match);
926
927static const struct i2c_device_id ltc2992_i2c_id[] = {
928	{"ltc2992"},
929	{}
930};
931MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
932
933static struct i2c_driver ltc2992_i2c_driver = {
934	.driver = {
935		.name = "ltc2992",
936		.of_match_table = ltc2992_of_match,
937	},
938	.probe = ltc2992_i2c_probe,
939	.id_table = ltc2992_i2c_id,
940};
941
942module_i2c_driver(ltc2992_i2c_driver);
943
944MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
945MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
946MODULE_LICENSE("Dual BSD/GPL");