intel-thc-hw.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2024 Intel Corporation */
  3
  4#ifndef _INTEL_THC_HW_H_
  5#define _INTEL_THC_HW_H_
  6
  7#include <linux/bits.h>
  8
  9/* THC registers offset */
 10/* Touch Host Controller Control Register */
 11#define THC_M_PRT_CONTROL_OFFSET		0x1008
 12/* THC SPI Bus Configuration Register */
 13#define THC_M_PRT_SPI_CFG_OFFSET		0x1010
 14/* THC SPI Bus Read Opcode Register */
 15#define THC_M_PRT_SPI_ICRRD_OPCODE_OFFSET	0x1014
 16/* THC SPI Bus Read Opcode Register */
 17#define THC_M_PRT_SPI_DMARD_OPCODE_OFFSET	0x1018
 18/* THC SPI Bus Write Opcode Register */
 19#define THC_M_PRT_SPI_WR_OPCODE_OFFSET		0x101C
 20/* THC Interrupt Enable Register */
 21#define THC_M_PRT_INT_EN_OFFSET			0x1020
 22/* THC Interrupt Status Register */
 23#define THC_M_PRT_INT_STATUS_OFFSET		0x1024
 24/* THC Error Cause Register */
 25#define THC_M_PRT_ERR_CAUSE_OFFSET		0x1028
 26/* THC SW sequencing Control */
 27#define THC_M_PRT_SW_SEQ_CNTRL_OFFSET		0x1040
 28/* THC SW sequencing Status */
 29#define THC_M_PRT_SW_SEQ_STS_OFFSET		0x1044
 30/* THC SW Sequencing Data DW0 or SPI Address Register */
 31#define THC_M_PRT_SW_SEQ_DATA0_ADDR_OFFSET	0x1048
 32/* THC SW sequencing Data DW1 */
 33#define THC_M_PRT_SW_SEQ_DATA1_OFFSET		0x104C
 34/* THC SW sequencing Data DW2 */
 35#define THC_M_PRT_SW_SEQ_DATA2_OFFSET		0x1050
 36/* THC SW sequencing Data DW3 */
 37#define THC_M_PRT_SW_SEQ_DATA3_OFFSET		0x1054
 38/* THC SW sequencing Data DW4 */
 39#define THC_M_PRT_SW_SEQ_DATA4_OFFSET		0x1058
 40/* THC SW sequencing Data DW5 */
 41#define THC_M_PRT_SW_SEQ_DATA5_OFFSET		0x105C
 42/* THC SW sequencing Data DW6 */
 43#define THC_M_PRT_SW_SEQ_DATA6_OFFSET		0x1060
 44/* THC SW sequencing Data DW7 */
 45#define THC_M_PRT_SW_SEQ_DATA7_OFFSET		0x1064
 46/* THC SW sequencing Data DW8 */
 47#define THC_M_PRT_SW_SEQ_DATA8_OFFSET		0x1068
 48/* THC SW sequencing Data DW9 */
 49#define THC_M_PRT_SW_SEQ_DATA9_OFFSET		0x106C
 50/* THC SW sequencing Data DW10 */
 51#define THC_M_PRT_SW_SEQ_DATA10_OFFSET		0x1070
 52/* THC SW sequencing Data DW11 */
 53#define THC_M_PRT_SW_SEQ_DATA11_OFFSET		0x1074
 54/* THC SW sequencing Data DW12 */
 55#define THC_M_PRT_SW_SEQ_DATA12_OFFSET		0x1078
 56/* THC SW sequencing Data DW13 */
 57#define THC_M_PRT_SW_SEQ_DATA13_OFFSET		0x107C
 58/* THC SW sequencing Data DW14 */
 59#define THC_M_PRT_SW_SEQ_DATA14_OFFSET		0x1080
 60/* THC SW sequencing Data DW15 */
 61#define THC_M_PRT_SW_SEQ_DATA15_OFFSET		0x1084
 62/* THC SW sequencing Data DW16 */
 63#define THC_M_PRT_SW_SEQ_DATA16_OFFSET		0x1088
 64/* THC Write PRD Base Address Register Low */
 65#define THC_M_PRT_WPRD_BA_LOW_OFFSET		0x1090
 66/* THC Write PRD Base Address Register High */
 67#define THC_M_PRT_WPRD_BA_HI_OFFSET		0x1094
 68/* THC Write DMA Control */
 69#define THC_M_PRT_WRITE_DMA_CNTRL_OFFSET	0x1098
 70/* THC Write Interrupt Status */
 71#define THC_M_PRT_WRITE_INT_STS_OFFSET		0x109C
 72/* THC Write DMA Error Register */
 73#define THC_M_PRT_WRITE_DMA_ERR_OFFSET		0x10A0
 74/* THC device address for the bulk write */
 75#define THC_M_PRT_WR_BULK_ADDR_OFFSET		0x10B4
 76/* THC Device Interrupt Cause Register Address */
 77#define THC_M_PRT_DEV_INT_CAUSE_ADDR_OFFSET	0x10B8
 78/* THC Device Interrupt Cause Register Value */
 79#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_OFFSET	0x10BC
 80/* THC TXDMA Frame Count */
 81#define THC_M_PRT_TX_FRM_CNT_OFFSET		0x10E0
 82/* THC TXDMA Packet Count */
 83#define THC_M_PRT_TXDMA_PKT_CNT_OFFSET		0x10E4
 84/* THC Device Interrupt Count on this port */
 85#define THC_M_PRT_DEVINT_CNT_OFFSET		0x10E8
 86/* Touch Device Interrupt Cause register Format Configuration Register 1 */
 87#define THC_M_PRT_DEVINT_CFG_1_OFFSET		0x10EC
 88/* Touch Device Interrupt Cause register Format Configuration Register 2 */
 89#define THC_M_PRT_DEVINT_CFG_2_OFFSET		0x10F0
 90/* THC Read PRD Base Address Low for the 1st RXDMA */
 91#define THC_M_PRT_RPRD_BA_LOW_1_OFFSET		0x1100
 92/* THC Read PRD Base Address High for the 1st RXDMA */
 93#define THC_M_PRT_RPRD_BA_HI_1_OFFSET		0x1104
 94/* THC Read PRD Control for the 1st RXDMA */
 95#define THC_M_PRT_RPRD_CNTRL_1_OFFSET		0x1108
 96/* THC Read DMA Control for the 1st RXDMA */
 97#define THC_M_PRT_READ_DMA_CNTRL_1_OFFSET	0x110C
 98/* THC Read Interrupt Status for the 1st RXDMA */
 99#define THC_M_PRT_READ_DMA_INT_STS_1_OFFSET	0x1110
100/* THC Read DMA Error Register for the 1st RXDMA */
101#define THC_M_PRT_READ_DMA_ERR_1_OFFSET		0x1114
102/* Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA */
103#define THC_M_PRT_GUC_OFFSET_LOW_1_OFFSET	0x1118
104/* Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA */
105#define THC_M_PRT_GUC_OFFSET_HI_1_OFFSET	0x111C
106/* Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA */
107#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_1_OFFSET	0x1120
108/* Touch Host Controller GuC Control register for the 1st RXDMA */
109#define THC_M_PRT_GUC_WORKQ_SZ_1_OFFSET		0x1124
110/* Touch Sequencer Control for the 1st DMA */
111#define THC_M_PRT_TSEQ_CNTRL_1_OFFSET		0x1128
112/* Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA */
113#define THC_M_PRT_GUC_DB_ADDR_LOW_1_OFFSET	0x1130
114/* Touch Sequencer GuC Doorbell Address High for the 1st RXDMA */
115#define THC_M_PRT_GUC_DB_ADDR_HI_1_OFFSET	0x1134
116/* Touch Sequencer GuC Doorbell Data */
117#define THC_M_PRT_GUC_DB_DATA_1_OFFSET		0x1138
118/* Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA */
119#define THC_M_PRT_GUC_OFFSET_INITVAL_1_OFFSET	0x1140
120/* THC Device Address for the bulk/touch data read for the 1st RXDMA */
121#define THC_M_PRT_RD_BULK_ADDR_1_OFFSET		0x1170
122/* THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port */
123#define THC_M_PRT_DB_CNT_1_OFFSET		0x11A0
124/* THC Frame Count from the 1st Stream RXDMA on this port */
125#define THC_M_PRT_FRM_CNT_1_OFFSET		0x11A4
126/* THC Micro Frame Count from the 1st Stream RXDMA on this port */
127#define THC_M_PRT_UFRM_CNT_1_OFFSET		0x11A8
128/* THC Packet Count from the 1st Stream RXDMA on this port */
129#define THC_M_PRT_RXDMA_PKT_CNT_1_OFFSET	0x11AC
130/*
131 * THC Software Interrupt Count from the 1st Stream RXDMA
132 * on this port
133 */
134#define THC_M_PRT_SWINT_CNT_1_OFFSET		0x11B0
135/* Touch Sequencer Frame Drop Counter for the 1st RXDMA */
136#define THC_M_PRT_FRAME_DROP_CNT_1_OFFSET	0x11B4
137/* THC Coaescing 1 */
138#define THC_M_PRT_COALESCE_1_OFFSET		0x11B8
139/* THC Read PRD Base Address Low for the 2nd RXDMA */
140#define THC_M_PRT_RPRD_BA_LOW_2_OFFSET		0x1200
141/* THC Read PRD Base Address High for the 2nd RXDMA */
142#define THC_M_PRT_RPRD_BA_HI_2_OFFSET		0x1204
143/* THC Read PRD Control for the 2nd RXDMA */
144#define THC_M_PRT_RPRD_CNTRL_2_OFFSET		0x1208
145/* THC Read DMA Control for the 2nd RXDMA */
146#define THC_M_PRT_READ_DMA_CNTRL_2_OFFSET	0x120C
147/* THC Read Interrupt Status for the 2nd RXDMA */
148#define THC_M_PRT_READ_DMA_INT_STS_2_OFFSET	0x1210
149/* THC Read DMA Error Register for the 2nd RXDMA */
150#define THC_M_PRT_READ_DMA_ERR_2_OFFSET		0x1214
151/* Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA */
152#define THC_M_PRT_GUC_OFFSET_LOW_2_OFFSET	0x1218
153/* Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA */
154#define THC_M_PRT_GUC_OFFSET_HI_2_OFFSET	0x121C
155/* Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA */
156#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_2_OFFSET	0x1220
157/* Touch Host Controller GuC Control register for the 2nd RXDMA */
158#define THC_M_PRT_GUC_WORKQ_SZ_2_OFFSET		0x1224
159/* Touch Sequencer Control for the 2nd DMA */
160#define THC_M_PRT_TSEQ_CNTRL_2_OFFSET		0x1228
161/* Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA */
162#define THC_M_PRT_GUC_DB_ADDR_LOW_2_OFFSET	0x1230
163/* Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA */
164#define THC_M_PRT_GUC_DB_ADDR_HI_2_OFFSET	0x1234
165/* Touch Sequencer GuC Doorbell Data for PRD2 */
166#define THC_M_PRT_GUC_DB_DATA_2_OFFSET		0x1238
167/* Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA */
168#define THC_M_PRT_GUC_OFFSET_INITVAL_2_OFFSET	0x1240
169/* THC Device Address for the bulk/touch data read for the 2nd RXDMA */
170#define THC_M_PRT_RD_BULK_ADDR_2_OFFSET		0x1270
171/* THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port */
172#define THC_M_PRT_DB_CNT_2_OFFSET		0x12A0
173/* THC Frame Count from the 2nd Stream RXDMA on this port */
174#define THC_M_PRT_FRM_CNT_2_OFFSET		0x12A4
175/* THC Micro Frame Count from the 2nd Stream RXDMA on this port */
176#define THC_M_PRT_UFRM_CNT_2_OFFSET		0x12A8
177/* THC Packet Count from the 2nd Stream RXDMA on this port */
178#define THC_M_PRT_RXDMA_PKT_CNT_2_OFFSET	0x12AC
179/*
180 * THC Software Interrupt Count from the 2nd Stream RXDMA
181 * on this port
182 */
183#define THC_M_PRT_SWINT_CNT_2_OFFSET		0x12B0
184/* Touch Sequencer Frame Drop Counter for the 2nd RXDMA */
185#define THC_M_PRT_FRAME_DROP_CNT_2_OFFSET	0x12B4
186/* THC Coaescing 2 */
187#define THC_M_PRT_COALESCE_2_OFFSET		0x12B8
188/* THC SPARE REGISTER */
189#define THC_M_PRT_SPARE_REG_OFFSET		0x12BC
190/* THC Read PRD Base Address Low for the SW RXDMA */
191#define THC_M_PRT_RPRD_BA_LOW_SW_OFFSET		0x12C0
192/* THC Read PRD Base Address High for the SW RXDMA */
193#define THC_M_PRT_RPRD_BA_HI_SW_OFFSET		0x12C4
194/* THC Read PRD Control for the SW RXDMA */
195#define THC_M_PRT_RPRD_CNTRL_SW_OFFSET		0x12C8
196/* THC Read DMA Control for the SW RXDMA */
197#define THC_M_PRT_READ_DMA_CNTRL_SW_OFFSET	0x12CC
198/* THC Read Interrupt Status for the SW RXDMA */
199#define THC_M_PRT_READ_DMA_INT_STS_SW_OFFSET	0x12D0
200/* Touch Sequencer Control for the SW DMA */
201#define THC_M_PRT_TSEQ_CNTRL_SW_OFFSET		0x12D4
202/* Address for the bulk read for SW DMA engine */
203#define THC_M_PRT_RD_BULK_ADDR_SW_OFFSET	0x12D8
204/* THC Frame Count from the SW RXDMA on this port */
205#define THC_M_PRT_FRM_CNT_SW_OFFSET		0x12DC
206/* THC Packet Count from the SW RXDMA on this port */
207#define THC_M_PRT_RXDMA_PKT_CNT_SW_OFFSET	0x12E0
208/* SW DMA PRD Table Length */
209#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_OFFSET	0x12E4
210/* THC timing based Frame/Interrupt caolescing control register for 1st RXDMA */
211#define THC_M_PRT_COALESCE_CNTRL_1_OFFSET	0x12E8
212/* THC timing based Frame/Interrupt caolescing control register for 2nd RXDMA */
213#define THC_M_PRT_COALESCE_CNTRL_2_OFFSET	0x12EC
214/* Touch Sequencer PRD Table Empty Counter for the 1st RXDMA */
215#define THC_M_PRT_PRD_EMPTY_CNT_1_OFFSET	0x12F0
216/* Touch Sequencer PRD Table Empty Counter for the 2nd RXDM */
217#define THC_M_PRT_PRD_EMPTY_CNT_2_OFFSET	0x12F4
218/* THC coalescing status to reflect the current coalescing FSM state for 1st RXDMA */
219#define THC_M_PRT_COALESCE_STS_1_OFFSET		0x12F8
220/* THC coalescing status to reflect the current coalescing FSM state for 2nd RXDMA */
221#define THC_M_PRT_COALESCE_STS_2_OFFSET		0x12FC
222/* THC Register for the SPI Port Duty Cycle Configuration */
223#define THC_M_PRT_SPI_DUTYC_CFG_OFFSET		0x1300
224/* THC Register for SW I2C Wtite Sequecning control */
225#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_OFFSET	0x1304
226/* THC current Timestamp Register for RXDMA1 */
227#define THC_M_PRT_TIMESTAMP_1_OFFSET		0x1308
228/* THC current Timestamp Register for RXDMA2 */
229#define THC_M_PRT_TIMESTAMP_2_OFFSET		0x130C
230/* Current SYNC Event Timestamp Register */
231#define THC_M_PRT_SYNC_TIMESTAMP_OFFSET		0x1310
232/* THC Display Sync Register */
233#define THC_M_PRT_DISP_SYNC_OFFSET		0x1314
234/* THC Display Sync Register */
235#define THC_M_PRT_DISP_SYNC_2_OFFSET		0x1318
236/* THC Register for SW I2C Wtite Sequecning control */
237#define THC_M_PRT_I2C_CFG_OFFSET		0x131C
238
239/* THC register bits definition */
240#define TXN_ERR_INT_STS_BIT			BIT(28)
241#define TXN_FATAL_INT_STS_BIT			BIT(30)
242
243#define NONDMA_INT_STS_BIT			BIT(4)
244#define EOF_INT_STS_BIT				BIT(5)
245
246#define THC_CFG_DID_VID_VID		        GENMASK(15, 0)
247#define THC_CFG_DID_VID_DID		        GENMASK(31, 16)
248
249#define THC_CFG_STS_CMD_IOSE			BIT(0)
250#define THC_CFG_STS_CMD_MSE			BIT(1)
251#define THC_CFG_STS_CMD_BME			BIT(2)
252#define THC_CFG_STS_CMD_SPCYC			BIT(3)
253#define THC_CFG_STS_CMD_MWRIEN			BIT(4)
254#define THC_CFG_STS_CMD_VGAPS			BIT(5)
255#define THC_CFG_STS_CMD_PERRR			BIT(6)
256#define THC_CFG_STS_CMD_SERREN			BIT(8)
257#define THC_CFG_STS_CMD_FBTBEN			BIT(9)
258#define THC_CFG_STS_CMD_INTD			BIT(10)
259#define THC_CFG_STS_CMD_INTS			BIT(19)
260#define THC_CFG_STS_CMD_CAPL			BIT(20)
261#define THC_CFG_STS_CMD_MCAP			BIT(21)
262#define THC_CFG_STS_CMD_FBTBC			BIT(23)
263#define THC_CFG_STS_CMD_MDPE			BIT(24)
264#define THC_CFG_STS_CMD_DEVT			GENMASK(26, 25)
265#define THC_CFG_STS_CMD_STA			BIT(27)
266#define THC_CFG_STS_CMD_RTA			BIT(28)
267#define THC_CFG_STS_CMD_RMA			BIT(29)
268#define THC_CFG_STS_CMD_SSE			BIT(30)
269#define THC_CFG_STS_CMD_DPE			BIT(31)
270
271#define THC_CFG_CC_RID_RID			GENMASK(7, 0)
272#define THC_CFG_CC_RID_PI			GENMASK(15, 8)
273#define THC_CFG_CC_RID_SCC			GENMASK(23, 16)
274#define THC_CFG_CC_RID_BCC			GENMASK(31, 24)
275
276#define THC_CFG_BIST_HTYPE_LT_CLS_CLSZ		GENMASK(7, 0)
277#define THC_CFG_BIST_HTYPE_LT_CLS_LT		GENMASK(15, 8)
278#define THC_CFG_BIST_HTYPE_LT_CLS_HTYPE		GENMASK(22, 16)
279#define THC_CFG_BIST_HTYPE_LT_CLS_MFD		BIT(23)
280
281#define THC_CFG_BAR0_LOW_MEMSPACE		BIT(0)
282#define THC_CFG_BAR0_LOW_TYP			GENMASK(2, 1)
283#define THC_CFG_BAR0_LOW_PREFETCH		BIT(3)
284#define THC_CFG_BAR0_LOW_MEMSIZE		GENMASK(14, 4)
285#define THC_CFG_BAR0_LOW_MEMBAR			GENMASK(31, 15)
286#define THC_CFG_BAR0_HI_MEMBAR			GENMASK(31, 0)
287
288#define THC_CFG_SID_SVID_SSVID			GENMASK(15, 0)
289#define THC_CFG_SID_SVID_SSID			GENMASK(31, 16)
290
291#define THC_CFG_CAPP_CP				GENMASK(7, 0)
292
293#define THC_CFG_INT_ILINE			GENMASK(7, 0)
294#define THC_CFG_INT_IPIN			GENMASK(15, 8)
295
296#define THC_CFG_UR_STS_CTL_URRE			BIT(0)
297#define THC_CFG_UR_STS_CTL_URD			BIT(1)
298#define THC_CFG_UR_STS_CTL_FD			BIT(2)
299
300#define THC_CFG_MSIMC_MSINP_MSICID_CAPID	GENMASK(7, 0)
301#define THC_CFG_MSIMC_MSINP_MSICID_NXTP	        GENMASK(15, 8)
302#define THC_CFG_MSIMC_MSINP_MSICID_MSIE		BIT(16)
303#define THC_CFG_MSIMC_MSINP_MSICID_MMC	        GENMASK(19, 17)
304#define THC_CFG_MSIMC_MSINP_MSICID_MMEN	        GENMASK(22, 20)
305#define THC_CFG_MSIMC_MSINP_MSICID_XAC		BIT(23)
306#define THC_CFG_MSIMC_MSINP_MSICID_PVMC		BIT(24)
307#define THC_CFG_MSIMA_MADDR		        GENMASK(31, 2)
308#define THC_CFG_MSIMUA_MAUDDR		        GENMASK(31, 0)
309#define THC_CFG_MSIMD_MDAT			GENMASK(15, 0)
310
311#define THC_CFG_PMCAP_PMNP_PMCID_CAPP	        GENMASK(7, 0)
312#define THC_CFG_PMCAP_PMNP_PMCID_NXTP	        GENMASK(15, 8)
313#define THC_CFG_PMCAP_PMNP_PMCID_VER	        GENMASK(18, 16)
314#define THC_CFG_PMCAP_PMNP_PMCID_PMECLK		BIT(19)
315#define THC_CFG_PMCAP_PMNP_PMCID_DSI		BIT(21)
316#define THC_CFG_PMCAP_PMNP_PMCID_AUXC	        GENMASK(24, 22)
317#define THC_CFG_PMCAP_PMNP_PMCID_D1S		BIT(25)
318#define THC_CFG_PMCAP_PMNP_PMCID_D2S		BIT(26)
319#define THC_CFG_PMCAP_PMNP_PMCID_PMES	        GENMASK(31, 27)
320
321#define THC_CFG_PMD_PMCSRBSE_PMCSR_PWRST	GENMASK(1, 0)
322#define THC_CFG_PMD_PMCSRBSE_PMCSR_NSR		BIT(3)
323#define THC_CFG_PMD_PMCSRBSE_PMCSR_PMEEN	BIT(8)
324#define THC_CFG_PMD_PMCSRBSE_PMCSR_DSEL	        GENMASK(12, 9)
325#define THC_CFG_PMD_PMCSRBSE_PMCSR_DS	        GENMASK(14, 13)
326#define THC_CFG_PMD_PMCSRBSE_PMCSR_PMESTS	BIT(15)
327
328#define THC_CFG_DEVIDLE_CAPPID		        GENMASK(7, 0)
329#define THC_CFG_DEVIDLE_NCAPPP		        GENMASK(15, 8)
330#define THC_CFG_DEVIDLE_LENGTH		        GENMASK(23, 16)
331#define THC_CFG_DEVIDLE_REV		        GENMASK(27, 24)
332#define THC_CFG_DEVIDLE_VID		        GENMASK(31, 28)
333
334#define THC_CFG_VSHDR_VSECID		        GENMASK(15, 0)
335#define THC_CFG_VSHDR_VSECR		        GENMASK(19, 16)
336#define THC_CFG_VSHDR_VSECL		        GENMASK(31, 20)
337
338#define THC_CFG_SWLTRPTR_VALID			BIT(0)
339#define THC_CFG_SWLTRPTR_BARNUM		        GENMASK(3, 1)
340#define THC_CFG_SWLTRPTR_SWLTRLOC		GENMASK(31, 4)
341
342#define THC_CFG_DEVIDLEPTR_VALID		BIT(0)
343#define THC_CFG_DEVIDLEPTR_BARNUM		GENMASK(3, 1)
344#define THC_CFG_DEVIDLEPTR_DEVIDLELOC	        GENMASK(31, 4)
345#define THC_CFG_DEVIDLEPOL_POLV		        GENMASK(9, 0)
346#define THC_CFG_DEVIDLEPOL_POLS		        GENMASK(12, 10)
347
348#define THC_CFG_PCE_SPE				BIT(0)
349#define THC_CFG_PCE_I3E				BIT(1)
350#define THC_CFG_PCE_D3HE			BIT(2)
351#define THC_CFG_PCE_SE				BIT(3)
352#define THC_CFG_PCE_HAE				BIT(5)
353
354#define THC_CFG_MANID_PROC			GENMASK(7, 0)
355#define THC_CFG_MANID_MID			GENMASK(15, 8)
356#define THC_CFG_MANID_MSID			GENMASK(23, 16)
357#define THC_CFG_MANID_DOT			GENMASK(27, 24)
358
359#define THC_M_CMN_DEVIDLECTRL_CIP		BIT(0)
360#define THC_M_CMN_DEVIDLECTRL_IR		BIT(1)
361#define THC_M_CMN_DEVIDLECTRL_DEVIDLE		BIT(2)
362#define THC_M_CMN_DEVIDLECTRL_RR		BIT(3)
363#define THC_M_CMN_DEVIDLECTRL_IRC		BIT(4)
364
365#define THC_M_CMN_LTR_CTRL_OFFSET		0x14
366#define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_REQ	BIT(0)
367#define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_EN	BIT(1)
368#define THC_M_CMN_LTR_CTRL_LP_LTR_REQ		BIT(2)
369#define THC_M_CMN_LTR_CTRL_LP_LTR_EN		BIT(3)
370#define THC_M_CMN_LTR_CTRL_LP_LTR_SCALE	        GENMASK(6, 4)
371#define THC_M_CMN_LTR_CTRL_LP_LTR_VAL	        GENMASK(16, 7)
372#define THC_M_CMN_LTR_CTRL_ACT_LTR_SCALE	GENMASK(19, 17)
373#define THC_M_CMN_LTR_CTRL_ACT_LTR_VAL	        GENMASK(29, 20)
374#define THC_M_CMN_LTR_CTRL_LAST_LTR_SENT	GENMASK(31, 30)
375
376#define THC_M_PRT_CONTROL_TSFTRST		BIT(0)
377#define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_EN	BIT(1)
378#define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_HW_STS	BIT(2)
379#define THC_M_PRT_CONTROL_DEVRST		BIT(3)
380#define THC_M_PRT_CONTROL_THC_DRV_LOCK_EN	BIT(13)
381#define THC_M_PRT_CONTROL_THC_INSTANCE_INDEX	GENMASK(18, 16)
382#define THC_M_PRT_CONTROL_PORT_INDEX	        GENMASK(22, 20)
383#define THC_M_PRT_CONTROL_THC_ARB_POLICY	GENMASK(25, 24)
384#define THC_M_PRT_CONTROL_THC_BIOS_LOCK_EN	BIT(27)
385#define THC_M_PRT_CONTROL_PORT_SUPPORTED	BIT(28)
386#define THC_M_PRT_CONTROL_SPI_IO_RDY		BIT(29)
387#define THC_M_PRT_CONTROL_PORT_TYPE	        GENMASK(31, 30)
388
389#define THC_M_PRT_SPI_CFG_SPI_TRDC		GENMASK(1, 0)
390#define THC_M_PRT_SPI_CFG_SPI_TRMODE	        GENMASK(3, 2)
391#define THC_M_PRT_SPI_CFG_SPI_TCRF		GENMASK(6, 4)
392#define THC_M_PRT_SPI_CFG_SPI_RD_MPS	        GENMASK(15, 7)
393#define THC_M_PRT_SPI_CFG_SPI_TWMODE	        GENMASK(19, 18)
394#define THC_M_PRT_SPI_CFG_SPI_TCWF		GENMASK(22, 20)
395#define THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN	BIT(23)
396#define THC_M_PRT_SPI_CFG_SPI_WR_MPS	        GENMASK(31, 24)
397
398#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_SIO	GENMASK(31, 24)
399#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_DIO	GENMASK(23, 16)
400#define THC_M_PRT_SPI_ICRRD_OPCODE_SPI_QIO	GENMASK(15, 8)
401
402#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE		GENMASK(15, 0)
403#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL		GENMASK(23, 16)
404#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL_EN	BIT(30)
405#define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE_EN	BIT(31)
406
407#define THC_M_PRT_INT_EN_SIPE				BIT(0)
408#define THC_M_PRT_INT_EN_SBO				BIT(1)
409#define THC_M_PRT_INT_EN_SIDR				BIT(2)
410#define THC_M_PRT_INT_EN_SOFB				BIT(3)
411#define THC_M_PRT_INT_EN_INVLD_DEV_ENTRY_INT_EN		BIT(9)
412#define THC_M_PRT_INT_EN_FRAME_BABBLE_ERR_INT_EN	BIT(10)
413#define THC_M_PRT_INT_EN_BUF_OVRRUN_ERR_INT_EN		BIT(12)
414#define THC_M_PRT_INT_EN_PRD_ENTRY_ERR_INT_EN		BIT(13)
415#define THC_M_PRT_INT_EN_DISP_SYNC_EVT_INT_EN		BIT(14)
416#define THC_M_PRT_INT_EN_DEV_RAW_INT_EN			BIT(15)
417#define THC_M_PRT_INT_EN_FATAL_ERR_INT_EN		BIT(16)
418#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_UNDER_INT_EN	BIT(17)
419#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_OVER_INT_EN	BIT(18)
420#define THC_M_PRT_INT_EN_THC_I2C_IC_RX_FULL_INT_EN	BIT(19)
421#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_OVER_INT_EN	BIT(20)
422#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_EMPTY_INT_EN	BIT(21)
423#define THC_M_PRT_INT_EN_THC_I2C_IC_TX_ABRT_INT_EN	BIT(22)
424#define THC_M_PRT_INT_EN_THC_I2C_IC_SCL_STUCK_AT_LOW_DET_INT_EN	BIT(24)
425#define THC_M_PRT_INT_EN_THC_I2C_IC_STOP_DET_INT_EN	BIT(25)
426#define THC_M_PRT_INT_EN_THC_I2C_IC_START_DET_INT_EN	BIT(26)
427#define THC_M_PRT_INT_EN_THC_I2C_IC_MST_ON_HOLD_INT_EN	BIT(27)
428#define THC_M_PRT_INT_EN_TXN_ERR_INT_EN			BIT(29)
429#define THC_M_PRT_INT_EN_GBL_INT_EN			BIT(31)
430
431#define THC_M_PRT_INT_STATUS_DISP_SYNC_EVT_INT_STS		BIT(14)
432#define THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS			BIT(15)
433#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS	BIT(17)
434#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS		BIT(18)
435#define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS		BIT(19)
436#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS		BIT(20)
437#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS	BIT(21)
438#define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS		BIT(22)
439#define THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS	BIT(23)
440#define THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS	BIT(24)
441#define THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS	BIT(25)
442#define THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS	BIT(26)
443#define THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS	BIT(27)
444#define THC_M_PRT_INT_STATUS_TXN_ERR_INT_STS			BIT(28)
445#define THC_M_PRT_INT_STATUS_FATAL_ERR_INT_STS			BIT(30)
446
447#define THC_M_PRT_ERR_CAUSE_INVLD_DEV_ENTRY	BIT(9)
448#define THC_M_PRT_ERR_CAUSE_FRAME_BABBLE_ERR	BIT(10)
449#define THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR	BIT(12)
450#define THC_M_PRT_ERR_CAUSE_PRD_ENTRY_ERR	BIT(13)
451#define THC_M_PRT_ERR_CAUSE_FATAL_ERR_CAUSE	GENMASK(23, 16)
452
453#define THC_M_PRT_SW_SEQ_CNTRL_TSSGO		BIT(0)
454#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CD_IE	BIT(1)
455#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CMD	GENMASK(15, 8)
456#define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_BC	GENMASK(31, 16)
457#define THC_M_PRT_SW_SEQ_STS_TSSDONE		BIT(0)
458#define THC_M_PRT_SW_SEQ_STS_THC_SS_ERR		BIT(1)
459#define THC_M_PRT_SW_SEQ_STS_THC_SS_CIP		BIT(3)
460#define THC_M_PRT_SW_SEQ_DATA0_ADDR_THC_SW_SEQ_DATA0_ADDR	GENMASK(31, 0)
461#define THC_M_PRT_SW_SEQ_DATA1_THC_SW_SEQ_DATA1		        GENMASK(31, 0)
462
463#define THC_M_PRT_WPRD_BA_LOW_THC_M_PRT_WPRD_BA_LOW	        GENMASK(31, 12)
464#define THC_M_PRT_WPRD_BA_HI_THC_M_PRT_WPRD_BA_HI		GENMASK(31, 0)
465
466#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_START		BIT(0)
467#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_ERROR	BIT(1)
468#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC		BIT(2)
469#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_DMACPL	BIT(3)
470#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_UHS			BIT(23)
471#define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_PTEC		GENMASK(31, 24)
472
473#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_CMPL_STATUS		BIT(0)
474#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ERROR_STS		BIT(1)
475#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_IOC_STS		BIT(2)
476#define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ACTIVE		BIT(3)
477
478#define THC_M_PRT_WR_BULK_ADDR_THC_M_PRT_WR_BULK_ADDR	        GENMASK(31, 0)
479
480#define THC_M_PRT_DEV_INT_CAUSE_ADDR_THC_M_PRT_DEV_INT_CAUSE_ADDR	GENMASK(31, 0)
481#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_INTERRUPT_TYPE	        GENMASK(3, 0)
482#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_MICRO_FRAME_SIZE	GENMASK(23, 4)
483#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_BEGINNING_OF_FRAME	BIT(29)
484#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_END_OF_FRAME		BIT(30)
485#define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_FRAME_TYPE		BIT(31)
486
487#define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT		GENMASK(30, 0)
488#define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT_RST		BIT(31)
489
490#define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT	        GENMASK(30, 0)
491#define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT_RST	BIT(31)
492
493#define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT		GENMASK(30, 0)
494#define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT_RST		BIT(31)
495
496#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_OFFSET	        GENMASK(4, 0)
497#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_LEN	        GENMASK(9, 5)
498#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_EOF_OFFSET	        GENMASK(14, 10)
499#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_SEND_ICR_US_EN		BIT(15)
500#define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_INTTYP_DATA_VAL	GENMASK(31, 16)
501
502#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_OFFSET	        GENMASK(4, 0)
503#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_LEN	        GENMASK(9, 5)
504#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_UFSIZE_UNIT	        GENMASK(15, 12)
505#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_IGNORE		BIT(16)
506#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_VAL		BIT(17)
507#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_ADDRINC_DIS	BIT(24)
508#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_ADDRINC_DIS	BIT(25)
509#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_PKT_STRM_EN	BIT(26)
510#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_PKT_STRM_EN	BIT(27)
511#define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_DEVINT_POL		BIT(28)
512
513#define THC_M_PRT_RPRD_BA_LOW_1_THC_M_PRT_RPRD_BA_LOW	        GENMASK(31, 12)
514#define THC_M_PRT_RPRD_BA_HI_1_THC_M_PRT_RPRD_BA_HI	        GENMASK(31, 0)
515
516#define THC_M_PRT_RPRD_CNTRL_PCD		GENMASK(6, 0)
517#define THC_M_PRT_RPRD_CNTRL_PTEC		GENMASK(15, 8)
518#define THC_M_PRT_RPRD_CNTRL_PREFETCH_WM	GENMASK(19, 16)
519
520#define THC_M_PRT_READ_DMA_CNTRL_START		BIT(0)
521#define THC_M_PRT_READ_DMA_CNTRL_IE_ERROR	BIT(1)
522#define THC_M_PRT_READ_DMA_CNTRL_IE_IOC		BIT(2)
523#define THC_M_PRT_READ_DMA_CNTRL_IE_STALL	BIT(3)
524#define THC_M_PRT_READ_DMA_CNTRL_IE_NDDI	BIT(4)
525#define THC_M_PRT_READ_DMA_CNTRL_IE_EOF		BIT(5)
526#define THC_M_PRT_READ_DMA_CNTRL_IE_DMACPL	BIT(7)
527#define THC_M_PRT_READ_DMA_CNTRL_TPCRP	        GENMASK(15, 8)
528#define THC_M_PRT_READ_DMA_CNTRL_TPCWP	        GENMASK(23, 16)
529#define THC_M_PRT_READ_DMA_CNTRL_INT_SW_DMA_EN	BIT(28)
530#define THC_M_PRT_READ_DMA_CNTRL_SOO		BIT(29)
531#define THC_M_PRT_READ_DMA_CNTRL_UHS		BIT(30)
532#define THC_M_PRT_READ_DMA_CNTRL_TPCPR		BIT(31)
533
534#define THC_M_PRT_READ_DMA_INT_STS_DMACPL_STS	BIT(0)
535#define THC_M_PRT_READ_DMA_INT_STS_ERROR_STS	BIT(1)
536#define THC_M_PRT_READ_DMA_INT_STS_IOC_STS	BIT(2)
537#define THC_M_PRT_READ_DMA_INT_STS_STALL_STS	BIT(3)
538#define THC_M_PRT_READ_DMA_INT_STS_NONDMA_INT_STS	BIT(4)
539#define THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS	BIT(5)
540#define THC_M_PRT_READ_DMA_INT_STS_ACTIVE	BIT(8)
541
542#define THC_M_PRT_READ_DMA_ERR_1_DLERR		BIT(0)
543
544#define THC_M_PRT_GUC_OFFSET_LOW_1_THC_M_PRT_GUC_OFFSET_LOW	GENMASK(31, 3)
545#define THC_M_PRT_GUC_OFFSET_HI_1_THC_M_PRT_GUC_OFFSET_HI	GENMASK(31, 0)
546#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_1_WORKQ_ITEM_SZ	        GENMASK(23, 0)
547#define THC_M_PRT_GUC_WORKQ_SZ_1_WORKQ_SZ       GENMASK(23, 0)
548#define THC_M_PRT_GUC_WORKQ_SZ_1_FCD	        GENMASK(27, 24)
549#define THC_M_PRT_GUC_WORKQ_SZ_1_GIC	        GENMASK(31, 28)
550
551#define THC_M_PRT_TSEQ_CNTRL_1_RGD		BIT(2)
552#define THC_M_PRT_TSEQ_CNTRL_1_EGP		BIT(3)
553#define THC_M_PRT_TSEQ_CNTRL_1_RTO		BIT(4)
554#define THC_M_PRT_TSEQ_CNTRL_1_EWOG		BIT(5)
555#define THC_M_PRT_TSEQ_CNTRL_1_RWOGC		BIT(6)
556#define THC_M_PRT_TSEQ_CNTRL_1_RX_DATA_FIFO_WR_WM		GENMASK(25, 16)
557#define THC_M_PRT_TSEQ_CNTRL_1_RESET_PREP_CHICKEN		BIT(30)
558#define THC_M_PRT_TSEQ_CNTRL_1_INT_EDG_DET_EN			BIT(31)
559
560#define THC_M_PRT_GUC_DB_ADDR_LOW_1_GUC_DB_ADDR_LOW	        GENMASK(31, 2)
561#define THC_M_PRT_GUC_DB_ADDR_HI_1_GUC_DB_ADDR_HI		GENMASK(31, 0)
562#define THC_M_PRT_GUC_DB_DATA_1_GUC_DB_DATA		        GENMASK(31, 0)
563#define THC_M_PRT_GUC_OFFSET_INITVAL_1_THC_M_PRT_GUC_OFFSET_INITVAL	GENMASK(31, 0)
564
565#define THC_M_PRT_RD_BULK_ADDR_1_THC_M_PRT_RD_BULK_ADDR	        GENMASK(31, 0)
566
567#define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT		        GENMASK(30, 0)
568#define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT_RST			BIT(31)
569
570#define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT		        GENMASK(30, 0)
571#define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT_RST		BIT(31)
572
573#define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT		        GENMASK(30, 0)
574#define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT_RST		BIT(31)
575
576#define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT	GENMASK(30, 0)
577#define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT_RST	BIT(31)
578
579#define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT		GENMASK(30, 0)
580#define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT_RST		BIT(31)
581
582#define THC_M_PRT_FRAME_DROP_CNT_1_NOFD			        GENMASK(30, 0)
583#define THC_M_PRT_FRAME_DROP_CNT_1_RFDC				BIT(31)
584
585#define THC_M_PRT_COALESCE_1_COALESCE_TIMEOUT		        GENMASK(6, 0)
586
587#define THC_M_PRT_RPRD_BA_LOW_2_THC_M_PRT_RPRD_BA_LOW	        GENMASK(31, 12)
588#define THC_M_PRT_RPRD_BA_HI_2_THC_M_PRT_RPRD_BA_HI	        GENMASK(31, 0)
589
590#define THC_M_PRT_READ_DMA_ERR_2_DLERR				BIT(0)
591
592#define THC_M_PRT_GUC_OFFSET_LOW_2_THC_M_PRT_GUC_OFFSET_LOW     GENMASK(31, 3)
593#define THC_M_PRT_GUC_OFFSET_HI_2_THC_M_PRT_GUC_OFFSET_HI	GENMASK(31, 0)
594
595#define THC_M_PRT_GUC_WORKQ_ITEM_SZ_2_WORKQ_ITEM_SZ	        GENMASK(23, 0)
596#define THC_M_PRT_GUC_WORKQ_SZ_2_WORKQ_SZ			GENMASK(23, 0)
597#define THC_M_PRT_GUC_WORKQ_SZ_2_FCD			        GENMASK(27, 24)
598#define THC_M_PRT_GUC_WORKQ_SZ_2_GIC			        GENMASK(31, 28)
599
600#define THC_M_PRT_TSEQ_CNTRL_2_RGD				BIT(2)
601#define THC_M_PRT_TSEQ_CNTRL_2_EGP				BIT(3)
602#define THC_M_PRT_TSEQ_CNTRL_2_RTO				BIT(4)
603
604#define THC_M_PRT_GUC_DB_ADDR_LOW_2_GUC_DB_ADDR_LOW	        GENMASK(31, 2)
605#define THC_M_PRT_GUC_DB_ADDR_HI_2_GUC_DB_ADDR_HI		GENMASK(31, 0)
606
607#define THC_M_PRT_GUC_DB_DATA_2_GUC_DB_DATA		        GENMASK(31, 0)
608
609#define THC_M_PRT_GUC_OFFSET_INITVAL_2_THC_M_PRT_GUC_OFFSET_INITVAL	GENMASK(31, 0)
610
611#define THC_M_PRT_RD_BULK_ADDR_2_THC_M_PRT_RD_BULK_ADDR	        GENMASK(31, 0)
612
613#define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT		        GENMASK(30, 0)
614#define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT_RST			BIT(31)
615
616#define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT		        GENMASK(30, 0)
617#define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT_RST		BIT(31)
618
619#define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT		        GENMASK(30, 0)
620#define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT_RST		BIT(31)
621
622#define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT	GENMASK(30, 0)
623#define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT_RST	BIT(31)
624
625#define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT		GENMASK(30, 0)
626#define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT_RST		BIT(31)
627
628#define THC_M_PRT_FRAME_DROP_CNT_2_NOFD			        GENMASK(30, 0)
629#define THC_M_PRT_FRAME_DROP_CNT_2_RFDC				BIT(31)
630
631#define THC_M_PRT_COALESCE_2_COALESCE_TIMEOUT		        GENMASK(6, 0)
632
633#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_I2C_RW_PIO_EN		BIT(23)
634#define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_PIO_I2C_WBC	        GENMASK(31, 26)
635
636#define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_RX_DLEN_EN	BIT(23)
637#define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_WBC		GENMASK(31, 26)
638
639#define THC_M_PRT_PRD_EMPTY_CNT_1_RPTEC				BIT(31)
640#define THC_M_PRT_PRD_EMPTY_CNT_2_RPTEC				BIT(31)
641
642#define THC_M_PRT_SW_DMA_PRD_TABLE_LEN_THC_M_PRT_SW_DMA_PRD_TABLE_LEN	GENMASK(23, 0)
643
644#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_VAL		GENMASK(3, 0)
645#define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN		BIT(25)
646
647/* CS Assertion delay default value */
648#define THC_CSA_CK_DELAY_VAL_DEFAULT		4
649
650/* ARB policy definition */
651/* Arbiter switches on packet boundary */
652#define THC_ARB_POLICY_PACKET_BOUNDARY		0
653/* Arbiter switches on Micro Frame boundary */
654#define THC_ARB_POLICY_UFRAME_BOUNDARY		1
655/* Arbiter switches on Frame boundary */
656#define THC_ARB_POLICY_FRAME_BOUNDARY		2
657
658#define THC_REGMAP_POLLING_INTERVAL_US		10 /* 10us */
659#define THC_PIO_DONE_TIMEOUT_US			USEC_PER_SEC /* 1s */
660
661/* Default configures for HIDSPI */
662#define THC_BIT_OFFSET_INTERRUPT_TYPE		4
663/* input_report_type is 4 bits for HIDSPI */
664#define THC_BIT_LENGTH_INTERRUPT_TYPE		4
665/* Last fragment indicator is bit 15 for HIDSPI */
666#define THC_BIT_OFFSET_LAST_FRAGMENT_FLAG	22
667#define THC_BIT_OFFSET_MICROFRAME_SIZE		8
668/* input_report_length is 14 bits for HIDSPI */
669#define THC_BIT_LENGTH_MICROFRAME_SIZE		14
670/* MFS unit in power of 2 */
671#define THC_UNIT_MICROFRAME_SIZE		2
672#define THC_BITMASK_INTERRUPT_TYPE_DATA		1
673#define THC_BITMASK_INVALID_TYPE_DATA		2
674
675/* Interrupt Quiesce default timeout value */
676#define THC_QUIESCE_EN_TIMEOUT_US		USEC_PER_SEC /* 1s */
677
678/* LTR definition */
679/*
680 * THC uses scale to calculate final LTR value.
681 * Scale is geometric progression of 2^5 step, starting from 2^0.
682 * For example, THC_LTR_SCALE_2(2) means 2^(5 * 2) = 1024, unit is ns.
683 */
684#define THC_LTR_SCALE_0				0
685#define THC_LTR_SCALE_1				1
686#define THC_LTR_SCALE_2				2
687#define THC_LTR_SCALE_3				3
688#define THC_LTR_SCALE_4				4
689#define THC_LTR_SCALE_5				5
690#define THC_LTR_MODE_ACTIVE			0
691#define THC_LTR_MODE_LP				1
692#define THC_LTR_MIN_VAL_SCALE_3			BIT(10)
693#define THC_LTR_MAX_VAL_SCALE_3			BIT(15)
694#define THC_LTR_MIN_VAL_SCALE_4			BIT(15)
695#define THC_LTR_MAX_VAL_SCALE_4			BIT(20)
696#define THC_LTR_MIN_VAL_SCALE_5			BIT(20)
697#define THC_LTR_MAX_VAL_SCALE_5			BIT(25)
698
699/*
700 * THC PIO opcode default value
701 * @THC_PIO_OP_SPI_TIC_READ: THC opcode for SPI PIO read
702 * @THC_PIO_OP_SPI_TIC_WRITE: THC opcode for SPI PIO write
703 * @THC_PIO_OP_I2C_SUBSYSTEM_READ: THC opcode for read I2C subsystem registers
704 * @THC_PIO_OP_I2C_SUBSYSTEM_WRITE: THC opcode for write I2C subsystem registers
705 * @THC_PIO_OP_I2C_TIC_READ: THC opcode for read I2C device
706 * @THC_PIO_OP_I2C_TIC_WRITE: THC opcode for write I2C device
707 * @THC_PIO_OP_I2C_TIC_WRITE_AND_READ: THC opcode for write followed by read I2C device
708 */
709enum thc_pio_opcode {
710	THC_PIO_OP_SPI_TIC_READ = 0x4,
711	THC_PIO_OP_SPI_TIC_WRITE = 0x6,
712	THC_PIO_OP_I2C_SUBSYSTEM_READ = 0x12,
713	THC_PIO_OP_I2C_SUBSYSTEM_WRITE = 0x13,
714	THC_PIO_OP_I2C_TIC_READ = 0x14,
715	THC_PIO_OP_I2C_TIC_WRITE = 0x18,
716	THC_PIO_OP_I2C_TIC_WRITE_AND_READ = 0x1C,
717};
718
719/**
720 * THC SPI IO mode
721 * @THC_SINGLE_IO: single IO mode, 1(opcode) - 1(address) - 1(data)
722 * @THC_DUAL_IO: dual IO mode, 1(opcode) - 2(address) - 2(data)
723 * @THC_QUAD_IO: quad IO mode, 1(opcode) - 4(address) - 4(data)
724 * @THC_QUAD_PARALLEL_IO: parallel quad IO mode, 4(opcode) - 4(address) - 4(data)
725 */
726enum thc_spi_iomode {
727	THC_SINGLE_IO = 0,
728	THC_DUAL_IO = 1,
729	THC_QUAD_IO = 2,
730	THC_QUAD_PARALLEL_IO = 3,
731};
732
733/**
734 * THC SPI frequency divider
735 *
736 * This DIV final value is determined by THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN bit.
737 * If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't be set, THC takes the DIV value directly;
738 * If THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC takes the DIV value multiply by 8.
739 *
740 * For example, if THC input clock is 125MHz:
741 * When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN isn't set, THC_SPI_FRQ_DIV_3 means DIV is 3,
742 * THC final clock is 125 / 3 = 41.667MHz;
743 * When THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN is set, THC_SPI_FRQ_DIV_3 means DIV is 3 * 8,
744 * THC final clock is 125 / (3 * 8) = 5.208MHz;
745 */
746enum thc_spi_frq_div {
747	THC_SPI_FRQ_RESERVED = 0,
748	THC_SPI_FRQ_DIV_1 = 1,
749	THC_SPI_FRQ_DIV_2 = 2,
750	THC_SPI_FRQ_DIV_3 = 3,
751	THC_SPI_FRQ_DIV_4 = 4,
752	THC_SPI_FRQ_DIV_5 = 5,
753	THC_SPI_FRQ_DIV_6 = 6,
754	THC_SPI_FRQ_DIV_7 = 7,
755};
756
757/* THC I2C sub-system registers */
758#define THC_I2C_IC_CON_OFFSET				0x0
759#define THC_I2C_IC_TAR_OFFSET				0x4
760#define THC_I2C_IC_SAR_OFFSET				0x8
761#define THC_I2C_IC_HS_MADDR_OFFSET			0xC
762#define THC_I2C_IC_DATA_CMD_OFFSET			0x10
763#define THC_I2C_IC_SS_SCL_HCNT_OFFSET			0x14
764#define THC_I2C_IC_UFM_SCL_HCNT_OFFSET			0x14
765#define THC_I2C_IC_SS_SCL_LCNT_OFFSET			0x18
766#define THC_I2C_IC_UFM_SCL_LCNT_OFFSET			0x18
767#define THC_I2C_IC_FS_SCL_HCNT_OFFSET			0x1C
768#define THC_I2C_IC_UFM_TBUF_CNT_OFFSET			0x1C
769#define THC_I2C_IC_FS_SCL_LCNT_OFFSET			0x20
770#define THC_I2C_IC_HS_SCL_HCNT_OFFSET			0x24
771#define THC_I2C_IC_HS_SCL_LCNT_OFFSET			0x28
772#define THC_I2C_IC_INTR_STAT_OFFSET			0x2C
773#define THC_I2C_IC_INTR_MASK_OFFSET			0x30
774#define THC_I2C_IC_RAW_INTR_STAT_OFFSET			0x34
775#define THC_I2C_IC_RX_TL_OFFSET				0x38
776#define THC_I2C_IC_TX_TL_OFFSET				0x3C
777#define THC_I2C_IC_CLR_INTR_OFFSET			0x40
778#define THC_I2C_IC_CLR_RX_UNDER_OFFSET			0x44
779#define THC_I2C_IC_CLR_RX_OVER_OFFSET			0x48
780#define THC_I2C_IC_CLR_TX_OVER_OFFSET			0x4C
781#define THC_I2C_IC_CLR_RD_REQ_OFFSET			0x50
782#define THC_I2C_IC_CLR_TX_ABRT_OFFSET			0x54
783#define THC_I2C_IC_CLR_RX_DONE_OFFSET			0x58
784#define THC_I2C_IC_CLR_ACTIVITY_OFFSET			0x5C
785#define THC_I2C_IC_CLR_STOP_DET_OFFSET			0x60
786#define THC_I2C_IC_CLR_START_DET_OFFSET			0x64
787#define THC_I2C_IC_CLR_GEN_CALL_OFFSET			0x68
788#define THC_I2C_IC_ENABLE_OFFSET			0x6C
789#define THC_I2C_IC_STATUS_OFFSET			0x70
790#define THC_I2C_IC_TXFLR_OFFSET				0x74
791#define THC_I2C_IC_RXFLR_OFFSET				0x78
792#define THC_I2C_IC_SDA_HOLD_OFFSET			0x7C
793#define THC_I2C_IC_TX_ABRT_SOURCE_OFFSET		0x80
794#define THC_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET		0x84
795#define THC_I2C_IC_DMA_CR_OFFSET			0x88
796#define THC_I2C_IC_DMA_TDLR_OFFSET			0x8C
797#define THC_I2C_IC_DMA_RDLR_OFFSET			0x90
798#define THC_I2C_IC_SDA_SETUP_OFFSET			0x94
799#define THC_I2C_IC_ACK_GENERAL_CALL_OFFSET		0x98
800#define THC_I2C_IC_ENABLE_STATUS_OFFSET			0x9C
801#define THC_I2C_IC_FS_SPKLEN_OFFSET			0xA0
802#define THC_I2C_IC_UFM_SPKLEN_OFFSET			0xA0
803#define THC_I2C_IC_HS_SPKLEN_OFFSET			0xA4
804#define THC_I2C_IC_CLR_RESTART_DET_OFFSET		0xA8
805#define THC_I2C_IC_SCL_STUCK_AT_LOW_TIMEOUT_OFFSET	0xAC
806#define THC_I2C_IC_SDA_STUCK_AT_LOW_TIMEOUT_OFFSET	0xB0
807#define THC_I2C_IC_CLR_SCL_STUCK_DET_OFFSET		0xB4
808#define THC_I2C_IC_DEVICE_ID_OFFSET			0xB8
809#define THC_I2C_IC_SMBUS_CLK_LOW_SEXT_OFFSET		0xBC
810#define THC_I2C_IC_SMBUS_CLK_LOW_MEXT_OFFSET		0xC0
811#define THC_I2C_IC_SMBUS_THIGH_MAX_IDLE_COUNT_OFFSET	0xC4
812#define THC_I2C_IC_SMBUS_INTR_STAT_OFFSET		0xC8
813#define THC_I2C_IC_SMBUS_INTR_MASK_OFFSET		0xCC
814#define THC_I2C_IC_SMBUS_RAW_INTR_STAT_OFFSET		0xD0
815#define THC_I2C_IC_CLR_SMBUS_INTR_OFFSET		0xD4
816#define THC_I2C_IC_OPTIONAL_SAR_OFFSET			0xD8
817#define THC_I2C_IC_SMBUS_UDID_LSB_OFFSET		0xDC
818#define THC_I2C_IC_SMBUS_UDID_WORD0_OFFSET		0xDC
819#define THC_I2C_IC_SMBUS_UDID_WORD1_OFFSET		0xE0
820#define THC_I2C_IC_SMBUS_UDID_WORD2_OFFSET		0xE4
821#define THC_I2C_IC_SMBUS_UDID_WORD3_OFFSET		0xE8
822#define THC_I2C_IC_COMP_PARAM_1_OFFSET			0xF4
823#define THC_I2C_IC_COMP_VERSION_OFFSET			0xF8
824#define THC_I2C_IC_COMP_TYPE_OFFSET			0xFC
825
826/**
827 * THC I2C sub-system supported speed mode
828 */
829enum THC_I2C_SPEED_MODE {
830	THC_I2C_STANDARD = 1,
831	THC_I2C_FAST_AND_PLUS = 2,
832	THC_I2C_HIGH_SPEED = 3,
833};
834
835/* THC I2C sub-system register bits definition */
836#define THC_I2C_IC_ENABLE_ENABLE			BIT(0)
837#define THC_I2C_IC_ENABLE_ABORT				BIT(1)
838#define THC_I2C_IC_ENABLE_TX_CMD_BLOCK			BIT(2)
839#define THC_I2C_IC_ENABLE_SDA_STUCK_RECOVERY_ENABLE	BIT(3)
840#define THC_I2C_IC_ENABLE_SMBUS_CLK_RESET		BIT(16)
841#define THC_I2C_IC_ENABLE_SMBUS_SUSPEND_EN		BIT(17)
842#define THC_I2C_IC_ENABLE_SMBUS_ALERT_EN		BIT(18)
843
844#define THC_I2C_IC_CON_MASTER_MODE			BIT(0)
845#define THC_I2C_IC_CON_SPEED				GENMASK(2, 1)
846#define THC_I2C_IC_CON_IC_10BITADDR_SLAVE		BIT(3)
847#define THC_I2C_IC_CON_IC_10BITADDR_MASTER		BIT(4)
848#define THC_I2C_IC_CON_IC_RESTART_EN			BIT(5)
849#define THC_I2C_IC_CON_IC_SLAVE_DISABLE			BIT(6)
850#define THC_I2C_IC_CON_STOP_DET_IFADDRESSED		BIT(7)
851#define THC_I2C_IC_CON_TX_EMPTY_CTRL			BIT(8)
852#define THC_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL		BIT(9)
853#define THC_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE	BIT(10)
854#define THC_I2C_IC_CON_BUS_CLEAR_FEATURE_CTRL		BIT(11)
855#define THC_I2C_IC_CON_OPTIONAL_SAR_CTRL		BIT(16)
856#define THC_I2C_IC_CON_SMBUS_SLAVE_QUICK_EN		BIT(17)
857#define THC_I2C_IC_CON_SMBUS_ARP_EN			BIT(18)
858#define THC_I2C_IC_CON_SMBUS_PERSISTENT_SLV_ADDR_EN	BIT(19)
859
860#define THC_I2C_IC_TAR_IC_TAR				GENMASK(9, 0)
861#define THC_I2C_IC_TAR_GC_OR_START			BIT(10)
862#define THC_I2C_IC_TAR_SPECIAL				BIT(11)
863#define THC_I2C_IC_TAR_IC_10BITADDR_MASTER		BIT(12)
864#define THC_I2C_IC_TAR_DEVICE_ID			BIT(13)
865#define THC_I2C_IC_TAR_SMBUS_QUICK_CMD			BIT(16)
866
867#define THC_I2C_IC_INTR_MASK_M_RX_UNDER			BIT(0)
868#define THC_I2C_IC_INTR_MASK_M_RX_OVER			BIT(1)
869#define THC_I2C_IC_INTR_MASK_M_RX_FULL			BIT(2)
870#define THC_I2C_IC_INTR_MASK_M_TX_OVER			BIT(3)
871#define THC_I2C_IC_INTR_MASK_M_TX_EMPTY			BIT(4)
872#define THC_I2C_IC_INTR_MASK_M_RD_REQ			BIT(5)
873#define THC_I2C_IC_INTR_MASK_M_TX_ABRT			BIT(6)
874#define THC_I2C_IC_INTR_MASK_M_RX_DONE			BIT(7)
875#define THC_I2C_IC_INTR_MASK_M_ACTIVITY			BIT(8)
876#define THC_I2C_IC_INTR_MASK_M_STOP_DET			BIT(9)
877#define THC_I2C_IC_INTR_MASK_M_START_DET		BIT(10)
878#define THC_I2C_IC_INTR_MASK_M_GEN_CALL			BIT(11)
879#define THC_I2C_IC_INTR_MASK_M_RESTART_DET		BIT(12)
880#define THC_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD		BIT(13)
881#define THC_I2C_IC_INTR_MASK_M_SCL_STUCK_AT_LOW		BIT(14)
882
883#define THC_I2C_IC_DMA_CR_RDMAE				BIT(0)
884#define THC_I2C_IC_DMA_CR_TDMAE				BIT(1)
885
886#endif /* _INTEL_THC_HW_H_  */