quicki2c-dev.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2024 Intel Corporation */
  3
  4#ifndef _QUICKI2C_DEV_H_
  5#define _QUICKI2C_DEV_H_
  6
  7#include <linux/hid-over-i2c.h>
  8#include <linux/workqueue.h>
  9
 10#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT1		0xA848
 11#define PCI_DEVICE_ID_INTEL_THC_LNL_DEVICE_ID_I2C_PORT2		0xA84A
 12#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT1	0xE348
 13#define PCI_DEVICE_ID_INTEL_THC_PTL_H_DEVICE_ID_I2C_PORT2	0xE34A
 14#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT1	0xE448
 15#define PCI_DEVICE_ID_INTEL_THC_PTL_U_DEVICE_ID_I2C_PORT2	0xE44A
 16#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT1 	0x4D48
 17#define PCI_DEVICE_ID_INTEL_THC_WCL_DEVICE_ID_I2C_PORT2 	0x4D4A
 18
 19/* Packet size value, the unit is 16 bytes */
 20#define MAX_PACKET_SIZE_VALUE_LNL			256
 21
 22/* HIDI2C special ACPI parameters DSD name */
 23#define QUICKI2C_ACPI_METHOD_NAME_ICRS		"ICRS"
 24#define QUICKI2C_ACPI_METHOD_NAME_ISUB		"ISUB"
 25
 26/* HIDI2C special ACPI parameters DSM methods */
 27#define QUICKI2C_ACPI_REVISION_NUM		1
 28#define QUICKI2C_ACPI_FUNC_NUM_HID_DESC_ADDR	1
 29#define QUICKI2C_ACPI_FUNC_NUM_ACTIVE_LTR_VAL	1
 30#define QUICKI2C_ACPI_FUNC_NUM_LP_LTR_VAL	2
 31
 32#define QUICKI2C_SUBIP_STANDARD_MODE_MAX_SPEED		100000
 33#define QUICKI2C_SUBIP_FAST_MODE_MAX_SPEED		400000
 34#define QUICKI2C_SUBIP_FASTPLUS_MODE_MAX_SPEED		1000000
 35#define QUICKI2C_SUBIP_HIGH_SPEED_MODE_MAX_SPEED	3400000
 36
 37#define QUICKI2C_DEFAULT_ACTIVE_LTR_VALUE	5
 38#define QUICKI2C_DEFAULT_LP_LTR_VALUE		500
 39#define QUICKI2C_RPM_TIMEOUT_MS			500
 40
 41/* PTL Max packet size detection capability is 255 Bytes */
 42#define MAX_RX_DETECT_SIZE_PTL			255
 43/* Max interrupt delay capability is 2.56ms */
 44#define MAX_RX_INTERRUPT_DELAY			256
 45
 46/* Default interrupt delay is 1ms, suitable for most devices */
 47#define DEFAULT_INTERRUPT_DELAY_US		(1 * USEC_PER_MSEC)
 48
 49/*
 50 * THC uses runtime auto suspend to dynamically switch between THC active LTR
 51 * and low power LTR to save CPU power.
 52 * Default value is 5000ms, that means if no touch event in this time, THC will
 53 * change to low power LTR mode.
 54 */
 55#define DEFAULT_AUTO_SUSPEND_DELAY_MS			5000
 56
 57enum quicki2c_dev_state {
 58	QUICKI2C_NONE,
 59	QUICKI2C_RESETING,
 60	QUICKI2C_RESETED,
 61	QUICKI2C_INITED,
 62	QUICKI2C_ENABLED,
 63	QUICKI2C_DISABLED,
 64};
 65
 66enum {
 67	HIDI2C_ADDRESSING_MODE_7BIT,
 68	HIDI2C_ADDRESSING_MODE_10BIT,
 69};
 70
 71/**
 72 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
 73 * @device_address: I2C device slave address
 74 * @connection_speed: I2C device expected connection speed
 75 * @addressing_mode: I2C device slave address mode, 7bit or 10bit
 76 *
 77 * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ICRS method, used for
 78 * Bus parameter.
 79 */
 80struct quicki2c_subip_acpi_parameter {
 81	u16 device_address;
 82	u64 connection_speed;
 83	u8 addressing_mode;
 84	u8 reserved;
 85} __packed;
 86
 87/**
 88 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
 89 * @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period
 90 * @SMLX: Standard Mode (100 kbit/s) Serial Clock Line LOW Period
 91 * @SMTD: Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period
 92 * @SMRD: Standard Mode (100 kbit/s) Serial Data Receive Hold Period
 93 * @FMHX: Fast Mode (400 kbit/s) Serial Clock Line HIGH Period
 94 * @FMLX: Fast Mode (400 kbit/s) Serial Clock Line LOW Period
 95 * @FMTD: Fast Mode (400 kbit/s) Serial Data Line Transmit Hold Period
 96 * @FMRD: Fast Mode (400 kbit/s) Serial Data Line Receive Hold Period
 97 * @FMSL: Maximum length (in ic_clk_cycles) of suppressed spikes
 98 *        in Standard Mode, Fast Mode and Fast Mode Plus
 99 * @FPHX: Fast Mode Plus (1Mbit/sec) Serial Clock Line HIGH Period
100 * @FPLX: Fast Mode Plus (1Mbit/sec) Serial Clock Line LOW Period
101 * @FPTD: Fast Mode Plus (1Mbit/sec) Serial Data Line Transmit HOLD Period
102 * @FPRD: Fast Mode Plus (1Mbit/sec) Serial Data Line Receive HOLD Period
103 * @HMHX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line HIGH Period
104 * @HMLX: High Speed Mode Plus (3.4Mbits/sec) Serial Clock Line LOW Period
105 * @HMTD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Transmit HOLD Period
106 * @HMRD: High Speed Mode Plus (3.4Mbits/sec) Serial Data Line Receive HOLD Period
107 * @HMSL: Maximum length (in ic_clk_cycles) of suppressed spikes in High Speed Mode
108 * @FSEN: Maximum Frame Size Feature Enable Control
109 * @FSVL: Maximum Frame Size Value (unit in Bytes)
110 * @INDE: Interrupt Delay Feature Enable Control
111 * @INDV: Interrupt Delay Value (unit in 10 us)
112 *
113 * Those properties get from QUICKI2C_ACPI_METHOD_NAME_ISUB method, used for
114 * I2C timing configure.
115 */
116struct quicki2c_subip_acpi_config {
117	u64 SMHX;
118	u64 SMLX;
119	u64 SMTD;
120	u64 SMRD;
121
122	u64 FMHX;
123	u64 FMLX;
124	u64 FMTD;
125	u64 FMRD;
126	u64 FMSL;
127
128	u64 FPHX;
129	u64 FPLX;
130	u64 FPTD;
131	u64 FPRD;
132
133	u64 HMHX;
134	u64 HMLX;
135	u64 HMTD;
136	u64 HMRD;
137	u64 HMSL;
138
139	u64 FSEN;
140	u64 FSVL;
141	u64 INDE;
142	u64 INDV;
143	u8 reserved;
144};
145
146/**
147 * struct quicki2c_ddata - Driver specific data for quicki2c device
148 * @max_detect_size: Identify max packet size detect for rx
149 * @interrupt_delay: Identify max interrupt detect delay for rx
150 */
151struct quicki2c_ddata {
152	u32 max_detect_size;
153	u32 max_interrupt_delay;
154};
155
156struct device;
157struct pci_dev;
158struct thc_device;
159struct hid_device;
160struct acpi_device;
161
162/**
163 * struct quicki2c_device -  THC QuickI2C device struct
164 * @dev: Point to kernel device
165 * @pdev: Point to PCI device
166 * @thc_hw: Point to THC device
167 * @hid_dev: Point to HID device
168 * @acpi_dev: Point to ACPI device
169 * @ddata: Point to QuickI2C platform specific driver data
170 * @state: THC I2C device state
171 * @mem_addr: MMIO memory address
172 * @dev_desc: Device descriptor for HIDI2C protocol
173 * @i2c_slave_addr: HIDI2C device slave address
174 * @hid_desc_addr: Register address for retrieve HID device descriptor
175 * @active_ltr_val: THC active LTR value
176 * @low_power_ltr_val: THC low power LTR value
177 * @i2c_speed_mode: 0 - standard mode, 1 - fast mode, 2 - fast mode plus
178 * @i2c_clock_hcnt: I2C CLK high period time (unit in cycle count)
179 * @i2c_clock_lcnt: I2C CLK low period time (unit in cycle count)
180 * @report_descriptor: Store a copy of device report descriptor
181 * @input_buf: Store a copy of latest input report data
182 * @report_buf: Store a copy of latest input/output report packet from set/get feature
183 * @report_len: The length of input/output report packet
184 * @reset_ack_wq: Workqueue for waiting reset response from device
185 * @reset_ack: Indicate reset response received or not
186 * @i2c_max_frame_size_enable: Indicate max frame size feature enabled or not
187 * @i2c_max_frame_size: Max RX frame size (unit in Bytes)
188 * @i2c_int_delay_enable: Indicate interrupt delay feature enabled or not
189 * @i2c_int_delay: Interrupt detection delay value (unit in 10 us)
190 */
191struct quicki2c_device {
192	struct device *dev;
193	struct pci_dev *pdev;
194	struct thc_device *thc_hw;
195	struct hid_device *hid_dev;
196	struct acpi_device *acpi_dev;
197	const struct quicki2c_ddata *ddata;
198	enum quicki2c_dev_state state;
199
200	void __iomem *mem_addr;
201
202	struct hidi2c_dev_descriptor dev_desc;
203	u8 i2c_slave_addr;
204	u16 hid_desc_addr;
205
206	u32 active_ltr_val;
207	u32 low_power_ltr_val;
208
209	u32 i2c_speed_mode;
210	u32 i2c_clock_hcnt;
211	u32 i2c_clock_lcnt;
212
213	u8 *report_descriptor;
214	u8 *input_buf;
215	u8 *report_buf;
216	u32 report_len;
217
218	wait_queue_head_t reset_ack_wq;
219	bool reset_ack;
220
221	u32 i2c_max_frame_size_enable;
222	u32 i2c_max_frame_size;
223	u32 i2c_int_delay_enable;
224	u32 i2c_int_delay;
225};
226
227#endif /* _QUICKI2C_DEV_H_ */