amd_sfh_interface.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * AMD MP2 1.1 communication interfaces
  4 *
  5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
  9 */
 10
 11#ifndef AMD_SFH_INTERFACE_H
 12#define AMD_SFH_INTERFACE_H
 13
 14#include "../amd_sfh_common.h"
 15
 16#define SENSOR_DATA_MEM_SIZE_DEFAULT		256
 17#define TOTAL_STATIC_MEM_DEFAULT		1024
 18#define OFFSET_SFH_INFO_BASE_DEFAULT		0
 19#define OFFSET_SENSOR_DATA_DEFAULT		(OFFSET_SFH_INFO_BASE_DEFAULT + \
 20							TOTAL_STATIC_MEM_DEFAULT)
 21enum sensor_index {
 22	ACCEL_IDX,
 23	GYRO_IDX,
 24	MAG_IDX,
 25	SRA_IDX,
 26	ALS_IDX,
 27	HPD_IDX,
 28	MAX_IDX = 15,
 29};
 30
 31struct sfh_cmd_base {
 32	union {
 33		u32 ul;
 34		struct {
 35			u32 sensor_id		: 4;
 36			u32 cmd_id		: 4;
 37			u32 sub_cmd_id		: 8;
 38			u32 sub_cmd_value	: 12;
 39			u32 rsvd		: 3;
 40			u32 intr_disable	: 1;
 41		} cmd;
 42	};
 43};
 44
 45struct sfh_cmd_response {
 46	union {
 47		u32 resp;
 48		struct {
 49			u32 response	: 8;
 50			u32 sensor_id	: 4;
 51			u32 cmd_id	: 4;
 52			u32 sub_cmd	: 6;
 53			u32 rsvd2	: 10;
 54		} response;
 55	};
 56};
 57
 58struct sfh_platform_info {
 59	union {
 60		u32 pi;
 61		struct {
 62			u32 cust_id		: 16;
 63			u32 plat_id		: 6;
 64			u32 interface_id	: 4;
 65			u32 rsvd		: 6;
 66		} pinfo;
 67	};
 68};
 69
 70struct sfh_firmware_info {
 71	union {
 72		u32 fw_ver;
 73		struct {
 74			u32 minor_rev : 8;
 75			u32 major_rev : 8;
 76			u32 minor_ver : 8;
 77			u32 major_ver : 8;
 78		} fver;
 79	};
 80};
 81
 82struct sfh_sensor_list {
 83	union {
 84		u32 slist;
 85		struct {
 86			u32 sensors	: 16;
 87			u32 rsvd	: 16;
 88		} sl;
 89	};
 90};
 91
 92struct sfh_sensor_prop {
 93	union {
 94		u32 sprop;
 95		struct {
 96			u32 elist	: 16;
 97			u32 feat	: 16;
 98		} sf;
 99	};
100};
101
102struct sfh_base_info {
103	union {
104		u32 sfh_base[24];
105		struct {
106			struct sfh_platform_info plat_info;
107			struct sfh_firmware_info  fw_info;
108			struct sfh_sensor_list s_list;
109			u32 rsvd;
110			struct sfh_sensor_prop s_prop[16];
111		} sbase;
112	};
113};
114
115struct sfh_common_data {
116	u64 timestamp;
117	u32 intr_cnt;
118	u32 featvalid		: 16;
119	u32 rsvd		: 13;
120	u32 sensor_state	: 3;
121};
122
123struct sfh_float32 {
124	u32 x;
125	u32 y;
126	u32 z;
127};
128
129struct sfh_accel_data {
130	struct sfh_common_data commondata;
131	struct sfh_float32 acceldata;
132	u32 accelstatus;
133};
134
135struct sfh_gyro_data {
136	struct sfh_common_data commondata;
137	struct sfh_float32 gyrodata;
138	u32 result;
139};
140
141struct sfh_mag_data {
142	struct sfh_common_data commondata;
143	struct sfh_float32 magdata;
144	u32 accuracy;
145};
146
147struct sfh_als_data {
148	struct sfh_common_data commondata;
149	u32 lux;
150	u32 light_color_temp;
151	u32 chromaticity_x;
152	u32 chromaticity_y;
153};
154
155struct hpd_status {
156	union {
157		struct {
158			u32 distance			: 16;
159			u32 probablity			: 8;
160			u32 presence			: 2;
161			u32 rsvd			: 5;
162			u32 state			: 1;
163		} shpd;
164		u32 val;
165	};
166};
167
168struct sfh_op_mode {
169	union {
170		u32 val;
171		struct {
172			u32 mode		: 3;
173			u32 lidstatus		: 1;
174			u32 angle		: 10;
175			u32 inbagstatedbg	: 2;
176			u32 ontablestate	: 2;
177			u32 inbagstate		: 2;
178			u32 outbagstate		: 2;
179			u32 inbagmlcstate	: 1;
180			u32 powerstate		: 2;
181			u32 data		: 3;
182			u32 devicemode		: 4;
183		} op_mode;
184	};
185};
186
187void sfh_interface_init(struct amd_mp2_dev *mp2);
188void sfh_deinit_emp2(void);
189void amd_sfh1_1_set_desc_ops(struct amd_mp2_ops *mp2_ops);
190int amd_sfh_float_to_int(u32 flt32_val);
191#endif