bindings.rs

  1// SPDX-License-Identifier: GPL-2.0
  2
  3#[repr(C)]
  4#[derive(Default)]
  5pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]);
  6impl<T> __IncompleteArrayField<T> {
  7    #[inline]
  8    pub const fn new() -> Self {
  9        __IncompleteArrayField(::core::marker::PhantomData, [])
 10    }
 11    #[inline]
 12    pub fn as_ptr(&self) -> *const T {
 13        self as *const _ as *const T
 14    }
 15    #[inline]
 16    pub fn as_mut_ptr(&mut self) -> *mut T {
 17        self as *mut _ as *mut T
 18    }
 19    #[inline]
 20    pub unsafe fn as_slice(&self, len: usize) -> &[T] {
 21        ::core::slice::from_raw_parts(self.as_ptr(), len)
 22    }
 23    #[inline]
 24    pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] {
 25        ::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len)
 26    }
 27}
 28impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> {
 29    fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
 30        fmt.write_str("__IncompleteArrayField")
 31    }
 32}
 33pub const NV_VGPU_MSG_SIGNATURE_VALID: u32 = 1129337430;
 34pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 = 0;
 35pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 = 23068672;
 36pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 = 8388608;
 37pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 = 98304;
 38pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 = 100663296;
 39pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 = 64;
 40pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 = 256;
 41pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 = 88;
 42pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 = 280;
 43pub const GSP_FW_WPR_META_REVISION: u32 = 1;
 44pub const GSP_FW_WPR_META_MAGIC: i64 = -2577556379034558285;
 45pub const REGISTRY_TABLE_ENTRY_TYPE_DWORD: u32 = 1;
 46pub type __u8 = ffi::c_uchar;
 47pub type __u16 = ffi::c_ushort;
 48pub type __u32 = ffi::c_uint;
 49pub type __u64 = ffi::c_ulonglong;
 50pub type u8_ = __u8;
 51pub type u16_ = __u16;
 52pub type u32_ = __u32;
 53pub type u64_ = __u64;
 54pub const NV_VGPU_MSG_FUNCTION_NOP: _bindgen_ty_2 = 0;
 55pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO: _bindgen_ty_2 = 1;
 56pub const NV_VGPU_MSG_FUNCTION_ALLOC_ROOT: _bindgen_ty_2 = 2;
 57pub const NV_VGPU_MSG_FUNCTION_ALLOC_DEVICE: _bindgen_ty_2 = 3;
 58pub const NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY: _bindgen_ty_2 = 4;
 59pub const NV_VGPU_MSG_FUNCTION_ALLOC_CTX_DMA: _bindgen_ty_2 = 5;
 60pub const NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA: _bindgen_ty_2 = 6;
 61pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY: _bindgen_ty_2 = 7;
 62pub const NV_VGPU_MSG_FUNCTION_BIND_CTX_DMA: _bindgen_ty_2 = 8;
 63pub const NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT: _bindgen_ty_2 = 9;
 64pub const NV_VGPU_MSG_FUNCTION_FREE: _bindgen_ty_2 = 10;
 65pub const NV_VGPU_MSG_FUNCTION_LOG: _bindgen_ty_2 = 11;
 66pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIDMEM: _bindgen_ty_2 = 12;
 67pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY: _bindgen_ty_2 = 13;
 68pub const NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA: _bindgen_ty_2 = 14;
 69pub const NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA: _bindgen_ty_2 = 15;
 70pub const NV_VGPU_MSG_FUNCTION_GET_EDID: _bindgen_ty_2 = 16;
 71pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_CHANNEL: _bindgen_ty_2 = 17;
 72pub const NV_VGPU_MSG_FUNCTION_ALLOC_DISP_OBJECT: _bindgen_ty_2 = 18;
 73pub const NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE: _bindgen_ty_2 = 19;
 74pub const NV_VGPU_MSG_FUNCTION_ALLOC_DYNAMIC_MEMORY: _bindgen_ty_2 = 20;
 75pub const NV_VGPU_MSG_FUNCTION_DUP_OBJECT: _bindgen_ty_2 = 21;
 76pub const NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS: _bindgen_ty_2 = 22;
 77pub const NV_VGPU_MSG_FUNCTION_ALLOC_EVENT: _bindgen_ty_2 = 23;
 78pub const NV_VGPU_MSG_FUNCTION_SEND_EVENT: _bindgen_ty_2 = 24;
 79pub const NV_VGPU_MSG_FUNCTION_REMAPPER_CONTROL: _bindgen_ty_2 = 25;
 80pub const NV_VGPU_MSG_FUNCTION_DMA_CONTROL: _bindgen_ty_2 = 26;
 81pub const NV_VGPU_MSG_FUNCTION_DMA_FILL_PTE_MEM: _bindgen_ty_2 = 27;
 82pub const NV_VGPU_MSG_FUNCTION_MANAGE_HW_RESOURCE: _bindgen_ty_2 = 28;
 83pub const NV_VGPU_MSG_FUNCTION_BIND_ARBITRARY_CTX_DMA: _bindgen_ty_2 = 29;
 84pub const NV_VGPU_MSG_FUNCTION_CREATE_FB_SEGMENT: _bindgen_ty_2 = 30;
 85pub const NV_VGPU_MSG_FUNCTION_DESTROY_FB_SEGMENT: _bindgen_ty_2 = 31;
 86pub const NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE: _bindgen_ty_2 = 32;
 87pub const NV_VGPU_MSG_FUNCTION_DEFERRED_API_CONTROL: _bindgen_ty_2 = 33;
 88pub const NV_VGPU_MSG_FUNCTION_REMOVE_DEFERRED_API: _bindgen_ty_2 = 34;
 89pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_READ: _bindgen_ty_2 = 35;
 90pub const NV_VGPU_MSG_FUNCTION_SIM_ESCAPE_WRITE: _bindgen_ty_2 = 36;
 91pub const NV_VGPU_MSG_FUNCTION_SIM_MANAGE_DISPLAY_CONTEXT_DMA: _bindgen_ty_2 = 37;
 92pub const NV_VGPU_MSG_FUNCTION_FREE_VIDMEM_VIRT: _bindgen_ty_2 = 38;
 93pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PSTATE_INFO: _bindgen_ty_2 = 39;
 94pub const NV_VGPU_MSG_FUNCTION_PERF_GET_PERFMON_SAMPLE: _bindgen_ty_2 = 40;
 95pub const NV_VGPU_MSG_FUNCTION_PERF_GET_VIRTUAL_PSTATE_INFO: _bindgen_ty_2 = 41;
 96pub const NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO: _bindgen_ty_2 = 42;
 97pub const NV_VGPU_MSG_FUNCTION_MAP_SEMA_MEMORY: _bindgen_ty_2 = 43;
 98pub const NV_VGPU_MSG_FUNCTION_UNMAP_SEMA_MEMORY: _bindgen_ty_2 = 44;
 99pub const NV_VGPU_MSG_FUNCTION_SET_SURFACE_PROPERTIES: _bindgen_ty_2 = 45;
100pub const NV_VGPU_MSG_FUNCTION_CLEANUP_SURFACE: _bindgen_ty_2 = 46;
101pub const NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER: _bindgen_ty_2 = 47;
102pub const NV_VGPU_MSG_FUNCTION_TDR_SET_TIMEOUT_STATE: _bindgen_ty_2 = 48;
103pub const NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA: _bindgen_ty_2 = 49;
104pub const NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS: _bindgen_ty_2 = 50;
105pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO: _bindgen_ty_2 = 51;
106pub const NV_VGPU_MSG_FUNCTION_ALLOC_VIRTMEM: _bindgen_ty_2 = 52;
107pub const NV_VGPU_MSG_FUNCTION_UPDATE_PDE_2: _bindgen_ty_2 = 53;
108pub const NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY: _bindgen_ty_2 = 54;
109pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_PSTATE_INFO: _bindgen_ty_2 = 55;
110pub const NV_VGPU_MSG_FUNCTION_TRANSLATE_GUEST_GPU_PTES: _bindgen_ty_2 = 56;
111pub const NV_VGPU_MSG_FUNCTION_RESERVED_57: _bindgen_ty_2 = 57;
112pub const NV_VGPU_MSG_FUNCTION_RESET_CURRENT_GR_CONTEXT: _bindgen_ty_2 = 58;
113pub const NV_VGPU_MSG_FUNCTION_SET_SEMA_MEM_VALIDATION_STATE: _bindgen_ty_2 = 59;
114pub const NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION: _bindgen_ty_2 = 60;
115pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPU_PDES: _bindgen_ty_2 = 61;
116pub const NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY: _bindgen_ty_2 = 62;
117pub const NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32: _bindgen_ty_2 = 63;
118pub const NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT: _bindgen_ty_2 = 64;
119pub const NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO: _bindgen_ty_2 = 65;
120pub const NV_VGPU_MSG_FUNCTION_RMFS_INIT: _bindgen_ty_2 = 66;
121pub const NV_VGPU_MSG_FUNCTION_RMFS_CLOSE_QUEUE: _bindgen_ty_2 = 67;
122pub const NV_VGPU_MSG_FUNCTION_RMFS_CLEANUP: _bindgen_ty_2 = 68;
123pub const NV_VGPU_MSG_FUNCTION_RMFS_TEST: _bindgen_ty_2 = 69;
124pub const NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE: _bindgen_ty_2 = 70;
125pub const NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD: _bindgen_ty_2 = 71;
126pub const NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO: _bindgen_ty_2 = 72;
127pub const NV_VGPU_MSG_FUNCTION_SET_REGISTRY: _bindgen_ty_2 = 73;
128pub const NV_VGPU_MSG_FUNCTION_GSP_INIT_POST_OBJGPU: _bindgen_ty_2 = 74;
129pub const NV_VGPU_MSG_FUNCTION_SUBDEV_EVENT_SET_NOTIFICATION: _bindgen_ty_2 = 75;
130pub const NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: _bindgen_ty_2 = 76;
131pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_INFO2: _bindgen_ty_2 = 77;
132pub const NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT: _bindgen_ty_2 = 78;
133pub const NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY: _bindgen_ty_2 = 79;
134pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_STATIC_INFO: _bindgen_ty_2 = 80;
135pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_FAULT_BUFFER: _bindgen_ty_2 = 81;
136pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_FAULT_BUFFER: _bindgen_ty_2 = 82;
137pub const NV_VGPU_MSG_FUNCTION_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER: _bindgen_ty_2 = 83;
138pub const NV_VGPU_MSG_FUNCTION_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER: _bindgen_ty_2 = 84;
139pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_VGPU_FB_USAGE: _bindgen_ty_2 = 85;
140pub const NV_VGPU_MSG_FUNCTION_CTRL_NVFBC_SW_SESSION_UPDATE_INFO: _bindgen_ty_2 = 86;
141pub const NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO: _bindgen_ty_2 = 87;
142pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL: _bindgen_ty_2 = 88;
143pub const NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL: _bindgen_ty_2 = 89;
144pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT: _bindgen_ty_2 = 90;
145pub const NV_VGPU_MSG_FUNCTION_CTRL_CLK_GET_EXTENDED_INFO: _bindgen_ty_2 = 91;
146pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST: _bindgen_ty_2 = 92;
147pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_VPSTATES_GET_CONTROL: _bindgen_ty_2 = 93;
148pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE: _bindgen_ty_2 = 94;
149pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR: _bindgen_ty_2 = 95;
150pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR: _bindgen_ty_2 = 96;
151pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE: _bindgen_ty_2 = 97;
152pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE: _bindgen_ty_2 = 98;
153pub const NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT: _bindgen_ty_2 = 99;
154pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS: _bindgen_ty_2 = 100;
155pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL: _bindgen_ty_2 = 101;
156pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL: _bindgen_ty_2 = 102;
157pub const NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: _bindgen_ty_2 = 103;
158pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2: _bindgen_ty_2 = 104;
159pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_AES_ENCRYPT: _bindgen_ty_2 = 105;
160pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY: _bindgen_ty_2 = 106;
161pub const NV_VGPU_MSG_FUNCTION_CTRL_CIPHER_SESSION_KEY_STATUS: _bindgen_ty_2 = 107;
162pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES: _bindgen_ty_2 = 108;
163pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES: _bindgen_ty_2 = 109;
164pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK: _bindgen_ty_2 = 110;
165pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX: _bindgen_ty_2 = 111;
166pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND: _bindgen_ty_2 = 112;
167pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE: _bindgen_ty_2 = 113;
168pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND: _bindgen_ty_2 = 114;
169pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX: _bindgen_ty_2 = 115;
170pub const NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES: _bindgen_ty_2 = 116;
171pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_CLEAR_FAULTED_BIT: _bindgen_ty_2 = 117;
172pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_LATEST_ECC_ADDRESSES: _bindgen_ty_2 = 118;
173pub const NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS: _bindgen_ty_2 = 119;
174pub const NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE: _bindgen_ty_2 = 120;
175pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK: _bindgen_ty_2 = 121;
176pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY: _bindgen_ty_2 = 122;
177pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK: _bindgen_ty_2 = 123;
178pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS: _bindgen_ty_2 = 124;
179pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS: _bindgen_ty_2 = 125;
180pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX: _bindgen_ty_2 = 126;
181pub const NV_VGPU_MSG_FUNCTION_RESERVED_0: _bindgen_ty_2 = 127;
182pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC: _bindgen_ty_2 = 128;
183pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY: _bindgen_ty_2 = 129;
184pub const NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS: _bindgen_ty_2 = 130;
185pub const NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES: _bindgen_ty_2 = 131;
186pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT: _bindgen_ty_2 = 132;
187pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT: _bindgen_ty_2 = 133;
188pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS: _bindgen_ty_2 = 134;
189pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG: _bindgen_ty_2 = 135;
190pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE: _bindgen_ty_2 = 136;
191pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE: _bindgen_ty_2 = 137;
192pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG: _bindgen_ty_2 = 138;
193pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE: _bindgen_ty_2 = 139;
194pub const NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM: _bindgen_ty_2 = 140;
195pub const NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT: _bindgen_ty_2 = 141;
196pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2: _bindgen_ty_2 = 142;
197pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES: _bindgen_ty_2 = 143;
198pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = 144;
199pub const NV_VGPU_MSG_FUNCTION_CTRL_KGR_GET_CTX_BUFFER_PTES: _bindgen_ty_2 = 145;
200pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX: _bindgen_ty_2 = 146;
201pub const NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO: _bindgen_ty_2 = 147;
202pub const NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO: _bindgen_ty_2 = 148;
203pub const NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL: _bindgen_ty_2 = 149;
204pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE: _bindgen_ty_2 = 150;
205pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS: _bindgen_ty_2 = 151;
206pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL: _bindgen_ty_2 = 152;
207pub const NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM: _bindgen_ty_2 = 153;
208pub const NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ: _bindgen_ty_2 = 154;
209pub const NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB: _bindgen_ty_2 = 155;
210pub const NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO: _bindgen_ty_2 = 156;
211pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP: _bindgen_ty_2 = 157;
212pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE: _bindgen_ty_2 = 158;
213pub const NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE: _bindgen_ty_2 = 159;
214pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_ALLOCATE: _bindgen_ty_2 = 160;
215pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_DESTROY: _bindgen_ty_2 = 161;
216pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_MAP: _bindgen_ty_2 = 162;
217pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_UNMAP: _bindgen_ty_2 = 163;
218pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_PUSH_STREAM: _bindgen_ty_2 = 164;
219pub const NV_VGPU_MSG_FUNCTION_UVM_PAGING_CHANNEL_SET_HANDLES: _bindgen_ty_2 = 165;
220pub const NV_VGPU_MSG_FUNCTION_UVM_METHOD_STREAM_GUEST_PAGES_OPERATION: _bindgen_ty_2 = 166;
221pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL: _bindgen_ty_2 = 167;
222pub const NV_VGPU_MSG_FUNCTION_DCE_RM_INIT: _bindgen_ty_2 = 168;
223pub const NV_VGPU_MSG_FUNCTION_REGISTER_VIRTUAL_EVENT_BUFFER: _bindgen_ty_2 = 169;
224pub const NV_VGPU_MSG_FUNCTION_CTRL_EVENT_BUFFER_UPDATE_GET: _bindgen_ty_2 = 170;
225pub const NV_VGPU_MSG_FUNCTION_GET_PLCABLE_ADDRESS_KIND: _bindgen_ty_2 = 171;
226pub const NV_VGPU_MSG_FUNCTION_CTRL_PERF_LIMITS_SET_STATUS_V2: _bindgen_ty_2 = 172;
227pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM: _bindgen_ty_2 = 173;
228pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE: _bindgen_ty_2 = 174;
229pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS: _bindgen_ty_2 = 175;
230pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_SIZE: _bindgen_ty_2 = 176;
231pub const NV_VGPU_MSG_FUNCTION_CTRL_FLCN_GET_CTX_BUFFER_INFO: _bindgen_ty_2 = 177;
232pub const NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS: _bindgen_ty_2 = 178;
233pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE: _bindgen_ty_2 = 179;
234pub const NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS: _bindgen_ty_2 = 180;
235pub const NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA: _bindgen_ty_2 = 181;
236pub const NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA: _bindgen_ty_2 = 182;
237pub const NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED: _bindgen_ty_2 = 183;
238pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE: _bindgen_ty_2 = 184;
239pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE: _bindgen_ty_2 = 185;
240pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN: _bindgen_ty_2 = 186;
241pub const NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX: _bindgen_ty_2 = 187;
242pub const NV_VGPU_MSG_FUNCTION_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION: _bindgen_ty_2 =
243    188;
244pub const NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK:
245    _bindgen_ty_2 = 189;
246pub const NV_VGPU_MSG_FUNCTION_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER: _bindgen_ty_2 = 190;
247pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS: _bindgen_ty_2 = 191;
248pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING: _bindgen_ty_2 = 192;
249pub const NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING: _bindgen_ty_2 = 193;
250pub const NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK: _bindgen_ty_2 = 194;
251pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS: _bindgen_ty_2 = 195;
252pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS: _bindgen_ty_2 = 196;
253pub const NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS: _bindgen_ty_2 = 197;
254pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS: _bindgen_ty_2 = 198;
255pub const NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER: _bindgen_ty_2 = 199;
256pub const NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB: _bindgen_ty_2 = 200;
257pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_QUERY_ECC_STATUS: _bindgen_ty_2 = 201;
258pub const NV_VGPU_MSG_FUNCTION_ECC_NOTIFIER_WRITE_ACK: _bindgen_ty_2 = 202;
259pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG: _bindgen_ty_2 = 203;
260pub const NV_VGPU_MSG_FUNCTION_RM_API_CONTROL: _bindgen_ty_2 = 204;
261pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE: _bindgen_ty_2 = 205;
262pub const NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA: _bindgen_ty_2 = 206;
263pub const NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA: _bindgen_ty_2 = 207;
264pub const NV_VGPU_MSG_FUNCTION_RESERVED_208: _bindgen_ty_2 = 208;
265pub const NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2: _bindgen_ty_2 = 209;
266pub const NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS: _bindgen_ty_2 = 210;
267pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_NVLINK_INBAND_SEND_DATA: _bindgen_ty_2 = 211;
268pub const NV_VGPU_MSG_FUNCTION_UPDATE_GPM_GUEST_BUFFER_INFO: _bindgen_ty_2 = 212;
269pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE: _bindgen_ty_2 = 213;
270pub const NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_STENCIL_CLEAR: _bindgen_ty_2 = 214;
271pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS: _bindgen_ty_2 = 215;
272pub const NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS: _bindgen_ty_2 = 216;
273pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_GCC_DEBUG: _bindgen_ty_2 = 217;
274pub const NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_GCC_DEBUG: _bindgen_ty_2 = 218;
275pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HES: _bindgen_ty_2 = 219;
276pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_HES: _bindgen_ty_2 = 220;
277pub const NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_CCU_PROF: _bindgen_ty_2 = 221;
278pub const NV_VGPU_MSG_FUNCTION_CTRL_RELEASE_CCU_PROF: _bindgen_ty_2 = 222;
279pub const NV_VGPU_MSG_FUNCTION_RESERVED: _bindgen_ty_2 = 223;
280pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL: _bindgen_ty_2 = 224;
281pub const NV_VGPU_MSG_FUNCTION_CTRL_CMD_GET_HS_CREDITS_MAPPING: _bindgen_ty_2 = 225;
282pub const NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_EXPORT: _bindgen_ty_2 = 226;
283pub const NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS: _bindgen_ty_2 = 227;
284pub type _bindgen_ty_2 = ffi::c_uint;
285pub const NV_VGPU_MSG_EVENT_FIRST_EVENT: _bindgen_ty_3 = 4096;
286pub const NV_VGPU_MSG_EVENT_GSP_INIT_DONE: _bindgen_ty_3 = 4097;
287pub const NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: _bindgen_ty_3 = 4098;
288pub const NV_VGPU_MSG_EVENT_POST_EVENT: _bindgen_ty_3 = 4099;
289pub const NV_VGPU_MSG_EVENT_RC_TRIGGERED: _bindgen_ty_3 = 4100;
290pub const NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED: _bindgen_ty_3 = 4101;
291pub const NV_VGPU_MSG_EVENT_OS_ERROR_LOG: _bindgen_ty_3 = 4102;
292pub const NV_VGPU_MSG_EVENT_RG_LINE_INTR: _bindgen_ty_3 = 4103;
293pub const NV_VGPU_MSG_EVENT_GPUACCT_PERFMON_UTIL_SAMPLES: _bindgen_ty_3 = 4104;
294pub const NV_VGPU_MSG_EVENT_SIM_READ: _bindgen_ty_3 = 4105;
295pub const NV_VGPU_MSG_EVENT_SIM_WRITE: _bindgen_ty_3 = 4106;
296pub const NV_VGPU_MSG_EVENT_SEMAPHORE_SCHEDULE_CALLBACK: _bindgen_ty_3 = 4107;
297pub const NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT: _bindgen_ty_3 = 4108;
298pub const NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: _bindgen_ty_3 = 4109;
299pub const NV_VGPU_MSG_EVENT_PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK: _bindgen_ty_3 = 4110;
300pub const NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE: _bindgen_ty_3 = 4111;
301pub const NV_VGPU_MSG_EVENT_VGPU_CONFIG: _bindgen_ty_3 = 4112;
302pub const NV_VGPU_MSG_EVENT_DISPLAY_MODESET: _bindgen_ty_3 = 4113;
303pub const NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE: _bindgen_ty_3 = 4114;
304pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: _bindgen_ty_3 = 4115;
305pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512: _bindgen_ty_3 = 4116;
306pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024: _bindgen_ty_3 = 4117;
307pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048: _bindgen_ty_3 = 4118;
308pub const NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096: _bindgen_ty_3 = 4119;
309pub const NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE: _bindgen_ty_3 = 4120;
310pub const NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED: _bindgen_ty_3 = 4121;
311pub const NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK: _bindgen_ty_3 = 4122;
312pub const NV_VGPU_MSG_EVENT_NVLINK_FAULT_UP: _bindgen_ty_3 = 4123;
313pub const NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _bindgen_ty_3 = 4124;
314pub const NV_VGPU_MSG_EVENT_MIG_CI_CONFIG_UPDATE: _bindgen_ty_3 = 4125;
315pub const NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE: _bindgen_ty_3 = 4126;
316pub const NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY: _bindgen_ty_3 = 4127;
317pub const NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: _bindgen_ty_3 = 4128;
318pub const NV_VGPU_MSG_EVENT_FECS_ERROR: _bindgen_ty_3 = 4129;
319pub const NV_VGPU_MSG_EVENT_RECOVERY_ACTION: _bindgen_ty_3 = 4130;
320pub const NV_VGPU_MSG_EVENT_NUM_EVENTS: _bindgen_ty_3 = 4131;
321pub type _bindgen_ty_3 = ffi::c_uint;
322#[repr(C)]
323#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
324pub struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
325    pub totalVFs: u32_,
326    pub firstVfOffset: u32_,
327    pub vfFeatureMask: u32_,
328    pub __bindgen_padding_0: [u8; 4usize],
329    pub FirstVFBar0Address: u64_,
330    pub FirstVFBar1Address: u64_,
331    pub FirstVFBar2Address: u64_,
332    pub bar0Size: u64_,
333    pub bar1Size: u64_,
334    pub bar2Size: u64_,
335    pub b64bitBar0: u8_,
336    pub b64bitBar1: u8_,
337    pub b64bitBar2: u8_,
338    pub bSriovEnabled: u8_,
339    pub bSriovHeavyEnabled: u8_,
340    pub bEmulateVFBar0TlbInvalidationRegister: u8_,
341    pub bClientRmAllocatedCtxBuffer: u8_,
342    pub bNonPowerOf2ChannelCountSupported: u8_,
343    pub bVfResizableBAR1Supported: u8_,
344    pub __bindgen_padding_1: [u8; 7usize],
345}
346#[repr(C)]
347#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
348pub struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
349    pub BoardID: u32_,
350    pub chipSKU: [ffi::c_char; 9usize],
351    pub chipSKUMod: [ffi::c_char; 5usize],
352    pub __bindgen_padding_0: [u8; 2usize],
353    pub skuConfigVersion: u32_,
354    pub project: [ffi::c_char; 5usize],
355    pub projectSKU: [ffi::c_char; 5usize],
356    pub CDP: [ffi::c_char; 6usize],
357    pub projectSKUMod: [ffi::c_char; 2usize],
358    pub __bindgen_padding_1: [u8; 2usize],
359    pub businessCycle: u32_,
360}
361pub type NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = [u8_; 17usize];
362#[repr(C)]
363#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
364pub struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
365    pub base: u64_,
366    pub limit: u64_,
367    pub reserved: u64_,
368    pub performance: u32_,
369    pub supportCompressed: u8_,
370    pub supportISO: u8_,
371    pub bProtected: u8_,
372    pub blackList: NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG,
373}
374#[repr(C)]
375#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
376pub struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
377    pub numFBRegions: u32_,
378    pub __bindgen_padding_0: [u8; 4usize],
379    pub fbRegion: [NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; 16usize],
380}
381#[repr(C)]
382#[derive(Debug, Copy, Clone, MaybeZeroable)]
383pub struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
384    pub index: u32_,
385    pub flags: u32_,
386    pub length: u32_,
387    pub data: [u8_; 256usize],
388}
389impl Default for NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
390    fn default() -> Self {
391        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
392        unsafe {
393            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
394            s.assume_init()
395        }
396    }
397}
398#[repr(C)]
399#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
400pub struct DOD_METHOD_DATA {
401    pub status: u32_,
402    pub acpiIdListLen: u32_,
403    pub acpiIdList: [u32_; 16usize],
404}
405#[repr(C)]
406#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
407pub struct JT_METHOD_DATA {
408    pub status: u32_,
409    pub jtCaps: u32_,
410    pub jtRevId: u16_,
411    pub bSBIOSCaps: u8_,
412    pub __bindgen_padding_0: u8,
413}
414#[repr(C)]
415#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
416pub struct MUX_METHOD_DATA_ELEMENT {
417    pub acpiId: u32_,
418    pub mode: u32_,
419    pub status: u32_,
420}
421#[repr(C)]
422#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
423pub struct MUX_METHOD_DATA {
424    pub tableLen: u32_,
425    pub acpiIdMuxModeTable: [MUX_METHOD_DATA_ELEMENT; 16usize],
426    pub acpiIdMuxPartTable: [MUX_METHOD_DATA_ELEMENT; 16usize],
427    pub acpiIdMuxStateTable: [MUX_METHOD_DATA_ELEMENT; 16usize],
428}
429#[repr(C)]
430#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
431pub struct CAPS_METHOD_DATA {
432    pub status: u32_,
433    pub optimusCaps: u32_,
434}
435#[repr(C)]
436#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
437pub struct ACPI_METHOD_DATA {
438    pub bValid: u8_,
439    pub __bindgen_padding_0: [u8; 3usize],
440    pub dodMethodData: DOD_METHOD_DATA,
441    pub jtMethodData: JT_METHOD_DATA,
442    pub muxMethodData: MUX_METHOD_DATA,
443    pub capsMethodData: CAPS_METHOD_DATA,
444}
445#[repr(C)]
446#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
447pub struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS {
448    pub headIndex: u32_,
449    pub maxHResolution: u32_,
450    pub maxVResolution: u32_,
451}
452#[repr(C)]
453#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
454pub struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS {
455    pub numHeads: u32_,
456    pub maxNumHeads: u32_,
457}
458#[repr(C)]
459#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
460pub struct BUSINFO {
461    pub deviceID: u16_,
462    pub vendorID: u16_,
463    pub subdeviceID: u16_,
464    pub subvendorID: u16_,
465    pub revisionID: u8_,
466    pub __bindgen_padding_0: u8,
467}
468#[repr(C)]
469#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
470pub struct GSP_VF_INFO {
471    pub totalVFs: u32_,
472    pub firstVFOffset: u32_,
473    pub FirstVFBar0Address: u64_,
474    pub FirstVFBar1Address: u64_,
475    pub FirstVFBar2Address: u64_,
476    pub b64bitBar0: u8_,
477    pub b64bitBar1: u8_,
478    pub b64bitBar2: u8_,
479    pub __bindgen_padding_0: [u8; 5usize],
480}
481#[repr(C)]
482#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
483pub struct GSP_PCIE_CONFIG_REG {
484    pub linkCap: u32_,
485}
486#[repr(C)]
487#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
488pub struct EcidManufacturingInfo {
489    pub ecidLow: u32_,
490    pub ecidHigh: u32_,
491    pub ecidExtended: u32_,
492}
493#[repr(C)]
494#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
495pub struct FW_WPR_LAYOUT_OFFSET {
496    pub nonWprHeapOffset: u64_,
497    pub frtsOffset: u64_,
498}
499#[repr(C)]
500#[derive(Debug, Copy, Clone, MaybeZeroable)]
501pub struct GspStaticConfigInfo_t {
502    pub grCapsBits: [u8_; 23usize],
503    pub __bindgen_padding_0: u8,
504    pub gidInfo: NV2080_CTRL_GPU_GET_GID_INFO_PARAMS,
505    pub SKUInfo: NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS,
506    pub __bindgen_padding_1: [u8; 4usize],
507    pub fbRegionInfoParams: NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS,
508    pub sriovCaps: NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS,
509    pub sriovMaxGfid: u32_,
510    pub engineCaps: [u32_; 3usize],
511    pub poisonFuseEnabled: u8_,
512    pub __bindgen_padding_2: [u8; 7usize],
513    pub fb_length: u64_,
514    pub fbio_mask: u64_,
515    pub fb_bus_width: u32_,
516    pub fb_ram_type: u32_,
517    pub fbp_mask: u64_,
518    pub l2_cache_size: u32_,
519    pub gpuNameString: [u8_; 64usize],
520    pub gpuShortNameString: [u8_; 64usize],
521    pub gpuNameString_Unicode: [u16_; 64usize],
522    pub bGpuInternalSku: u8_,
523    pub bIsQuadroGeneric: u8_,
524    pub bIsQuadroAd: u8_,
525    pub bIsNvidiaNvs: u8_,
526    pub bIsVgx: u8_,
527    pub bGeforceSmb: u8_,
528    pub bIsTitan: u8_,
529    pub bIsTesla: u8_,
530    pub bIsMobile: u8_,
531    pub bIsGc6Rtd3Allowed: u8_,
532    pub bIsGc8Rtd3Allowed: u8_,
533    pub bIsGcOffRtd3Allowed: u8_,
534    pub bIsGcoffLegacyAllowed: u8_,
535    pub bIsMigSupported: u8_,
536    pub RTD3GC6TotalBoardPower: u16_,
537    pub RTD3GC6PerstDelay: u16_,
538    pub __bindgen_padding_3: [u8; 2usize],
539    pub bar1PdeBase: u64_,
540    pub bar2PdeBase: u64_,
541    pub bVbiosValid: u8_,
542    pub __bindgen_padding_4: [u8; 3usize],
543    pub vbiosSubVendor: u32_,
544    pub vbiosSubDevice: u32_,
545    pub bPageRetirementSupported: u8_,
546    pub bSplitVasBetweenServerClientRm: u8_,
547    pub bClRootportNeedsNosnoopWAR: u8_,
548    pub __bindgen_padding_5: u8,
549    pub displaylessMaxHeads: VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS,
550    pub displaylessMaxResolution: VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS,
551    pub __bindgen_padding_6: [u8; 4usize],
552    pub displaylessMaxPixels: u64_,
553    pub hInternalClient: u32_,
554    pub hInternalDevice: u32_,
555    pub hInternalSubdevice: u32_,
556    pub bSelfHostedMode: u8_,
557    pub bAtsSupported: u8_,
558    pub bIsGpuUefi: u8_,
559    pub bIsEfiInit: u8_,
560    pub ecidInfo: [EcidManufacturingInfo; 2usize],
561    pub fwWprLayoutOffset: FW_WPR_LAYOUT_OFFSET,
562}
563impl Default for GspStaticConfigInfo_t {
564    fn default() -> Self {
565        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
566        unsafe {
567            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
568            s.assume_init()
569        }
570    }
571}
572#[repr(C)]
573#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
574pub struct GspSystemInfo {
575    pub gpuPhysAddr: u64_,
576    pub gpuPhysFbAddr: u64_,
577    pub gpuPhysInstAddr: u64_,
578    pub gpuPhysIoAddr: u64_,
579    pub nvDomainBusDeviceFunc: u64_,
580    pub simAccessBufPhysAddr: u64_,
581    pub notifyOpSharedSurfacePhysAddr: u64_,
582    pub pcieAtomicsOpMask: u64_,
583    pub consoleMemSize: u64_,
584    pub maxUserVa: u64_,
585    pub pciConfigMirrorBase: u32_,
586    pub pciConfigMirrorSize: u32_,
587    pub PCIDeviceID: u32_,
588    pub PCISubDeviceID: u32_,
589    pub PCIRevisionID: u32_,
590    pub pcieAtomicsCplDeviceCapMask: u32_,
591    pub oorArch: u8_,
592    pub __bindgen_padding_0: [u8; 7usize],
593    pub clPdbProperties: u64_,
594    pub Chipset: u32_,
595    pub bGpuBehindBridge: u8_,
596    pub bFlrSupported: u8_,
597    pub b64bBar0Supported: u8_,
598    pub bMnocAvailable: u8_,
599    pub chipsetL1ssEnable: u32_,
600    pub bUpstreamL0sUnsupported: u8_,
601    pub bUpstreamL1Unsupported: u8_,
602    pub bUpstreamL1PorSupported: u8_,
603    pub bUpstreamL1PorMobileOnly: u8_,
604    pub bSystemHasMux: u8_,
605    pub upstreamAddressValid: u8_,
606    pub FHBBusInfo: BUSINFO,
607    pub chipsetIDInfo: BUSINFO,
608    pub __bindgen_padding_1: [u8; 2usize],
609    pub acpiMethodData: ACPI_METHOD_DATA,
610    pub hypervisorType: u32_,
611    pub bIsPassthru: u8_,
612    pub __bindgen_padding_2: [u8; 7usize],
613    pub sysTimerOffsetNs: u64_,
614    pub gspVFInfo: GSP_VF_INFO,
615    pub bIsPrimary: u8_,
616    pub isGridBuild: u8_,
617    pub __bindgen_padding_3: [u8; 2usize],
618    pub pcieConfigReg: GSP_PCIE_CONFIG_REG,
619    pub gridBuildCsp: u32_,
620    pub bPreserveVideoMemoryAllocations: u8_,
621    pub bTdrEventSupported: u8_,
622    pub bFeatureStretchVblankCapable: u8_,
623    pub bEnableDynamicGranularityPageArrays: u8_,
624    pub bClockBoostSupported: u8_,
625    pub bRouteDispIntrsToCPU: u8_,
626    pub __bindgen_padding_4: [u8; 6usize],
627    pub hostPageSize: u64_,
628}
629#[repr(C)]
630#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
631pub struct MESSAGE_QUEUE_INIT_ARGUMENTS {
632    pub sharedMemPhysAddr: u64_,
633    pub pageTableEntryCount: u32_,
634    pub __bindgen_padding_0: [u8; 4usize],
635    pub cmdQueueOffset: u64_,
636    pub statQueueOffset: u64_,
637}
638#[repr(C)]
639#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
640pub struct GSP_SR_INIT_ARGUMENTS {
641    pub oldLevel: u32_,
642    pub flags: u32_,
643    pub bInPMTransition: u8_,
644    pub __bindgen_padding_0: [u8; 3usize],
645}
646#[repr(C)]
647#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
648pub struct GSP_ARGUMENTS_CACHED {
649    pub messageQueueInitArguments: MESSAGE_QUEUE_INIT_ARGUMENTS,
650    pub srInitArguments: GSP_SR_INIT_ARGUMENTS,
651    pub gpuInstance: u32_,
652    pub bDmemStack: u8_,
653    pub __bindgen_padding_0: [u8; 7usize],
654    pub profilerArgs: GSP_ARGUMENTS_CACHED__bindgen_ty_1,
655}
656#[repr(C)]
657#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
658pub struct GSP_ARGUMENTS_CACHED__bindgen_ty_1 {
659    pub pa: u64_,
660    pub size: u64_,
661}
662#[repr(C)]
663#[derive(Copy, Clone, MaybeZeroable)]
664pub union rpc_message_rpc_union_field_v03_00 {
665    pub spare: u32_,
666    pub cpuRmGfid: u32_,
667}
668impl Default for rpc_message_rpc_union_field_v03_00 {
669    fn default() -> Self {
670        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
671        unsafe {
672            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
673            s.assume_init()
674        }
675    }
676}
677pub type rpc_message_rpc_union_field_v = rpc_message_rpc_union_field_v03_00;
678#[repr(C)]
679#[derive(MaybeZeroable)]
680pub struct rpc_message_header_v03_00 {
681    pub header_version: u32_,
682    pub signature: u32_,
683    pub length: u32_,
684    pub function: u32_,
685    pub rpc_result: u32_,
686    pub rpc_result_private: u32_,
687    pub sequence: u32_,
688    pub u: rpc_message_rpc_union_field_v,
689    pub rpc_message_data: __IncompleteArrayField<u8_>,
690}
691impl Default for rpc_message_header_v03_00 {
692    fn default() -> Self {
693        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
694        unsafe {
695            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
696            s.assume_init()
697        }
698    }
699}
700pub type rpc_message_header_v = rpc_message_header_v03_00;
701#[repr(C)]
702#[derive(Copy, Clone, MaybeZeroable)]
703pub struct GspFwWprMeta {
704    pub magic: u64_,
705    pub revision: u64_,
706    pub sysmemAddrOfRadix3Elf: u64_,
707    pub sizeOfRadix3Elf: u64_,
708    pub sysmemAddrOfBootloader: u64_,
709    pub sizeOfBootloader: u64_,
710    pub bootloaderCodeOffset: u64_,
711    pub bootloaderDataOffset: u64_,
712    pub bootloaderManifestOffset: u64_,
713    pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1,
714    pub gspFwRsvdStart: u64_,
715    pub nonWprHeapOffset: u64_,
716    pub nonWprHeapSize: u64_,
717    pub gspFwWprStart: u64_,
718    pub gspFwHeapOffset: u64_,
719    pub gspFwHeapSize: u64_,
720    pub gspFwOffset: u64_,
721    pub bootBinOffset: u64_,
722    pub frtsOffset: u64_,
723    pub frtsSize: u64_,
724    pub gspFwWprEnd: u64_,
725    pub fbSize: u64_,
726    pub vgaWorkspaceOffset: u64_,
727    pub vgaWorkspaceSize: u64_,
728    pub bootCount: u64_,
729    pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2,
730    pub gspFwHeapVfPartitionCount: u8_,
731    pub flags: u8_,
732    pub padding: [u8_; 2usize],
733    pub pmuReservedSize: u32_,
734    pub verified: u64_,
735}
736#[repr(C)]
737#[derive(Copy, Clone, MaybeZeroable)]
738pub union GspFwWprMeta__bindgen_ty_1 {
739    pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1__bindgen_ty_1,
740    pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_1__bindgen_ty_2,
741}
742#[repr(C)]
743#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
744pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_1 {
745    pub sysmemAddrOfSignature: u64_,
746    pub sizeOfSignature: u64_,
747}
748#[repr(C)]
749#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
750pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_2 {
751    pub gspFwHeapFreeListWprOffset: u32_,
752    pub unused0: u32_,
753    pub unused1: u64_,
754}
755impl Default for GspFwWprMeta__bindgen_ty_1 {
756    fn default() -> Self {
757        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
758        unsafe {
759            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
760            s.assume_init()
761        }
762    }
763}
764#[repr(C)]
765#[derive(Copy, Clone, MaybeZeroable)]
766pub union GspFwWprMeta__bindgen_ty_2 {
767    pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_2__bindgen_ty_1,
768    pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2__bindgen_ty_2,
769}
770#[repr(C)]
771#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
772pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_1 {
773    pub partitionRpcAddr: u64_,
774    pub partitionRpcRequestOffset: u16_,
775    pub partitionRpcReplyOffset: u16_,
776    pub elfCodeOffset: u32_,
777    pub elfDataOffset: u32_,
778    pub elfCodeSize: u32_,
779    pub elfDataSize: u32_,
780    pub lsUcodeVersion: u32_,
781}
782#[repr(C)]
783#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
784pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_2 {
785    pub partitionRpcPadding: [u32_; 4usize],
786    pub sysmemAddrOfCrashReportQueue: u64_,
787    pub sizeOfCrashReportQueue: u32_,
788    pub lsUcodeVersionPadding: [u32_; 1usize],
789}
790impl Default for GspFwWprMeta__bindgen_ty_2 {
791    fn default() -> Self {
792        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
793        unsafe {
794            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
795            s.assume_init()
796        }
797    }
798}
799impl Default for GspFwWprMeta {
800    fn default() -> Self {
801        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
802        unsafe {
803            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
804            s.assume_init()
805        }
806    }
807}
808pub type LibosAddress = u64_;
809pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_NONE: LibosMemoryRegionKind = 0;
810pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONTIGUOUS: LibosMemoryRegionKind = 1;
811pub const LibosMemoryRegionKind_LIBOS_MEMORY_REGION_RADIX3: LibosMemoryRegionKind = 2;
812pub type LibosMemoryRegionKind = ffi::c_uint;
813pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_NONE: LibosMemoryRegionLoc = 0;
814pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_SYSMEM: LibosMemoryRegionLoc = 1;
815pub const LibosMemoryRegionLoc_LIBOS_MEMORY_REGION_LOC_FB: LibosMemoryRegionLoc = 2;
816pub type LibosMemoryRegionLoc = ffi::c_uint;
817#[repr(C)]
818#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
819pub struct LibosMemoryRegionInitArgument {
820    pub id8: LibosAddress,
821    pub pa: LibosAddress,
822    pub size: LibosAddress,
823    pub kind: u8_,
824    pub loc: u8_,
825    pub __bindgen_padding_0: [u8; 6usize],
826}
827#[repr(C)]
828#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
829pub struct PACKED_REGISTRY_ENTRY {
830    pub nameOffset: u32_,
831    pub type_: u8_,
832    pub __bindgen_padding_0: [u8; 3usize],
833    pub data: u32_,
834    pub length: u32_,
835}
836#[repr(C)]
837#[derive(Debug, Default, MaybeZeroable)]
838pub struct PACKED_REGISTRY_TABLE {
839    pub size: u32_,
840    pub numEntries: u32_,
841    pub entries: __IncompleteArrayField<PACKED_REGISTRY_ENTRY>,
842}
843#[repr(C)]
844#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
845pub struct msgqTxHeader {
846    pub version: u32_,
847    pub size: u32_,
848    pub msgSize: u32_,
849    pub msgCount: u32_,
850    pub writePtr: u32_,
851    pub flags: u32_,
852    pub rxHdrOff: u32_,
853    pub entryOff: u32_,
854}
855#[repr(C)]
856#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
857pub struct msgqRxHeader {
858    pub readPtr: u32_,
859}
860#[repr(C)]
861#[repr(align(8))]
862#[derive(MaybeZeroable)]
863pub struct GSP_MSG_QUEUE_ELEMENT {
864    pub authTagBuffer: [u8_; 16usize],
865    pub aadBuffer: [u8_; 16usize],
866    pub checkSum: u32_,
867    pub seqNum: u32_,
868    pub elemCount: u32_,
869    pub __bindgen_padding_0: [u8; 4usize],
870    pub rpc: rpc_message_header_v,
871}
872impl Default for GSP_MSG_QUEUE_ELEMENT {
873    fn default() -> Self {
874        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
875        unsafe {
876            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
877            s.assume_init()
878        }
879    }
880}
881#[repr(C)]
882#[derive(Debug, Default, MaybeZeroable)]
883pub struct rpc_run_cpu_sequencer_v17_00 {
884    pub bufferSizeDWord: u32_,
885    pub cmdIndex: u32_,
886    pub regSaveArea: [u32_; 8usize],
887    pub commandBuffer: __IncompleteArrayField<u32_>,
888}
889pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_WRITE: GSP_SEQ_BUF_OPCODE = 0;
890pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_MODIFY: GSP_SEQ_BUF_OPCODE = 1;
891pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_POLL: GSP_SEQ_BUF_OPCODE = 2;
892pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_DELAY_US: GSP_SEQ_BUF_OPCODE = 3;
893pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_REG_STORE: GSP_SEQ_BUF_OPCODE = 4;
894pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESET: GSP_SEQ_BUF_OPCODE = 5;
895pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_START: GSP_SEQ_BUF_OPCODE = 6;
896pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT: GSP_SEQ_BUF_OPCODE = 7;
897pub const GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESUME: GSP_SEQ_BUF_OPCODE = 8;
898pub type GSP_SEQ_BUF_OPCODE = ffi::c_uint;
899#[repr(C)]
900#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
901pub struct GSP_SEQ_BUF_PAYLOAD_REG_WRITE {
902    pub addr: u32_,
903    pub val: u32_,
904}
905#[repr(C)]
906#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
907pub struct GSP_SEQ_BUF_PAYLOAD_REG_MODIFY {
908    pub addr: u32_,
909    pub mask: u32_,
910    pub val: u32_,
911}
912#[repr(C)]
913#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
914pub struct GSP_SEQ_BUF_PAYLOAD_REG_POLL {
915    pub addr: u32_,
916    pub mask: u32_,
917    pub val: u32_,
918    pub timeout: u32_,
919    pub error: u32_,
920}
921#[repr(C)]
922#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
923pub struct GSP_SEQ_BUF_PAYLOAD_DELAY_US {
924    pub val: u32_,
925}
926#[repr(C)]
927#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
928pub struct GSP_SEQ_BUF_PAYLOAD_REG_STORE {
929    pub addr: u32_,
930    pub index: u32_,
931}
932#[repr(C)]
933#[derive(Copy, Clone, MaybeZeroable)]
934pub struct GSP_SEQUENCER_BUFFER_CMD {
935    pub opCode: GSP_SEQ_BUF_OPCODE,
936    pub payload: GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1,
937}
938#[repr(C)]
939#[derive(Copy, Clone, MaybeZeroable)]
940pub union GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1 {
941    pub regWrite: GSP_SEQ_BUF_PAYLOAD_REG_WRITE,
942    pub regModify: GSP_SEQ_BUF_PAYLOAD_REG_MODIFY,
943    pub regPoll: GSP_SEQ_BUF_PAYLOAD_REG_POLL,
944    pub delayUs: GSP_SEQ_BUF_PAYLOAD_DELAY_US,
945    pub regStore: GSP_SEQ_BUF_PAYLOAD_REG_STORE,
946}
947impl Default for GSP_SEQUENCER_BUFFER_CMD__bindgen_ty_1 {
948    fn default() -> Self {
949        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
950        unsafe {
951            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
952            s.assume_init()
953        }
954    }
955}
956impl Default for GSP_SEQUENCER_BUFFER_CMD {
957    fn default() -> Self {
958        let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
959        unsafe {
960            ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
961            s.assume_init()
962        }
963    }
964}