gfw.rs

 1// SPDX-License-Identifier: GPL-2.0
 2
 3//! GPU Firmware (`GFW`) support, a.k.a `devinit`.
 4//!
 5//! Upon reset, the GPU runs some firmware code from the BIOS to setup its core parameters. Most of
 6//! the GPU is considered unusable until this step is completed, so we must wait on it before
 7//! performing driver initialization.
 8//!
 9//! A clarification about devinit terminology: devinit is a sequence of register read/writes after
10//! reset that performs tasks such as:
11//! 1. Programming VRAM memory controller timings.
12//! 2. Power sequencing.
13//! 3. Clock and PLL configuration.
14//! 4. Thermal management.
15//!
16//! devinit itself is a 'script' which is interpreted by an interpreter program typically running
17//! on the PMU microcontroller.
18//!
19//! Note that the devinit sequence also needs to run during suspend/resume.
20
21use kernel::{
22    io::poll::read_poll_timeout,
23    prelude::*,
24    time::Delta, //
25};
26
27use crate::{
28    driver::Bar0,
29    regs, //
30};
31
32/// Wait for the `GFW` (GPU firmware) boot completion signal (`GFW_BOOT`), or a 4 seconds timeout.
33///
34/// Upon GPU reset, several microcontrollers (such as PMU, SEC2, GSP etc) run some firmware code to
35/// setup its core parameters. Most of the GPU is considered unusable until this step is completed,
36/// so it must be waited on very early during driver initialization.
37///
38/// The `GFW` code includes several components that need to execute before the driver loads. These
39/// components are located in the VBIOS ROM and executed in a sequence on these different
40/// microcontrollers. The devinit sequence typically runs on the PMU, and the FWSEC runs on the
41/// GSP.
42///
43/// This function waits for a signal indicating that core initialization is complete. Before this
44/// signal is received, little can be done with the GPU. This signal is set by the FWSEC running on
45/// the GSP in Heavy-secured mode.
46pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result {
47    // Before accessing the completion status in `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05`, we must
48    // first check `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK`. This is because
49    // `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05` becomes accessible only after the secure firmware
50    // (FWSEC) lowers the privilege level to allow CPU (LS/Light-secured) access. We can only
51    // safely read the status register from CPU (LS/Light-secured) once the mask indicates
52    // that the privilege level has been lowered.
53    //
54    // TIMEOUT: arbitrarily large value. GFW starts running immediately after the GPU is put out of
55    // reset, and should complete in less time than that.
56    read_poll_timeout(
57        || {
58            Ok(
59                // Check that FWSEC has lowered its protection level before reading the GFW_BOOT
60                // status.
61                regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar)
62                    .read_protection_level0()
63                    && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(bar).completed(),
64            )
65        },
66        |&gfw_booted| gfw_booted,
67        Delta::from_millis(1),
68        Delta::from_secs(4),
69    )
70    .map(|_| ())
71}