ipu-ic.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2012-2014 Mentor Graphics Inc.
  4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  5 */
  6
  7#include <linux/types.h>
  8#include <linux/init.h>
  9#include <linux/errno.h>
 10#include <linux/spinlock.h>
 11#include <linux/bitrev.h>
 12#include <linux/io.h>
 13#include <linux/err.h>
 14#include <linux/sizes.h>
 15#include "ipu-prv.h"
 16
 17/* IC Register Offsets */
 18#define IC_CONF                 0x0000
 19#define IC_PRP_ENC_RSC          0x0004
 20#define IC_PRP_VF_RSC           0x0008
 21#define IC_PP_RSC               0x000C
 22#define IC_CMBP_1               0x0010
 23#define IC_CMBP_2               0x0014
 24#define IC_IDMAC_1              0x0018
 25#define IC_IDMAC_2              0x001C
 26#define IC_IDMAC_3              0x0020
 27#define IC_IDMAC_4              0x0024
 28
 29/* IC Register Fields */
 30#define IC_CONF_PRPENC_EN       (1 << 0)
 31#define IC_CONF_PRPENC_CSC1     (1 << 1)
 32#define IC_CONF_PRPENC_ROT_EN   (1 << 2)
 33#define IC_CONF_PRPVF_EN        (1 << 8)
 34#define IC_CONF_PRPVF_CSC1      (1 << 9)
 35#define IC_CONF_PRPVF_CSC2      (1 << 10)
 36#define IC_CONF_PRPVF_CMB       (1 << 11)
 37#define IC_CONF_PRPVF_ROT_EN    (1 << 12)
 38#define IC_CONF_PP_EN           (1 << 16)
 39#define IC_CONF_PP_CSC1         (1 << 17)
 40#define IC_CONF_PP_CSC2         (1 << 18)
 41#define IC_CONF_PP_CMB          (1 << 19)
 42#define IC_CONF_PP_ROT_EN       (1 << 20)
 43#define IC_CONF_IC_GLB_LOC_A    (1 << 28)
 44#define IC_CONF_KEY_COLOR_EN    (1 << 29)
 45#define IC_CONF_RWS_EN          (1 << 30)
 46#define IC_CONF_CSI_MEM_WR_EN   (1 << 31)
 47
 48#define IC_IDMAC_1_CB0_BURST_16         (1 << 0)
 49#define IC_IDMAC_1_CB1_BURST_16         (1 << 1)
 50#define IC_IDMAC_1_CB2_BURST_16         (1 << 2)
 51#define IC_IDMAC_1_CB3_BURST_16         (1 << 3)
 52#define IC_IDMAC_1_CB4_BURST_16         (1 << 4)
 53#define IC_IDMAC_1_CB5_BURST_16         (1 << 5)
 54#define IC_IDMAC_1_CB6_BURST_16         (1 << 6)
 55#define IC_IDMAC_1_CB7_BURST_16         (1 << 7)
 56#define IC_IDMAC_1_PRPENC_ROT_MASK      (0x7 << 11)
 57#define IC_IDMAC_1_PRPENC_ROT_OFFSET    11
 58#define IC_IDMAC_1_PRPVF_ROT_MASK       (0x7 << 14)
 59#define IC_IDMAC_1_PRPVF_ROT_OFFSET     14
 60#define IC_IDMAC_1_PP_ROT_MASK          (0x7 << 17)
 61#define IC_IDMAC_1_PP_ROT_OFFSET        17
 62#define IC_IDMAC_1_PP_FLIP_RS           (1 << 22)
 63#define IC_IDMAC_1_PRPVF_FLIP_RS        (1 << 21)
 64#define IC_IDMAC_1_PRPENC_FLIP_RS       (1 << 20)
 65
 66#define IC_IDMAC_2_PRPENC_HEIGHT_MASK   (0x3ff << 0)
 67#define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0
 68#define IC_IDMAC_2_PRPVF_HEIGHT_MASK    (0x3ff << 10)
 69#define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET  10
 70#define IC_IDMAC_2_PP_HEIGHT_MASK       (0x3ff << 20)
 71#define IC_IDMAC_2_PP_HEIGHT_OFFSET     20
 72
 73#define IC_IDMAC_3_PRPENC_WIDTH_MASK    (0x3ff << 0)
 74#define IC_IDMAC_3_PRPENC_WIDTH_OFFSET  0
 75#define IC_IDMAC_3_PRPVF_WIDTH_MASK     (0x3ff << 10)
 76#define IC_IDMAC_3_PRPVF_WIDTH_OFFSET   10
 77#define IC_IDMAC_3_PP_WIDTH_MASK        (0x3ff << 20)
 78#define IC_IDMAC_3_PP_WIDTH_OFFSET      20
 79
 80struct ic_task_regoffs {
 81	u32 rsc;
 82	u32 tpmem_csc[2];
 83};
 84
 85struct ic_task_bitfields {
 86	u32 ic_conf_en;
 87	u32 ic_conf_rot_en;
 88	u32 ic_conf_cmb_en;
 89	u32 ic_conf_csc1_en;
 90	u32 ic_conf_csc2_en;
 91	u32 ic_cmb_galpha_bit;
 92};
 93
 94static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = {
 95	[IC_TASK_ENCODER] = {
 96		.rsc = IC_PRP_ENC_RSC,
 97		.tpmem_csc = {0x2008, 0},
 98	},
 99	[IC_TASK_VIEWFINDER] = {
100		.rsc = IC_PRP_VF_RSC,
101		.tpmem_csc = {0x4028, 0x4040},
102	},
103	[IC_TASK_POST_PROCESSOR] = {
104		.rsc = IC_PP_RSC,
105		.tpmem_csc = {0x6060, 0x6078},
106	},
107};
108
109static const struct ic_task_bitfields ic_task_bit[IC_NUM_TASKS] = {
110	[IC_TASK_ENCODER] = {
111		.ic_conf_en = IC_CONF_PRPENC_EN,
112		.ic_conf_rot_en = IC_CONF_PRPENC_ROT_EN,
113		.ic_conf_cmb_en = 0,    /* NA */
114		.ic_conf_csc1_en = IC_CONF_PRPENC_CSC1,
115		.ic_conf_csc2_en = 0,   /* NA */
116		.ic_cmb_galpha_bit = 0, /* NA */
117	},
118	[IC_TASK_VIEWFINDER] = {
119		.ic_conf_en = IC_CONF_PRPVF_EN,
120		.ic_conf_rot_en = IC_CONF_PRPVF_ROT_EN,
121		.ic_conf_cmb_en = IC_CONF_PRPVF_CMB,
122		.ic_conf_csc1_en = IC_CONF_PRPVF_CSC1,
123		.ic_conf_csc2_en = IC_CONF_PRPVF_CSC2,
124		.ic_cmb_galpha_bit = 0,
125	},
126	[IC_TASK_POST_PROCESSOR] = {
127		.ic_conf_en = IC_CONF_PP_EN,
128		.ic_conf_rot_en = IC_CONF_PP_ROT_EN,
129		.ic_conf_cmb_en = IC_CONF_PP_CMB,
130		.ic_conf_csc1_en = IC_CONF_PP_CSC1,
131		.ic_conf_csc2_en = IC_CONF_PP_CSC2,
132		.ic_cmb_galpha_bit = 8,
133	},
134};
135
136struct ipu_ic_priv;
137
138struct ipu_ic {
139	enum ipu_ic_task task;
140	const struct ic_task_regoffs *reg;
141	const struct ic_task_bitfields *bit;
142
143	struct ipu_ic_colorspace in_cs;
144	struct ipu_ic_colorspace g_in_cs;
145	struct ipu_ic_colorspace out_cs;
146
147	bool graphics;
148	bool rotation;
149	bool in_use;
150
151	struct ipu_ic_priv *priv;
152};
153
154struct ipu_ic_priv {
155	void __iomem *base;
156	void __iomem *tpmem_base;
157	spinlock_t lock;
158	struct ipu_soc *ipu;
159	int use_count;
160	int irt_use_count;
161	struct ipu_ic task[IC_NUM_TASKS];
162};
163
164static inline u32 ipu_ic_read(struct ipu_ic *ic, unsigned offset)
165{
166	return readl(ic->priv->base + offset);
167}
168
169static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset)
170{
171	writel(value, ic->priv->base + offset);
172}
173
174static int init_csc(struct ipu_ic *ic,
175		    const struct ipu_ic_csc *csc,
176		    int csc_index)
177{
178	struct ipu_ic_priv *priv = ic->priv;
179	u32 __iomem *base;
180	const u16 (*c)[3];
181	const u16 *a;
182	u32 param;
183
184	base = (u32 __iomem *)
185		(priv->tpmem_base + ic->reg->tpmem_csc[csc_index]);
186
187	/* Cast to unsigned */
188	c = (const u16 (*)[3])csc->params.coeff;
189	a = (const u16 *)csc->params.offset;
190
191	param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) |
192		((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff);
193	writel(param, base++);
194
195	param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) |
196		(csc->params.sat << 10);
197	writel(param, base++);
198
199	param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
200		((c[1][0] & 0x1ff) << 9) | (c[2][0] & 0x1ff);
201	writel(param, base++);
202
203	param = ((a[1] & 0x1fe0) >> 5);
204	writel(param, base++);
205
206	param = ((a[2] & 0x1f) << 27) | ((c[0][2] & 0x1ff) << 18) |
207		((c[1][2] & 0x1ff) << 9) | (c[2][1] & 0x1ff);
208	writel(param, base++);
209
210	param = ((a[2] & 0x1fe0) >> 5);
211	writel(param, base++);
212
213	return 0;
214}
215
216static int calc_resize_coeffs(struct ipu_ic *ic,
217			      u32 in_size, u32 out_size,
218			      u32 *resize_coeff,
219			      u32 *downsize_coeff)
220{
221	struct ipu_ic_priv *priv = ic->priv;
222	struct ipu_soc *ipu = priv->ipu;
223	u32 temp_size, temp_downsize;
224
225	/*
226	 * Input size cannot be more than 4096, and output size cannot
227	 * be more than 1024
228	 */
229	if (in_size > 4096) {
230		dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n");
231		return -EINVAL;
232	}
233	if (out_size > 1024) {
234		dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n");
235		return -EINVAL;
236	}
237
238	/* Cannot downsize more than 4:1 */
239	if ((out_size << 2) < in_size) {
240		dev_err(ipu->dev, "Unsupported downsize\n");
241		return -EINVAL;
242	}
243
244	/* Compute downsizing coefficient */
245	temp_downsize = 0;
246	temp_size = in_size;
247	while (((temp_size > 1024) || (temp_size >= out_size * 2)) &&
248	       (temp_downsize < 2)) {
249		temp_size >>= 1;
250		temp_downsize++;
251	}
252	*downsize_coeff = temp_downsize;
253
254	/*
255	 * compute resizing coefficient using the following equation:
256	 * resize_coeff = M * (SI - 1) / (SO - 1)
257	 * where M = 2^13, SI = input size, SO = output size
258	 */
259	*resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
260	if (*resize_coeff >= 16384L) {
261		dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n");
262		*resize_coeff = 0x3FFF;
263	}
264
265	return 0;
266}
267
268void ipu_ic_task_enable(struct ipu_ic *ic)
269{
270	struct ipu_ic_priv *priv = ic->priv;
271	unsigned long flags;
272	u32 ic_conf;
273
274	spin_lock_irqsave(&priv->lock, flags);
275
276	ic_conf = ipu_ic_read(ic, IC_CONF);
277
278	ic_conf |= ic->bit->ic_conf_en;
279
280	if (ic->rotation)
281		ic_conf |= ic->bit->ic_conf_rot_en;
282
283	if (ic->in_cs.cs != ic->out_cs.cs)
284		ic_conf |= ic->bit->ic_conf_csc1_en;
285
286	if (ic->graphics) {
287		ic_conf |= ic->bit->ic_conf_cmb_en;
288		ic_conf |= ic->bit->ic_conf_csc1_en;
289
290		if (ic->g_in_cs.cs != ic->out_cs.cs)
291			ic_conf |= ic->bit->ic_conf_csc2_en;
292	}
293
294	ipu_ic_write(ic, ic_conf, IC_CONF);
295
296	spin_unlock_irqrestore(&priv->lock, flags);
297}
298EXPORT_SYMBOL_GPL(ipu_ic_task_enable);
299
300void ipu_ic_task_disable(struct ipu_ic *ic)
301{
302	struct ipu_ic_priv *priv = ic->priv;
303	unsigned long flags;
304	u32 ic_conf;
305
306	spin_lock_irqsave(&priv->lock, flags);
307
308	ic_conf = ipu_ic_read(ic, IC_CONF);
309
310	ic_conf &= ~(ic->bit->ic_conf_en |
311		     ic->bit->ic_conf_csc1_en |
312		     ic->bit->ic_conf_rot_en);
313	if (ic->bit->ic_conf_csc2_en)
314		ic_conf &= ~ic->bit->ic_conf_csc2_en;
315	if (ic->bit->ic_conf_cmb_en)
316		ic_conf &= ~ic->bit->ic_conf_cmb_en;
317
318	ipu_ic_write(ic, ic_conf, IC_CONF);
319
320	spin_unlock_irqrestore(&priv->lock, flags);
321}
322EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
323
324int ipu_ic_task_init_rsc(struct ipu_ic *ic,
325			 const struct ipu_ic_csc *csc,
326			 int in_width, int in_height,
327			 int out_width, int out_height,
328			 u32 rsc)
329{
330	struct ipu_ic_priv *priv = ic->priv;
331	u32 downsize_coeff, resize_coeff;
332	unsigned long flags;
333	int ret = 0;
334
335	if (!rsc) {
336		/* Setup vertical resizing */
337
338		ret = calc_resize_coeffs(ic, in_height, out_height,
339					 &resize_coeff, &downsize_coeff);
340		if (ret)
341			return ret;
342
343		rsc = (downsize_coeff << 30) | (resize_coeff << 16);
344
345		/* Setup horizontal resizing */
346		ret = calc_resize_coeffs(ic, in_width, out_width,
347					 &resize_coeff, &downsize_coeff);
348		if (ret)
349			return ret;
350
351		rsc |= (downsize_coeff << 14) | resize_coeff;
352	}
353
354	spin_lock_irqsave(&priv->lock, flags);
355
356	ipu_ic_write(ic, rsc, ic->reg->rsc);
357
358	/* Setup color space conversion */
359	ic->in_cs = csc->in_cs;
360	ic->out_cs = csc->out_cs;
361
362	ret = init_csc(ic, csc, 0);
363
364	spin_unlock_irqrestore(&priv->lock, flags);
365	return ret;
366}
367
368int ipu_ic_task_init(struct ipu_ic *ic,
369		     const struct ipu_ic_csc *csc,
370		     int in_width, int in_height,
371		     int out_width, int out_height)
372{
373	return ipu_ic_task_init_rsc(ic, csc,
374				    in_width, in_height,
375				    out_width, out_height, 0);
376}
377EXPORT_SYMBOL_GPL(ipu_ic_task_init);
378
379int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
380			  u32 width, u32 height, int burst_size,
381			  enum ipu_rotate_mode rot)
382{
383	struct ipu_ic_priv *priv = ic->priv;
384	struct ipu_soc *ipu = priv->ipu;
385	u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
386	u32 temp_rot = bitrev8(rot) >> 5;
387	bool need_hor_flip = false;
388	unsigned long flags;
389	int ret = 0;
390
391	if ((burst_size != 8) && (burst_size != 16)) {
392		dev_err(ipu->dev, "Illegal burst length for IC\n");
393		return -EINVAL;
394	}
395
396	width--;
397	height--;
398
399	if (temp_rot & 0x2)	/* Need horizontal flip */
400		need_hor_flip = true;
401
402	spin_lock_irqsave(&priv->lock, flags);
403
404	ic_idmac_1 = ipu_ic_read(ic, IC_IDMAC_1);
405	ic_idmac_2 = ipu_ic_read(ic, IC_IDMAC_2);
406	ic_idmac_3 = ipu_ic_read(ic, IC_IDMAC_3);
407
408	switch (channel->num) {
409	case IPUV3_CHANNEL_IC_PP_MEM:
410		if (burst_size == 16)
411			ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
412		else
413			ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
414
415		if (need_hor_flip)
416			ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
417		else
418			ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
419
420		ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
421		ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
422
423		ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
424		ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
425		break;
426	case IPUV3_CHANNEL_MEM_IC_PP:
427		if (burst_size == 16)
428			ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
429		else
430			ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
431		break;
432	case IPUV3_CHANNEL_MEM_ROT_PP:
433		ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
434		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
435		break;
436	case IPUV3_CHANNEL_MEM_IC_PRP_VF:
437		if (burst_size == 16)
438			ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
439		else
440			ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
441		break;
442	case IPUV3_CHANNEL_IC_PRP_ENC_MEM:
443		if (burst_size == 16)
444			ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
445		else
446			ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
447
448		if (need_hor_flip)
449			ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
450		else
451			ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
452
453		ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
454		ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
455
456		ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
457		ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
458		break;
459	case IPUV3_CHANNEL_MEM_ROT_ENC:
460		ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
461		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
462		break;
463	case IPUV3_CHANNEL_IC_PRP_VF_MEM:
464		if (burst_size == 16)
465			ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
466		else
467			ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
468
469		if (need_hor_flip)
470			ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
471		else
472			ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
473
474		ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
475		ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
476
477		ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
478		ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
479		break;
480	case IPUV3_CHANNEL_MEM_ROT_VF:
481		ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
482		ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
483		break;
484	case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
485		if (burst_size == 16)
486			ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
487		else
488			ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
489		break;
490	case IPUV3_CHANNEL_G_MEM_IC_PP:
491		if (burst_size == 16)
492			ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
493		else
494			ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
495		break;
496	case IPUV3_CHANNEL_VDI_MEM_IC_VF:
497		if (burst_size == 16)
498			ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
499		else
500			ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
501		break;
502	default:
503		goto unlock;
504	}
505
506	ipu_ic_write(ic, ic_idmac_1, IC_IDMAC_1);
507	ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
508	ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
509
510	if (ipu_rot_mode_is_irt(rot))
511		ic->rotation = true;
512
513unlock:
514	spin_unlock_irqrestore(&priv->lock, flags);
515	return ret;
516}
517EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);
518
519static void ipu_irt_enable(struct ipu_ic *ic)
520{
521	struct ipu_ic_priv *priv = ic->priv;
522
523	if (!priv->irt_use_count)
524		ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN);
525
526	priv->irt_use_count++;
527}
528
529static void ipu_irt_disable(struct ipu_ic *ic)
530{
531	struct ipu_ic_priv *priv = ic->priv;
532
533	if (priv->irt_use_count) {
534		if (!--priv->irt_use_count)
535			ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN);
536	}
537}
538
539int ipu_ic_enable(struct ipu_ic *ic)
540{
541	struct ipu_ic_priv *priv = ic->priv;
542	unsigned long flags;
543
544	spin_lock_irqsave(&priv->lock, flags);
545
546	if (!priv->use_count)
547		ipu_module_enable(priv->ipu, IPU_CONF_IC_EN);
548
549	priv->use_count++;
550
551	if (ic->rotation)
552		ipu_irt_enable(ic);
553
554	spin_unlock_irqrestore(&priv->lock, flags);
555
556	return 0;
557}
558EXPORT_SYMBOL_GPL(ipu_ic_enable);
559
560int ipu_ic_disable(struct ipu_ic *ic)
561{
562	struct ipu_ic_priv *priv = ic->priv;
563	unsigned long flags;
564
565	spin_lock_irqsave(&priv->lock, flags);
566
567	priv->use_count--;
568
569	if (!priv->use_count)
570		ipu_module_disable(priv->ipu, IPU_CONF_IC_EN);
571
572	if (priv->use_count < 0)
573		priv->use_count = 0;
574
575	if (ic->rotation)
576		ipu_irt_disable(ic);
577
578	ic->rotation = ic->graphics = false;
579
580	spin_unlock_irqrestore(&priv->lock, flags);
581
582	return 0;
583}
584EXPORT_SYMBOL_GPL(ipu_ic_disable);
585
586struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task)
587{
588	struct ipu_ic_priv *priv = ipu->ic_priv;
589	unsigned long flags;
590	struct ipu_ic *ic, *ret;
591
592	if (task >= IC_NUM_TASKS)
593		return ERR_PTR(-EINVAL);
594
595	ic = &priv->task[task];
596
597	spin_lock_irqsave(&priv->lock, flags);
598
599	if (ic->in_use) {
600		ret = ERR_PTR(-EBUSY);
601		goto unlock;
602	}
603
604	ic->in_use = true;
605	ret = ic;
606
607unlock:
608	spin_unlock_irqrestore(&priv->lock, flags);
609	return ret;
610}
611EXPORT_SYMBOL_GPL(ipu_ic_get);
612
613void ipu_ic_put(struct ipu_ic *ic)
614{
615	struct ipu_ic_priv *priv = ic->priv;
616	unsigned long flags;
617
618	spin_lock_irqsave(&priv->lock, flags);
619	ic->in_use = false;
620	spin_unlock_irqrestore(&priv->lock, flags);
621}
622EXPORT_SYMBOL_GPL(ipu_ic_put);
623
624int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
625		unsigned long base, unsigned long tpmem_base)
626{
627	struct ipu_ic_priv *priv;
628	int i;
629
630	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
631	if (!priv)
632		return -ENOMEM;
633
634	ipu->ic_priv = priv;
635
636	spin_lock_init(&priv->lock);
637	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
638	if (!priv->base)
639		return -ENOMEM;
640	priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K);
641	if (!priv->tpmem_base)
642		return -ENOMEM;
643
644	dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base);
645
646	priv->ipu = ipu;
647
648	for (i = 0; i < IC_NUM_TASKS; i++) {
649		priv->task[i].task = i;
650		priv->task[i].priv = priv;
651		priv->task[i].reg = &ic_task_reg[i];
652		priv->task[i].bit = &ic_task_bit[i];
653	}
654
655	return 0;
656}
657
658void ipu_ic_exit(struct ipu_soc *ipu)
659{
660}
661
662void ipu_ic_dump(struct ipu_ic *ic)
663{
664	struct ipu_ic_priv *priv = ic->priv;
665	struct ipu_soc *ipu = priv->ipu;
666
667	dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n",
668		ipu_ic_read(ic, IC_CONF));
669	dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n",
670		ipu_ic_read(ic, IC_PRP_ENC_RSC));
671	dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n",
672		ipu_ic_read(ic, IC_PRP_VF_RSC));
673	dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n",
674		ipu_ic_read(ic, IC_PP_RSC));
675	dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n",
676		ipu_ic_read(ic, IC_CMBP_1));
677	dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n",
678		ipu_ic_read(ic, IC_CMBP_2));
679	dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n",
680		ipu_ic_read(ic, IC_IDMAC_1));
681	dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n",
682		ipu_ic_read(ic, IC_IDMAC_2));
683	dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n",
684		ipu_ic_read(ic, IC_IDMAC_3));
685	dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n",
686		ipu_ic_read(ic, IC_IDMAC_4));
687}
688EXPORT_SYMBOL_GPL(ipu_ic_dump);