ipu-csi.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2012-2014 Mentor Graphics Inc.
  4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
  5 */
  6#include <linux/export.h>
  7#include <linux/module.h>
  8#include <linux/types.h>
  9#include <linux/errno.h>
 10#include <linux/delay.h>
 11#include <linux/io.h>
 12#include <linux/err.h>
 13#include <linux/platform_device.h>
 14#include <linux/videodev2.h>
 15#include <uapi/linux/v4l2-mediabus.h>
 16#include <linux/clk.h>
 17#include <linux/clk-provider.h>
 18#include <linux/clkdev.h>
 19
 20#include "ipu-prv.h"
 21
 22struct ipu_csi {
 23	void __iomem *base;
 24	int id;
 25	u32 module;
 26	struct clk *clk_ipu;	/* IPU bus clock */
 27	spinlock_t lock;
 28	bool inuse;
 29	struct ipu_soc *ipu;
 30};
 31
 32/* CSI Register Offsets */
 33#define CSI_SENS_CONF		0x0000
 34#define CSI_SENS_FRM_SIZE	0x0004
 35#define CSI_ACT_FRM_SIZE	0x0008
 36#define CSI_OUT_FRM_CTRL	0x000c
 37#define CSI_TST_CTRL		0x0010
 38#define CSI_CCIR_CODE_1		0x0014
 39#define CSI_CCIR_CODE_2		0x0018
 40#define CSI_CCIR_CODE_3		0x001c
 41#define CSI_MIPI_DI		0x0020
 42#define CSI_SKIP		0x0024
 43#define CSI_CPD_CTRL		0x0028
 44#define CSI_CPD_RC(n)		(0x002c + ((n)*4))
 45#define CSI_CPD_RS(n)		(0x004c + ((n)*4))
 46#define CSI_CPD_GRC(n)		(0x005c + ((n)*4))
 47#define CSI_CPD_GRS(n)		(0x007c + ((n)*4))
 48#define CSI_CPD_GBC(n)		(0x008c + ((n)*4))
 49#define CSI_CPD_GBS(n)		(0x00Ac + ((n)*4))
 50#define CSI_CPD_BC(n)		(0x00Bc + ((n)*4))
 51#define CSI_CPD_BS(n)		(0x00Dc + ((n)*4))
 52#define CSI_CPD_OFFSET1		0x00ec
 53#define CSI_CPD_OFFSET2		0x00f0
 54
 55/* CSI Register Fields */
 56#define CSI_SENS_CONF_DATA_FMT_SHIFT		8
 57#define CSI_SENS_CONF_DATA_FMT_MASK		0x00000700
 58#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444	0L
 59#define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV	1L
 60#define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY	2L
 61#define CSI_SENS_CONF_DATA_FMT_BAYER		3L
 62#define CSI_SENS_CONF_DATA_FMT_RGB565		4L
 63#define CSI_SENS_CONF_DATA_FMT_RGB555		5L
 64#define CSI_SENS_CONF_DATA_FMT_RGB444		6L
 65#define CSI_SENS_CONF_DATA_FMT_JPEG		7L
 66
 67#define CSI_SENS_CONF_VSYNC_POL_SHIFT		0
 68#define CSI_SENS_CONF_HSYNC_POL_SHIFT		1
 69#define CSI_SENS_CONF_DATA_POL_SHIFT		2
 70#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT		3
 71#define CSI_SENS_CONF_SENS_PRTCL_MASK		0x00000070
 72#define CSI_SENS_CONF_SENS_PRTCL_SHIFT		4
 73#define CSI_SENS_CONF_PACK_TIGHT_SHIFT		7
 74#define CSI_SENS_CONF_DATA_WIDTH_SHIFT		11
 75#define CSI_SENS_CONF_EXT_VSYNC_SHIFT		15
 76#define CSI_SENS_CONF_DIVRATIO_SHIFT		16
 77
 78#define CSI_SENS_CONF_DIVRATIO_MASK		0x00ff0000
 79#define CSI_SENS_CONF_DATA_DEST_SHIFT		24
 80#define CSI_SENS_CONF_DATA_DEST_MASK		0x07000000
 81#define CSI_SENS_CONF_JPEG8_EN_SHIFT		27
 82#define CSI_SENS_CONF_JPEG_EN_SHIFT		28
 83#define CSI_SENS_CONF_FORCE_EOF_SHIFT		29
 84#define CSI_SENS_CONF_DATA_EN_POL_SHIFT		31
 85
 86#define CSI_DATA_DEST_IC			2
 87#define CSI_DATA_DEST_IDMAC			4
 88
 89#define CSI_CCIR_ERR_DET_EN			0x01000000
 90#define CSI_HORI_DOWNSIZE_EN			0x80000000
 91#define CSI_VERT_DOWNSIZE_EN			0x40000000
 92#define CSI_TEST_GEN_MODE_EN			0x01000000
 93
 94#define CSI_HSC_MASK				0x1fff0000
 95#define CSI_HSC_SHIFT				16
 96#define CSI_VSC_MASK				0x00000fff
 97#define CSI_VSC_SHIFT				0
 98
 99#define CSI_TEST_GEN_R_MASK			0x000000ff
100#define CSI_TEST_GEN_R_SHIFT			0
101#define CSI_TEST_GEN_G_MASK			0x0000ff00
102#define CSI_TEST_GEN_G_SHIFT			8
103#define CSI_TEST_GEN_B_MASK			0x00ff0000
104#define CSI_TEST_GEN_B_SHIFT			16
105
106#define CSI_MAX_RATIO_SKIP_SMFC_MASK		0x00000007
107#define CSI_MAX_RATIO_SKIP_SMFC_SHIFT		0
108#define CSI_SKIP_SMFC_MASK			0x000000f8
109#define CSI_SKIP_SMFC_SHIFT			3
110#define CSI_ID_2_SKIP_MASK			0x00000300
111#define CSI_ID_2_SKIP_SHIFT			8
112
113#define CSI_COLOR_FIRST_ROW_MASK		0x00000002
114#define CSI_COLOR_FIRST_COMP_MASK		0x00000001
115
116/* MIPI CSI-2 data types */
117#define MIPI_DT_YUV420		0x18 /* YYY.../UYVY.... */
118#define MIPI_DT_YUV420_LEGACY	0x1a /* UYY.../VYY...   */
119#define MIPI_DT_YUV422		0x1e /* UYVY...         */
120#define MIPI_DT_RGB444		0x20
121#define MIPI_DT_RGB555		0x21
122#define MIPI_DT_RGB565		0x22
123#define MIPI_DT_RGB666		0x23
124#define MIPI_DT_RGB888		0x24
125#define MIPI_DT_RAW6		0x28
126#define MIPI_DT_RAW7		0x29
127#define MIPI_DT_RAW8		0x2a
128#define MIPI_DT_RAW10		0x2b
129#define MIPI_DT_RAW12		0x2c
130#define MIPI_DT_RAW14		0x2d
131
132/*
133 * Bitfield of CSI bus signal polarities and modes.
134 */
135struct ipu_csi_bus_config {
136	unsigned data_width:4;
137	unsigned clk_mode:3;
138	unsigned ext_vsync:1;
139	unsigned vsync_pol:1;
140	unsigned hsync_pol:1;
141	unsigned pixclk_pol:1;
142	unsigned data_pol:1;
143	unsigned sens_clksrc:1;
144	unsigned pack_tight:1;
145	unsigned force_eof:1;
146	unsigned data_en_pol:1;
147
148	unsigned data_fmt;
149	unsigned mipi_dt;
150};
151
152/*
153 * Enumeration of CSI data bus widths.
154 */
155enum ipu_csi_data_width {
156	IPU_CSI_DATA_WIDTH_4   = 0,
157	IPU_CSI_DATA_WIDTH_8   = 1,
158	IPU_CSI_DATA_WIDTH_10  = 3,
159	IPU_CSI_DATA_WIDTH_12  = 5,
160	IPU_CSI_DATA_WIDTH_16  = 9,
161};
162
163/*
164 * Enumeration of CSI clock modes.
165 */
166enum ipu_csi_clk_mode {
167	IPU_CSI_CLK_MODE_GATED_CLK,
168	IPU_CSI_CLK_MODE_NONGATED_CLK,
169	IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
170	IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
171	IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
172	IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
173	IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
174	IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
175};
176
177static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
178{
179	return readl(csi->base + offset);
180}
181
182static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
183				 unsigned offset)
184{
185	writel(value, csi->base + offset);
186}
187
188/*
189 * Find the CSI data format and data width for the given V4L2 media
190 * bus pixel format code.
191 */
192static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code,
193				enum v4l2_mbus_type mbus_type)
194{
195	switch (mbus_code) {
196	case MEDIA_BUS_FMT_BGR565_2X8_BE:
197	case MEDIA_BUS_FMT_BGR565_2X8_LE:
198	case MEDIA_BUS_FMT_RGB565_2X8_BE:
199	case MEDIA_BUS_FMT_RGB565_2X8_LE:
200		if (mbus_type == V4L2_MBUS_CSI2_DPHY)
201			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
202		else
203			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
204		cfg->mipi_dt = MIPI_DT_RGB565;
205		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
206		break;
207	case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
208	case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
209		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
210		cfg->mipi_dt = MIPI_DT_RGB444;
211		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
212		break;
213	case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
214	case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
215		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
216		cfg->mipi_dt = MIPI_DT_RGB555;
217		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
218		break;
219	case MEDIA_BUS_FMT_RGB888_1X24:
220	case MEDIA_BUS_FMT_BGR888_1X24:
221		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
222		cfg->mipi_dt = MIPI_DT_RGB888;
223		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
224		break;
225	case MEDIA_BUS_FMT_UYVY8_2X8:
226		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
227		cfg->mipi_dt = MIPI_DT_YUV422;
228		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
229		break;
230	case MEDIA_BUS_FMT_YUYV8_2X8:
231		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
232		cfg->mipi_dt = MIPI_DT_YUV422;
233		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
234		break;
235	case MEDIA_BUS_FMT_UYVY8_1X16:
236		if (mbus_type == V4L2_MBUS_BT656) {
237			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
238			cfg->data_width = IPU_CSI_DATA_WIDTH_8;
239		} else {
240			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
241			cfg->data_width = IPU_CSI_DATA_WIDTH_16;
242		}
243		cfg->mipi_dt = MIPI_DT_YUV422;
244		break;
245	case MEDIA_BUS_FMT_YUYV8_1X16:
246		if (mbus_type == V4L2_MBUS_BT656) {
247			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
248			cfg->data_width = IPU_CSI_DATA_WIDTH_8;
249		} else {
250			cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
251			cfg->data_width = IPU_CSI_DATA_WIDTH_16;
252		}
253		cfg->mipi_dt = MIPI_DT_YUV422;
254		break;
255	case MEDIA_BUS_FMT_SBGGR8_1X8:
256	case MEDIA_BUS_FMT_SGBRG8_1X8:
257	case MEDIA_BUS_FMT_SGRBG8_1X8:
258	case MEDIA_BUS_FMT_SRGGB8_1X8:
259	case MEDIA_BUS_FMT_Y8_1X8:
260		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
261		cfg->mipi_dt = MIPI_DT_RAW8;
262		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
263		break;
264	case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
265	case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
266	case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
267	case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
268	case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
269	case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
270	case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
271	case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
272		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
273		cfg->mipi_dt = MIPI_DT_RAW10;
274		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
275		break;
276	case MEDIA_BUS_FMT_SBGGR10_1X10:
277	case MEDIA_BUS_FMT_SGBRG10_1X10:
278	case MEDIA_BUS_FMT_SGRBG10_1X10:
279	case MEDIA_BUS_FMT_SRGGB10_1X10:
280	case MEDIA_BUS_FMT_Y10_1X10:
281		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
282		cfg->mipi_dt = MIPI_DT_RAW10;
283		cfg->data_width = IPU_CSI_DATA_WIDTH_10;
284		break;
285	case MEDIA_BUS_FMT_SBGGR12_1X12:
286	case MEDIA_BUS_FMT_SGBRG12_1X12:
287	case MEDIA_BUS_FMT_SGRBG12_1X12:
288	case MEDIA_BUS_FMT_SRGGB12_1X12:
289	case MEDIA_BUS_FMT_Y12_1X12:
290		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
291		cfg->mipi_dt = MIPI_DT_RAW12;
292		cfg->data_width = IPU_CSI_DATA_WIDTH_12;
293		break;
294	case MEDIA_BUS_FMT_JPEG_1X8:
295		/* TODO */
296		cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
297		cfg->mipi_dt = MIPI_DT_RAW8;
298		cfg->data_width = IPU_CSI_DATA_WIDTH_8;
299		break;
300	default:
301		return -EINVAL;
302	}
303
304	return 0;
305}
306
307/* translate alternate field mode based on given standard */
308static inline enum v4l2_field
309ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std)
310{
311	return (field != V4L2_FIELD_ALTERNATE) ? field :
312		((std & V4L2_STD_525_60) ?
313		 V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB);
314}
315
316/*
317 * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
318 */
319static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
320			    const struct v4l2_mbus_config *mbus_cfg,
321			    const struct v4l2_mbus_framefmt *mbus_fmt)
322{
323	int ret, is_bt1120;
324
325	memset(csicfg, 0, sizeof(*csicfg));
326
327	ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type);
328	if (ret < 0)
329		return ret;
330
331	switch (mbus_cfg->type) {
332	case V4L2_MBUS_PARALLEL:
333		csicfg->ext_vsync = 1;
334		csicfg->vsync_pol = (mbus_cfg->bus.parallel.flags &
335				     V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
336		csicfg->hsync_pol = (mbus_cfg->bus.parallel.flags &
337				     V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
338		csicfg->pixclk_pol = (mbus_cfg->bus.parallel.flags &
339				      V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
340		csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
341		break;
342	case V4L2_MBUS_BT656:
343		csicfg->ext_vsync = 0;
344		/* UYVY10_1X20 etc. should be supported as well */
345		is_bt1120 = mbus_fmt->code == MEDIA_BUS_FMT_UYVY8_1X16 ||
346			    mbus_fmt->code == MEDIA_BUS_FMT_YUYV8_1X16;
347		if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) ||
348		    mbus_fmt->field == V4L2_FIELD_ALTERNATE)
349			csicfg->clk_mode = is_bt1120 ?
350				IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR :
351				IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
352		else
353			csicfg->clk_mode = is_bt1120 ?
354				IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR :
355				IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
356		break;
357	case V4L2_MBUS_CSI2_DPHY:
358		/*
359		 * MIPI CSI-2 requires non gated clock mode, all other
360		 * parameters are not applicable for MIPI CSI-2 bus.
361		 */
362		csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
363		break;
364	default:
365		/* will never get here, keep compiler quiet */
366		break;
367	}
368
369	return 0;
370}
371
372static int
373ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
374				const struct v4l2_mbus_framefmt *infmt,
375				const struct v4l2_mbus_framefmt *outfmt,
376				v4l2_std_id std)
377{
378	enum v4l2_field infield, outfield;
379	bool swap_fields;
380
381	/* get translated field type of input and output */
382	infield = ipu_csi_translate_field(infmt->field, std);
383	outfield = ipu_csi_translate_field(outfmt->field, std);
384
385	/*
386	 * Write the H-V-F codes the CSI will match against the
387	 * incoming data for start/end of active and blanking
388	 * field intervals. If input and output field types are
389	 * sequential but not the same (one is SEQ_BT and the other
390	 * is SEQ_TB), swap the F-bit so that the CSI will capture
391	 * field 1 lines before field 0 lines.
392	 */
393	swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) &&
394		       V4L2_FIELD_IS_SEQUENTIAL(outfield) &&
395		       infield != outfield);
396
397	if (!swap_fields) {
398		/*
399		 * Field0BlankEnd  = 110, Field0BlankStart  = 010
400		 * Field0ActiveEnd = 100, Field0ActiveStart = 000
401		 * Field1BlankEnd  = 111, Field1BlankStart  = 011
402		 * Field1ActiveEnd = 101, Field1ActiveStart = 001
403		 */
404		ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
405			      CSI_CCIR_CODE_1);
406		ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
407	} else {
408		dev_dbg(csi->ipu->dev, "capture field swap\n");
409
410		/* same as above but with F-bit inverted */
411		ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
412			      CSI_CCIR_CODE_1);
413		ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
414	}
415
416	ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
417
418	return 0;
419}
420
421
422int ipu_csi_init_interface(struct ipu_csi *csi,
423			   const struct v4l2_mbus_config *mbus_cfg,
424			   const struct v4l2_mbus_framefmt *infmt,
425			   const struct v4l2_mbus_framefmt *outfmt)
426{
427	struct ipu_csi_bus_config cfg;
428	unsigned long flags;
429	u32 width, height, data = 0;
430	v4l2_std_id std;
431	int ret;
432
433	ret = fill_csi_bus_cfg(&cfg, mbus_cfg, infmt);
434	if (ret < 0)
435		return ret;
436
437	/* set default sensor frame width and height */
438	width = infmt->width;
439	height = infmt->height;
440	if (infmt->field == V4L2_FIELD_ALTERNATE)
441		height *= 2;
442
443	/* Set the CSI_SENS_CONF register remaining fields */
444	data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
445		cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
446		cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
447		cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
448		cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
449		cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
450		cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
451		cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
452		cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
453		cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
454		cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
455
456	spin_lock_irqsave(&csi->lock, flags);
457
458	ipu_csi_write(csi, data, CSI_SENS_CONF);
459
460	/* Set CCIR registers */
461
462	switch (cfg.clk_mode) {
463	case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
464		ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
465		ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
466		break;
467	case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
468		if (width == 720 && height == 480) {
469			std = V4L2_STD_NTSC;
470			height = 525;
471		} else if (width == 720 && height == 576) {
472			std = V4L2_STD_PAL;
473			height = 625;
474		} else {
475			dev_err(csi->ipu->dev,
476				"Unsupported interlaced video mode\n");
477			ret = -EINVAL;
478			goto out_unlock;
479		}
480
481		ret = ipu_csi_set_bt_interlaced_codes(csi, infmt, outfmt, std);
482		if (ret)
483			goto out_unlock;
484		break;
485	case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
486	case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
487	case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
488	case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
489		ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
490				   CSI_CCIR_CODE_1);
491		ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
492		break;
493	case IPU_CSI_CLK_MODE_GATED_CLK:
494	case IPU_CSI_CLK_MODE_NONGATED_CLK:
495		ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
496		break;
497	}
498
499	/* Setup sensor frame size */
500	ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
501		      CSI_SENS_FRM_SIZE);
502
503	dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
504		ipu_csi_read(csi, CSI_SENS_CONF));
505	dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
506		ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
507
508out_unlock:
509	spin_unlock_irqrestore(&csi->lock, flags);
510
511	return ret;
512}
513EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
514
515void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
516{
517	unsigned long flags;
518	u32 reg;
519
520	spin_lock_irqsave(&csi->lock, flags);
521
522	ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
523			  CSI_ACT_FRM_SIZE);
524
525	reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
526	reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
527	reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
528	ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
529
530	spin_unlock_irqrestore(&csi->lock, flags);
531}
532EXPORT_SYMBOL_GPL(ipu_csi_set_window);
533
534void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
535{
536	unsigned long flags;
537	u32 reg;
538
539	spin_lock_irqsave(&csi->lock, flags);
540
541	reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
542	reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
543	reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
544	       (vert ? CSI_VERT_DOWNSIZE_EN : 0);
545	ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
546
547	spin_unlock_irqrestore(&csi->lock, flags);
548}
549EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
550
551int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
552			      struct v4l2_mbus_framefmt *mbus_fmt)
553{
554	struct ipu_csi_bus_config cfg;
555	unsigned long flags;
556	u32 temp;
557	int ret;
558
559	if (vc > 3)
560		return -EINVAL;
561
562	ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2_DPHY);
563	if (ret < 0)
564		return ret;
565
566	spin_lock_irqsave(&csi->lock, flags);
567
568	temp = ipu_csi_read(csi, CSI_MIPI_DI);
569	temp &= ~(0xff << (vc * 8));
570	temp |= (cfg.mipi_dt << (vc * 8));
571	ipu_csi_write(csi, temp, CSI_MIPI_DI);
572
573	spin_unlock_irqrestore(&csi->lock, flags);
574
575	return 0;
576}
577EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
578
579int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
580			  u32 max_ratio, u32 id)
581{
582	unsigned long flags;
583	u32 temp;
584
585	if (max_ratio > 5 || id > 3)
586		return -EINVAL;
587
588	spin_lock_irqsave(&csi->lock, flags);
589
590	temp = ipu_csi_read(csi, CSI_SKIP);
591	temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
592		  CSI_SKIP_SMFC_MASK);
593	temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
594		(id << CSI_ID_2_SKIP_SHIFT) |
595		(skip << CSI_SKIP_SMFC_SHIFT);
596	ipu_csi_write(csi, temp, CSI_SKIP);
597
598	spin_unlock_irqrestore(&csi->lock, flags);
599
600	return 0;
601}
602EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
603
604int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
605{
606	unsigned long flags;
607	u32 csi_sens_conf, dest;
608
609	if (csi_dest == IPU_CSI_DEST_IDMAC)
610		dest = CSI_DATA_DEST_IDMAC;
611	else
612		dest = CSI_DATA_DEST_IC; /* IC or VDIC */
613
614	spin_lock_irqsave(&csi->lock, flags);
615
616	csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
617	csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
618	csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
619	ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
620
621	spin_unlock_irqrestore(&csi->lock, flags);
622
623	return 0;
624}
625EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
626
627int ipu_csi_enable(struct ipu_csi *csi)
628{
629	ipu_module_enable(csi->ipu, csi->module);
630
631	return 0;
632}
633EXPORT_SYMBOL_GPL(ipu_csi_enable);
634
635int ipu_csi_disable(struct ipu_csi *csi)
636{
637	ipu_module_disable(csi->ipu, csi->module);
638
639	return 0;
640}
641EXPORT_SYMBOL_GPL(ipu_csi_disable);
642
643struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
644{
645	unsigned long flags;
646	struct ipu_csi *csi, *ret;
647
648	if (id > 1)
649		return ERR_PTR(-EINVAL);
650
651	csi = ipu->csi_priv[id];
652	ret = csi;
653
654	spin_lock_irqsave(&csi->lock, flags);
655
656	if (csi->inuse) {
657		ret = ERR_PTR(-EBUSY);
658		goto unlock;
659	}
660
661	csi->inuse = true;
662unlock:
663	spin_unlock_irqrestore(&csi->lock, flags);
664	return ret;
665}
666EXPORT_SYMBOL_GPL(ipu_csi_get);
667
668void ipu_csi_put(struct ipu_csi *csi)
669{
670	unsigned long flags;
671
672	spin_lock_irqsave(&csi->lock, flags);
673	csi->inuse = false;
674	spin_unlock_irqrestore(&csi->lock, flags);
675}
676EXPORT_SYMBOL_GPL(ipu_csi_put);
677
678int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
679		 unsigned long base, u32 module, struct clk *clk_ipu)
680{
681	struct ipu_csi *csi;
682
683	if (id > 1)
684		return -ENODEV;
685
686	csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
687	if (!csi)
688		return -ENOMEM;
689
690	ipu->csi_priv[id] = csi;
691
692	spin_lock_init(&csi->lock);
693	csi->module = module;
694	csi->id = id;
695	csi->clk_ipu = clk_ipu;
696	csi->base = devm_ioremap(dev, base, PAGE_SIZE);
697	if (!csi->base)
698		return -ENOMEM;
699
700	dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
701		id, base, csi->base);
702	csi->ipu = ipu;
703
704	return 0;
705}
706
707void ipu_csi_exit(struct ipu_soc *ipu, int id)
708{
709}
710
711void ipu_csi_dump(struct ipu_csi *csi)
712{
713	dev_dbg(csi->ipu->dev, "CSI_SENS_CONF:     %08x\n",
714		ipu_csi_read(csi, CSI_SENS_CONF));
715	dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
716		ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
717	dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE:  %08x\n",
718		ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
719	dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL:  %08x\n",
720		ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
721	dev_dbg(csi->ipu->dev, "CSI_TST_CTRL:      %08x\n",
722		ipu_csi_read(csi, CSI_TST_CTRL));
723	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1:   %08x\n",
724		ipu_csi_read(csi, CSI_CCIR_CODE_1));
725	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2:   %08x\n",
726		ipu_csi_read(csi, CSI_CCIR_CODE_2));
727	dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3:   %08x\n",
728		ipu_csi_read(csi, CSI_CCIR_CODE_3));
729	dev_dbg(csi->ipu->dev, "CSI_MIPI_DI:       %08x\n",
730		ipu_csi_read(csi, CSI_MIPI_DI));
731	dev_dbg(csi->ipu->dev, "CSI_SKIP:          %08x\n",
732		ipu_csi_read(csi, CSI_SKIP));
733}
734EXPORT_SYMBOL_GPL(ipu_csi_dump);