dev.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Tegra host1x driver
  4 *
  5 * Copyright (c) 2010-2013, NVIDIA Corporation.
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/delay.h>
 10#include <linux/dma-mapping.h>
 11#include <linux/io.h>
 12#include <linux/list.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/of_platform.h>
 16#include <linux/platform_device.h>
 17#include <linux/pm_runtime.h>
 18#include <linux/slab.h>
 19
 20#include <soc/tegra/common.h>
 21
 22#define CREATE_TRACE_POINTS
 23#include <trace/events/host1x.h>
 24#undef CREATE_TRACE_POINTS
 25
 26#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
 27#include <asm/dma-iommu.h>
 28#endif
 29
 30#include "bus.h"
 31#include "channel.h"
 32#include "context.h"
 33#include "debug.h"
 34#include "dev.h"
 35#include "intr.h"
 36
 37#include "hw/host1x01.h"
 38#include "hw/host1x02.h"
 39#include "hw/host1x04.h"
 40#include "hw/host1x05.h"
 41#include "hw/host1x06.h"
 42#include "hw/host1x07.h"
 43#include "hw/host1x08.h"
 44
 45void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
 46{
 47	writel(v, host1x->common_regs + r);
 48}
 49
 50void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
 51{
 52	writel(v, host1x->hv_regs + r);
 53}
 54
 55u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
 56{
 57	return readl(host1x->hv_regs + r);
 58}
 59
 60void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
 61{
 62	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
 63
 64	writel(v, sync_regs + r);
 65}
 66
 67u32 host1x_sync_readl(struct host1x *host1x, u32 r)
 68{
 69	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
 70
 71	return readl(sync_regs + r);
 72}
 73
 74#ifdef CONFIG_64BIT
 75u64 host1x_sync_readq(struct host1x *host1x, u32 r)
 76{
 77	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
 78
 79	return readq(sync_regs + r);
 80}
 81#endif
 82
 83void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
 84{
 85	writel(v, ch->regs + r);
 86}
 87
 88u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
 89{
 90	return readl(ch->regs + r);
 91}
 92
 93static const struct host1x_info host1x01_info = {
 94	.nb_channels = 8,
 95	.nb_pts = 32,
 96	.nb_mlocks = 16,
 97	.nb_bases = 8,
 98	.init = host1x01_init,
 99	.sync_offset = 0x3000,
100	.dma_mask = DMA_BIT_MASK(32),
101	.has_wide_gather = false,
102	.has_hypervisor = false,
103	.num_sid_entries = 0,
104	.sid_table = NULL,
105	.reserve_vblank_syncpts = true,
106};
107
108static const struct host1x_info host1x02_info = {
109	.nb_channels = 9,
110	.nb_pts = 32,
111	.nb_mlocks = 16,
112	.nb_bases = 12,
113	.init = host1x02_init,
114	.sync_offset = 0x3000,
115	.dma_mask = DMA_BIT_MASK(32),
116	.has_wide_gather = false,
117	.has_hypervisor = false,
118	.num_sid_entries = 0,
119	.sid_table = NULL,
120	.reserve_vblank_syncpts = true,
121};
122
123static const struct host1x_info host1x04_info = {
124	.nb_channels = 12,
125	.nb_pts = 192,
126	.nb_mlocks = 16,
127	.nb_bases = 64,
128	.init = host1x04_init,
129	.sync_offset = 0x2100,
130	.dma_mask = DMA_BIT_MASK(34),
131	.has_wide_gather = false,
132	.has_hypervisor = false,
133	.num_sid_entries = 0,
134	.sid_table = NULL,
135	.reserve_vblank_syncpts = false,
136};
137
138static const struct host1x_info host1x05_info = {
139	.nb_channels = 14,
140	.nb_pts = 192,
141	.nb_mlocks = 16,
142	.nb_bases = 64,
143	.init = host1x05_init,
144	.sync_offset = 0x2100,
145	.dma_mask = DMA_BIT_MASK(34),
146	.has_wide_gather = false,
147	.has_hypervisor = false,
148	.num_sid_entries = 0,
149	.sid_table = NULL,
150	.reserve_vblank_syncpts = false,
151};
152
153static const struct host1x_sid_entry tegra186_sid_table[] = {
154	{ /* SE1      */  .base = 0x1ac8, .offset = 0x90,    .limit = 0x90    },
155	{ /* SE2      */  .base = 0x1ad0, .offset = 0x90,    .limit = 0x90    },
156	{ /* SE3      */  .base = 0x1ad8, .offset = 0x90,    .limit = 0x90    },
157	{ /* SE4      */  .base = 0x1ae0, .offset = 0x90,    .limit = 0x90    },
158	{ /* ISP      */  .base = 0x1ae8, .offset = 0x50,    .limit = 0x50    },
159	{ /* VIC      */  .base = 0x1af0, .offset = 0x30,    .limit = 0x34    },
160	{ /* NVENC    */  .base = 0x1af8, .offset = 0x30,    .limit = 0x34    },
161	{ /* NVDEC    */  .base = 0x1b00, .offset = 0x30,    .limit = 0x34    },
162	{ /* NVJPG    */  .base = 0x1b08, .offset = 0x30,    .limit = 0x34    },
163	{ /* TSEC     */  .base = 0x1b10, .offset = 0x30,    .limit = 0x34    },
164	{ /* TSECB    */  .base = 0x1b18, .offset = 0x30,    .limit = 0x34    },
165	{ /* VI 0     */  .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
166	{ /* VI 1     */  .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
167	{ /* VI 2     */  .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
168	{ /* VI 3     */  .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
169	{ /* VI 4     */  .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
170	{ /* VI 5     */  .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
171	{ /* VI 6     */  .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
172	{ /* VI 7     */  .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
173	{ /* VI 8     */  .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
174	{ /* VI 9     */  .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
175	{ /* VI 10    */  .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
176	{ /* VI 11    */  .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
177};
178
179static const struct host1x_info host1x06_info = {
180	.nb_channels = 63,
181	.nb_pts = 576,
182	.nb_mlocks = 24,
183	.nb_bases = 16,
184	.init = host1x06_init,
185	.sync_offset = 0x0,
186	.dma_mask = DMA_BIT_MASK(40),
187	.has_wide_gather = true,
188	.has_hypervisor = true,
189	.num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
190	.sid_table = tegra186_sid_table,
191	.reserve_vblank_syncpts = false,
192	.skip_reset_assert = true,
193};
194
195static const struct host1x_sid_entry tegra194_sid_table[] = {
196	{ /* SE1          */  .base = 0x1ac8, .offset = 0x90,  .limit = 0x90  },
197	{ /* SE2          */  .base = 0x1ad0, .offset = 0x90,  .limit = 0x90  },
198	{ /* SE3          */  .base = 0x1ad8, .offset = 0x90,  .limit = 0x90  },
199	{ /* SE4          */  .base = 0x1ae0, .offset = 0x90,  .limit = 0x90  },
200	{ /* ISP          */  .base = 0x1ae8, .offset = 0x800, .limit = 0x800 },
201	{ /* VIC          */  .base = 0x1af0, .offset = 0x30,  .limit = 0x34  },
202	{ /* NVENC        */  .base = 0x1af8, .offset = 0x30,  .limit = 0x34  },
203	{ /* NVDEC        */  .base = 0x1b00, .offset = 0x30,  .limit = 0x34  },
204	{ /* NVJPG        */  .base = 0x1b08, .offset = 0x30,  .limit = 0x34  },
205	{ /* TSEC         */  .base = 0x1b10, .offset = 0x30,  .limit = 0x34  },
206	{ /* TSECB        */  .base = 0x1b18, .offset = 0x30,  .limit = 0x34  },
207	{ /* VI           */  .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
208	{ /* VI_THI       */  .base = 0x1b88, .offset = 0x30,  .limit = 0x34  },
209	{ /* ISP_THI      */  .base = 0x1b90, .offset = 0x30,  .limit = 0x34  },
210	{ /* PVA0_CLUSTER */  .base = 0x1b98, .offset = 0x0,   .limit = 0x0   },
211	{ /* PVA0_CLUSTER */  .base = 0x1ba0, .offset = 0x0,   .limit = 0x0   },
212	{ /* NVDLA0       */  .base = 0x1ba8, .offset = 0x30,  .limit = 0x34  },
213	{ /* NVDLA1       */  .base = 0x1bb0, .offset = 0x30,  .limit = 0x34  },
214	{ /* NVENC1       */  .base = 0x1bb8, .offset = 0x30,  .limit = 0x34  },
215	{ /* NVDEC1       */  .base = 0x1bc0, .offset = 0x30,  .limit = 0x34  },
216};
217
218static const struct host1x_info host1x07_info = {
219	.nb_channels = 63,
220	.nb_pts = 704,
221	.nb_mlocks = 32,
222	.nb_bases = 0,
223	.init = host1x07_init,
224	.sync_offset = 0x0,
225	.dma_mask = DMA_BIT_MASK(40),
226	.has_wide_gather = true,
227	.has_hypervisor = true,
228	.num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
229	.sid_table = tegra194_sid_table,
230	.reserve_vblank_syncpts = false,
231};
232
233/*
234 * Tegra234 has two stream ID protection tables, one for setting stream IDs
235 * through the channel path via SETSTREAMID, and one for setting them via
236 * MMIO. We program each engine's data stream ID in the channel path table
237 * and firmware stream ID in the MMIO path table.
238 */
239static const struct host1x_sid_entry tegra234_sid_table[] = {
240	{ /* SE1 MMIO     */  .base = 0x1650, .offset = 0x90,  .limit = 0x90  },
241	{ /* SE1 ch       */  .base = 0x1730, .offset = 0x90,  .limit = 0x90  },
242	{ /* SE2 MMIO     */  .base = 0x1658, .offset = 0x90,  .limit = 0x90  },
243	{ /* SE2 ch       */  .base = 0x1738, .offset = 0x90,  .limit = 0x90  },
244	{ /* SE4 MMIO     */  .base = 0x1660, .offset = 0x90,  .limit = 0x90  },
245	{ /* SE4 ch       */  .base = 0x1740, .offset = 0x90,  .limit = 0x90  },
246	{ /* ISP MMIO     */  .base = 0x1680, .offset = 0x800, .limit = 0x800 },
247	{ /* VIC MMIO     */  .base = 0x1688, .offset = 0x34,  .limit = 0x34  },
248	{ /* VIC ch       */  .base = 0x17b8, .offset = 0x30,  .limit = 0x30  },
249	{ /* NVENC MMIO   */  .base = 0x1690, .offset = 0x34,  .limit = 0x34  },
250	{ /* NVENC ch     */  .base = 0x17c0, .offset = 0x30,  .limit = 0x30  },
251	{ /* NVDEC MMIO   */  .base = 0x1698, .offset = 0x34,  .limit = 0x34  },
252	{ /* NVDEC ch     */  .base = 0x17c8, .offset = 0x30,  .limit = 0x30  },
253	{ /* NVJPG MMIO   */  .base = 0x16a0, .offset = 0x34,  .limit = 0x34  },
254	{ /* NVJPG ch     */  .base = 0x17d0, .offset = 0x30,  .limit = 0x30  },
255	{ /* TSEC MMIO    */  .base = 0x16a8, .offset = 0x30,  .limit = 0x34  },
256	{ /* NVJPG1 MMIO  */  .base = 0x16b0, .offset = 0x34,  .limit = 0x34  },
257	{ /* NVJPG1 ch    */  .base = 0x17a8, .offset = 0x30,  .limit = 0x30  },
258	{ /* VI MMIO      */  .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
259	{ /* VI_THI MMIO  */  .base = 0x16c0, .offset = 0x30,  .limit = 0x34  },
260	{ /* ISP_THI MMIO */  .base = 0x16c8, .offset = 0x30,  .limit = 0x34  },
261	{ /* NVDLA MMIO   */  .base = 0x16d8, .offset = 0x30,  .limit = 0x34  },
262	{ /* NVDLA ch     */  .base = 0x17e0, .offset = 0x30,  .limit = 0x34  },
263	{ /* NVDLA1 MMIO  */  .base = 0x16e0, .offset = 0x30,  .limit = 0x34  },
264	{ /* NVDLA1 ch    */  .base = 0x17e8, .offset = 0x30,  .limit = 0x34  },
265	{ /* OFA MMIO     */  .base = 0x16e8, .offset = 0x34,  .limit = 0x34  },
266	{ /* OFA ch       */  .base = 0x1768, .offset = 0x30,  .limit = 0x30  },
267	{ /* VI2 MMIO     */  .base = 0x16f0, .offset = 0x800, .limit = 0x800 },
268	{ /* VI2_THI MMIO */  .base = 0x16f8, .offset = 0x30,  .limit = 0x34  },
269};
270
271static const struct host1x_info host1x08_info = {
272	.nb_channels = 63,
273	.nb_pts = 1024,
274	.nb_mlocks = 24,
275	.nb_bases = 0,
276	.init = host1x08_init,
277	.sync_offset = 0x0,
278	.dma_mask = DMA_BIT_MASK(40),
279	.has_wide_gather = true,
280	.has_hypervisor = true,
281	.has_common = true,
282	.num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
283	.sid_table = tegra234_sid_table,
284	.streamid_vm_table = { 0x1004, 128 },
285	.classid_vm_table = { 0x1404, 25 },
286	.mmio_vm_table = { 0x1504, 25 },
287	.reserve_vblank_syncpts = false,
288};
289
290static const struct of_device_id host1x_of_match[] = {
291	{ .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
292	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
293	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
294	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
295	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
296	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
297	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
298	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
299	{ },
300};
301MODULE_DEVICE_TABLE(of, host1x_of_match);
302
303static void host1x_setup_virtualization_tables(struct host1x *host)
304{
305	const struct host1x_info *info = host->info;
306	unsigned int i;
307
308	if (!info->has_hypervisor)
309		return;
310
311	for (i = 0; i < info->num_sid_entries; i++) {
312		const struct host1x_sid_entry *entry = &info->sid_table[i];
313
314		host1x_hypervisor_writel(host, entry->offset, entry->base);
315		host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
316	}
317
318	for (i = 0; i < info->streamid_vm_table.count; i++) {
319		/* Allow access to all stream IDs to all VMs. */
320		host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
321	}
322
323	for (i = 0; i < info->classid_vm_table.count; i++) {
324		/* Allow access to all classes to all VMs. */
325		host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
326	}
327
328	for (i = 0; i < info->mmio_vm_table.count; i++) {
329		/* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
330		host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
331	}
332}
333
334static bool host1x_wants_iommu(struct host1x *host1x)
335{
336	/* Our IOMMU usage policy doesn't currently play well with GART */
337	if (of_machine_is_compatible("nvidia,tegra20"))
338		return false;
339
340	/*
341	 * If we support addressing a maximum of 32 bits of physical memory
342	 * and if the host1x firewall is enabled, there's no need to enable
343	 * IOMMU support. This can happen for example on Tegra20, Tegra30
344	 * and Tegra114.
345	 *
346	 * Tegra124 and later can address up to 34 bits of physical memory and
347	 * many platforms come equipped with more than 2 GiB of system memory,
348	 * which requires crossing the 4 GiB boundary. But there's a catch: on
349	 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
350	 * only address up to 32 bits of memory in GATHER opcodes, which means
351	 * that command buffers need to either be in the first 2 GiB of system
352	 * memory (which could quickly lead to memory exhaustion), or command
353	 * buffers need to be treated differently from other buffers (which is
354	 * not possible with the current ABI).
355	 *
356	 * A third option is to use the IOMMU in these cases to make sure all
357	 * buffers will be mapped into a 32-bit IOVA space that host1x can
358	 * address. This allows all of the system memory to be used and works
359	 * within the limitations of the host1x on these SoCs.
360	 *
361	 * In summary, default to enable IOMMU on Tegra124 and later. For any
362	 * of the earlier SoCs, only use the IOMMU for additional safety when
363	 * the host1x firewall is disabled.
364	 */
365	if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
366		if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
367			return false;
368	}
369
370	return true;
371}
372
373/*
374 * Returns ERR_PTR on failure, NULL if the translation is IDENTITY, otherwise a
375 * valid paging domain.
376 */
377static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
378{
379	struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
380	int err;
381
382#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
383	if (host->dev->archdata.mapping) {
384		struct dma_iommu_mapping *mapping =
385				to_dma_iommu_mapping(host->dev);
386		arm_iommu_detach_device(host->dev);
387		arm_iommu_release_mapping(mapping);
388
389		domain = iommu_get_domain_for_dev(host->dev);
390	}
391#endif
392
393	/*
394	 * We may not always want to enable IOMMU support (for example if the
395	 * host1x firewall is already enabled and we don't support addressing
396	 * more than 32 bits of physical memory), so check for that first.
397	 *
398	 * Similarly, if host1x is already attached to an IOMMU (via the DMA
399	 * API), don't try to attach again.
400	 */
401	if (domain && domain->type == IOMMU_DOMAIN_IDENTITY)
402		domain = NULL;
403	if (!host1x_wants_iommu(host) || domain)
404		return domain;
405
406	host->group = iommu_group_get(host->dev);
407	if (host->group) {
408		struct iommu_domain_geometry *geometry;
409		dma_addr_t start, end;
410		unsigned long order;
411
412		err = iova_cache_get();
413		if (err < 0)
414			goto put_group;
415
416		host->domain = iommu_paging_domain_alloc(host->dev);
417		if (IS_ERR(host->domain)) {
418			err = PTR_ERR(host->domain);
419			host->domain = NULL;
420			goto put_cache;
421		}
422
423		err = iommu_attach_group(host->domain, host->group);
424		if (err) {
425			if (err == -ENODEV)
426				err = 0;
427
428			goto free_domain;
429		}
430
431		geometry = &host->domain->geometry;
432		start = geometry->aperture_start & host->info->dma_mask;
433		end = geometry->aperture_end & host->info->dma_mask;
434
435		order = __ffs(host->domain->pgsize_bitmap);
436		init_iova_domain(&host->iova, 1UL << order, start >> order);
437		host->iova_end = end;
438
439		domain = host->domain;
440	}
441
442	return domain;
443
444free_domain:
445	iommu_domain_free(host->domain);
446	host->domain = NULL;
447put_cache:
448	iova_cache_put();
449put_group:
450	iommu_group_put(host->group);
451	host->group = NULL;
452
453	return ERR_PTR(err);
454}
455
456static int host1x_iommu_init(struct host1x *host)
457{
458	u64 mask = host->info->dma_mask;
459	struct iommu_domain *domain;
460	int err;
461
462	domain = host1x_iommu_attach(host);
463	if (IS_ERR(domain)) {
464		err = PTR_ERR(domain);
465		dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
466		return err;
467	}
468
469	/*
470	 * If we're not behind an IOMMU make sure we don't get push buffers
471	 * that are allocated outside of the range addressable by the GATHER
472	 * opcode.
473	 *
474	 * Newer generations of Tegra (Tegra186 and later) support a wide
475	 * variant of the GATHER opcode that allows addressing more bits.
476	 */
477	if (!domain && !host->info->has_wide_gather)
478		mask = DMA_BIT_MASK(32);
479
480	err = dma_coerce_mask_and_coherent(host->dev, mask);
481	if (err < 0) {
482		dev_err(host->dev, "failed to set DMA mask: %d\n", err);
483		return err;
484	}
485
486	return 0;
487}
488
489static void host1x_iommu_exit(struct host1x *host)
490{
491	if (host->domain) {
492		put_iova_domain(&host->iova);
493		iommu_detach_group(host->domain, host->group);
494
495		iommu_domain_free(host->domain);
496		host->domain = NULL;
497
498		iova_cache_put();
499
500		iommu_group_put(host->group);
501		host->group = NULL;
502	}
503}
504
505static int host1x_get_resets(struct host1x *host)
506{
507	int err;
508
509	host->resets[0].id = "mc";
510	host->resets[1].id = "host1x";
511	host->nresets = ARRAY_SIZE(host->resets);
512
513	err = devm_reset_control_bulk_get_optional_exclusive_released(
514				host->dev, host->nresets, host->resets);
515	if (err) {
516		dev_err(host->dev, "failed to get reset: %d\n", err);
517		return err;
518	}
519
520	return 0;
521}
522
523static int host1x_probe(struct platform_device *pdev)
524{
525	struct host1x *host;
526	int err, i;
527
528	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
529	if (!host)
530		return -ENOMEM;
531
532	host->info = of_device_get_match_data(&pdev->dev);
533
534	if (host->info->has_hypervisor) {
535		host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
536		if (IS_ERR(host->regs))
537			return PTR_ERR(host->regs);
538
539		host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
540		if (IS_ERR(host->hv_regs))
541			return PTR_ERR(host->hv_regs);
542
543		if (host->info->has_common) {
544			host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
545			if (IS_ERR(host->common_regs))
546				return PTR_ERR(host->common_regs);
547		}
548	} else {
549		host->regs = devm_platform_ioremap_resource(pdev, 0);
550		if (IS_ERR(host->regs))
551			return PTR_ERR(host->regs);
552	}
553
554	for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) {
555		char irq_name[] = "syncptX";
556
557		sprintf(irq_name, "syncpt%d", i);
558
559		err = platform_get_irq_byname_optional(pdev, irq_name);
560		if (err == -ENXIO)
561			break;
562		if (err < 0)
563			return err;
564
565		host->syncpt_irqs[i] = err;
566	}
567
568	host->num_syncpt_irqs = i;
569
570	/* Device tree without irq names */
571	if (i == 0) {
572		host->syncpt_irqs[0] = platform_get_irq(pdev, 0);
573		if (host->syncpt_irqs[0] < 0)
574			return host->syncpt_irqs[0];
575
576		host->num_syncpt_irqs = 1;
577	}
578
579	mutex_init(&host->devices_lock);
580	INIT_LIST_HEAD(&host->devices);
581	INIT_LIST_HEAD(&host->list);
582	host->dev = &pdev->dev;
583
584	/* set common host1x device data */
585	platform_set_drvdata(pdev, host);
586
587	host->dev->dma_parms = &host->dma_parms;
588	dma_set_max_seg_size(host->dev, UINT_MAX);
589
590	if (host->info->init) {
591		err = host->info->init(host);
592		if (err)
593			return err;
594	}
595
596	host->clk = devm_clk_get(&pdev->dev, NULL);
597	if (IS_ERR(host->clk))
598		return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "failed to get clock\n");
599
600	err = host1x_get_resets(host);
601	if (err)
602		return err;
603
604	host1x_bo_cache_init(&host->cache);
605
606	err = host1x_iommu_init(host);
607	if (err < 0) {
608		dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
609		goto destroy_cache;
610	}
611
612	err = host1x_channel_list_init(&host->channel_list,
613				       host->info->nb_channels);
614	if (err) {
615		dev_err(&pdev->dev, "failed to initialize channel list\n");
616		goto iommu_exit;
617	}
618
619	err = host1x_memory_context_list_init(host);
620	if (err) {
621		dev_err(&pdev->dev, "failed to initialize context list\n");
622		goto free_channels;
623	}
624
625	err = host1x_syncpt_init(host);
626	if (err) {
627		dev_err(&pdev->dev, "failed to initialize syncpts\n");
628		goto free_contexts;
629	}
630
631	mutex_init(&host->intr_mutex);
632
633	pm_runtime_enable(&pdev->dev);
634
635	err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
636	if (err)
637		goto pm_disable;
638
639	/* the driver's code isn't ready yet for the dynamic RPM */
640	err = pm_runtime_resume_and_get(&pdev->dev);
641	if (err)
642		goto pm_disable;
643
644	err = host1x_intr_init(host);
645	if (err) {
646		dev_err(&pdev->dev, "failed to initialize interrupts\n");
647		goto pm_put;
648	}
649
650	host1x_debug_init(host);
651
652	err = host1x_register(host);
653	if (err < 0)
654		goto deinit_debugfs;
655
656	err = devm_of_platform_populate(&pdev->dev);
657	if (err < 0)
658		goto unregister;
659
660	return 0;
661
662unregister:
663	host1x_unregister(host);
664deinit_debugfs:
665	host1x_debug_deinit(host);
666	host1x_intr_deinit(host);
667pm_put:
668	pm_runtime_put_sync_suspend(&pdev->dev);
669pm_disable:
670	pm_runtime_disable(&pdev->dev);
671	host1x_syncpt_deinit(host);
672free_contexts:
673	host1x_memory_context_list_free(&host->context_list);
674free_channels:
675	host1x_channel_list_free(&host->channel_list);
676iommu_exit:
677	host1x_iommu_exit(host);
678destroy_cache:
679	host1x_bo_cache_destroy(&host->cache);
680
681	return err;
682}
683
684static void host1x_remove(struct platform_device *pdev)
685{
686	struct host1x *host = platform_get_drvdata(pdev);
687
688	host1x_unregister(host);
689	host1x_debug_deinit(host);
690
691	pm_runtime_force_suspend(&pdev->dev);
692
693	host1x_intr_deinit(host);
694	host1x_syncpt_deinit(host);
695	host1x_memory_context_list_free(&host->context_list);
696	host1x_channel_list_free(&host->channel_list);
697	host1x_iommu_exit(host);
698	host1x_bo_cache_destroy(&host->cache);
699}
700
701static int __maybe_unused host1x_runtime_suspend(struct device *dev)
702{
703	struct host1x *host = dev_get_drvdata(dev);
704	int err;
705
706	host1x_channel_stop_all(host);
707	host1x_intr_stop(host);
708	host1x_syncpt_save(host);
709
710	if (!host->info->skip_reset_assert) {
711		err = reset_control_bulk_assert(host->nresets, host->resets);
712		if (err) {
713			dev_err(dev, "failed to assert reset: %d\n", err);
714			goto resume_host1x;
715		}
716
717		usleep_range(1000, 2000);
718	}
719
720	clk_disable_unprepare(host->clk);
721	reset_control_bulk_release(host->nresets, host->resets);
722
723	return 0;
724
725resume_host1x:
726	host1x_setup_virtualization_tables(host);
727	host1x_syncpt_restore(host);
728	host1x_intr_start(host);
729
730	return err;
731}
732
733static int __maybe_unused host1x_runtime_resume(struct device *dev)
734{
735	struct host1x *host = dev_get_drvdata(dev);
736	int err;
737
738	err = reset_control_bulk_acquire(host->nresets, host->resets);
739	if (err) {
740		dev_err(dev, "failed to acquire reset: %d\n", err);
741		return err;
742	}
743
744	err = clk_prepare_enable(host->clk);
745	if (err) {
746		dev_err(dev, "failed to enable clock: %d\n", err);
747		goto release_reset;
748	}
749
750	err = reset_control_bulk_deassert(host->nresets, host->resets);
751	if (err < 0) {
752		dev_err(dev, "failed to deassert reset: %d\n", err);
753		goto disable_clk;
754	}
755
756	host1x_setup_virtualization_tables(host);
757	host1x_syncpt_restore(host);
758	host1x_intr_start(host);
759
760	return 0;
761
762disable_clk:
763	clk_disable_unprepare(host->clk);
764release_reset:
765	reset_control_bulk_release(host->nresets, host->resets);
766
767	return err;
768}
769
770static const struct dev_pm_ops host1x_pm_ops = {
771	SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume,
772			   NULL)
773	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
774};
775
776static struct platform_driver tegra_host1x_driver = {
777	.driver = {
778		.name = "tegra-host1x",
779		.of_match_table = host1x_of_match,
780		.pm = &host1x_pm_ops,
781	},
782	.probe = host1x_probe,
783	.remove = host1x_remove,
784};
785
786static struct platform_driver * const drivers[] = {
787	&tegra_host1x_driver,
788	&tegra_mipi_driver,
789};
790
791static int __init tegra_host1x_init(void)
792{
793	int err;
794
795	err = bus_register(&host1x_bus_type);
796	if (err < 0)
797		return err;
798
799	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
800	if (err < 0)
801		bus_unregister(&host1x_bus_type);
802
803	return err;
804}
805module_init(tegra_host1x_init);
806
807static void __exit tegra_host1x_exit(void)
808{
809	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
810	bus_unregister(&host1x_bus_type);
811}
812module_exit(tegra_host1x_exit);
813
814/**
815 * host1x_get_dma_mask() - query the supported DMA mask for host1x
816 * @host1x: host1x instance
817 *
818 * Note that this returns the supported DMA mask for host1x, which can be
819 * different from the applicable DMA mask under certain circumstances.
820 */
821u64 host1x_get_dma_mask(struct host1x *host1x)
822{
823	return host1x->info->dma_mask;
824}
825EXPORT_SYMBOL(host1x_get_dma_mask);
826
827MODULE_SOFTDEP("post: tegra-drm");
828MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
829MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
830MODULE_DESCRIPTION("Host1x driver for Tegra products");
831MODULE_LICENSE("GPL");