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zynqmp_dp.c
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linux-6.19.14/drivers/gpu/drm/xlnx/zynqmp_dp.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ZynqMP DisplayPort Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12#include <drm/display/drm_dp_helper.h> 13#include <drm/drm_atomic_helper.h> 14#include <drm/drm_crtc.h> 15#include <drm/drm_device.h> 16#include <drm/drm_edid.h> 17#include <drm/drm_fourcc.h> 18#include <drm/drm_modes.h> 19#include <drm/drm_of.h> 20 21#include <linux/bitfield.h> 22#include <linux/clk.h> 23#include <linux/debugfs.h> 24#include <linux/delay.h> 25#include <linux/device.h> 26#include <linux/io.h> 27#include <linux/media-bus-format.h> 28#include <linux/module.h> 29#include <linux/platform_device.h> 30#include <linux/pm_runtime.h> 31#include <linux/phy/phy.h> 32#include <linux/reset.h> 33#include <linux/slab.h> 34 35#include "zynqmp_disp.h" 36#include "zynqmp_dp.h" 37#include "zynqmp_dpsub.h" 38#include "zynqmp_kms.h" 39 40static uint zynqmp_dp_aux_timeout_ms = 50; 41module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); 42MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); 43 44/* 45 * Some sink requires a delay after power on request 46 */ 47static uint zynqmp_dp_power_on_delay_ms = 4; 48module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); 49MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)"); 50 51/* Link configuration registers */ 52#define ZYNQMP_DP_LINK_BW_SET 0x0 53#define ZYNQMP_DP_LANE_COUNT_SET 0x4 54#define ZYNQMP_DP_ENHANCED_FRAME_EN 0x8 55#define ZYNQMP_DP_TRAINING_PATTERN_SET 0xc 56#define ZYNQMP_DP_LINK_QUAL_PATTERN_SET 0x10 57#define ZYNQMP_DP_SCRAMBLING_DISABLE 0x14 58#define ZYNQMP_DP_DOWNSPREAD_CTL 0x18 59#define ZYNQMP_DP_SOFTWARE_RESET 0x1c 60#define ZYNQMP_DP_SOFTWARE_RESET_STREAM1 BIT(0) 61#define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 BIT(1) 62#define ZYNQMP_DP_SOFTWARE_RESET_STREAM3 BIT(2) 63#define ZYNQMP_DP_SOFTWARE_RESET_STREAM4 BIT(3) 64#define ZYNQMP_DP_SOFTWARE_RESET_AUX BIT(7) 65#define ZYNQMP_DP_SOFTWARE_RESET_ALL (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \ 66 ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \ 67 ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \ 68 ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \ 69 ZYNQMP_DP_SOFTWARE_RESET_AUX) 70#define ZYNQMP_DP_COMP_PATTERN_80BIT_1 0x20 71#define ZYNQMP_DP_COMP_PATTERN_80BIT_2 0x24 72#define ZYNQMP_DP_COMP_PATTERN_80BIT_3 0x28 73 74/* Core enable registers */ 75#define ZYNQMP_DP_TRANSMITTER_ENABLE 0x80 76#define ZYNQMP_DP_MAIN_STREAM_ENABLE 0x84 77#define ZYNQMP_DP_FORCE_SCRAMBLER_RESET 0xc0 78#define ZYNQMP_DP_VERSION 0xf8 79#define ZYNQMP_DP_VERSION_MAJOR_MASK GENMASK(31, 24) 80#define ZYNQMP_DP_VERSION_MAJOR_SHIFT 24 81#define ZYNQMP_DP_VERSION_MINOR_MASK GENMASK(23, 16) 82#define ZYNQMP_DP_VERSION_MINOR_SHIFT 16 83#define ZYNQMP_DP_VERSION_REVISION_MASK GENMASK(15, 12) 84#define ZYNQMP_DP_VERSION_REVISION_SHIFT 12 85#define ZYNQMP_DP_VERSION_PATCH_MASK GENMASK(11, 8) 86#define ZYNQMP_DP_VERSION_PATCH_SHIFT 8 87#define ZYNQMP_DP_VERSION_INTERNAL_MASK GENMASK(7, 0) 88#define ZYNQMP_DP_VERSION_INTERNAL_SHIFT 0 89 90/* Core ID registers */ 91#define ZYNQMP_DP_CORE_ID 0xfc 92#define ZYNQMP_DP_CORE_ID_MAJOR_MASK GENMASK(31, 24) 93#define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT 24 94#define ZYNQMP_DP_CORE_ID_MINOR_MASK GENMASK(23, 16) 95#define ZYNQMP_DP_CORE_ID_MINOR_SHIFT 16 96#define ZYNQMP_DP_CORE_ID_REVISION_MASK GENMASK(15, 8) 97#define ZYNQMP_DP_CORE_ID_REVISION_SHIFT 8 98#define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1) 99 100/* AUX channel interface registers */ 101#define ZYNQMP_DP_AUX_COMMAND 0x100 102#define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT 8 103#define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY BIT(12) 104#define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT 0 105#define ZYNQMP_DP_AUX_WRITE_FIFO 0x104 106#define ZYNQMP_DP_AUX_ADDRESS 0x108 107#define ZYNQMP_DP_AUX_CLK_DIVIDER 0x10c 108#define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT 8 109#define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE 0x130 110#define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD BIT(0) 111#define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST BIT(1) 112#define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY BIT(2) 113#define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT BIT(3) 114#define ZYNQMP_DP_AUX_REPLY_DATA 0x134 115#define ZYNQMP_DP_AUX_REPLY_CODE 0x138 116#define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK (0) 117#define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK BIT(0) 118#define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER BIT(1) 119#define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK (0) 120#define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK BIT(2) 121#define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER BIT(3) 122#define ZYNQMP_DP_AUX_REPLY_COUNT 0x13c 123#define ZYNQMP_DP_REPLY_DATA_COUNT 0x148 124#define ZYNQMP_DP_REPLY_DATA_COUNT_MASK 0xff 125#define ZYNQMP_DP_INT_STATUS 0x3a0 126#define ZYNQMP_DP_INT_MASK 0x3a4 127#define ZYNQMP_DP_INT_EN 0x3a8 128#define ZYNQMP_DP_INT_DS 0x3ac 129#define ZYNQMP_DP_INT_HPD_IRQ BIT(0) 130#define ZYNQMP_DP_INT_HPD_EVENT BIT(1) 131#define ZYNQMP_DP_INT_REPLY_RECEIVED BIT(2) 132#define ZYNQMP_DP_INT_REPLY_TIMEOUT BIT(3) 133#define ZYNQMP_DP_INT_HPD_PULSE_DET BIT(4) 134#define ZYNQMP_DP_INT_EXT_PKT_TXD BIT(5) 135#define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW BIT(12) 136#define ZYNQMP_DP_INT_VBLANK_START BIT(13) 137#define ZYNQMP_DP_INT_PIXEL1_MATCH BIT(14) 138#define ZYNQMP_DP_INT_PIXEL0_MATCH BIT(15) 139#define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK 0x3f0000 140#define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK 0xfc00000 141#define ZYNQMP_DP_INT_CUST_TS_2 BIT(28) 142#define ZYNQMP_DP_INT_CUST_TS BIT(29) 143#define ZYNQMP_DP_INT_EXT_VSYNC_TS BIT(30) 144#define ZYNQMP_DP_INT_VSYNC_TS BIT(31) 145#define ZYNQMP_DP_INT_ALL (ZYNQMP_DP_INT_HPD_IRQ | \ 146 ZYNQMP_DP_INT_HPD_EVENT | \ 147 ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \ 148 ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 149 150/* Main stream attribute registers */ 151#define ZYNQMP_DP_MAIN_STREAM_HTOTAL 0x180 152#define ZYNQMP_DP_MAIN_STREAM_VTOTAL 0x184 153#define ZYNQMP_DP_MAIN_STREAM_POLARITY 0x188 154#define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT 0 155#define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT 1 156#define ZYNQMP_DP_MAIN_STREAM_HSWIDTH 0x18c 157#define ZYNQMP_DP_MAIN_STREAM_VSWIDTH 0x190 158#define ZYNQMP_DP_MAIN_STREAM_HRES 0x194 159#define ZYNQMP_DP_MAIN_STREAM_VRES 0x198 160#define ZYNQMP_DP_MAIN_STREAM_HSTART 0x19c 161#define ZYNQMP_DP_MAIN_STREAM_VSTART 0x1a0 162#define ZYNQMP_DP_MAIN_STREAM_MISC0 0x1a4 163#define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK BIT(0) 164#define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB (0 << 1) 165#define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422 (5 << 1) 166#define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444 (6 << 1) 167#define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK (7 << 1) 168#define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE BIT(3) 169#define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR BIT(4) 170#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6 (0 << 5) 171#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8 (1 << 5) 172#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10 (2 << 5) 173#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12 (3 << 5) 174#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16 (4 << 5) 175#define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK (7 << 5) 176#define ZYNQMP_DP_MAIN_STREAM_MISC1 0x1a8 177#define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN BIT(7) 178#define ZYNQMP_DP_MAIN_STREAM_M_VID 0x1ac 179#define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE 0x1b0 180#define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF 64 181#define ZYNQMP_DP_MAIN_STREAM_N_VID 0x1b4 182#define ZYNQMP_DP_USER_PIX_WIDTH 0x1b8 183#define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE 0x1bc 184#define ZYNQMP_DP_MIN_BYTES_PER_TU 0x1c4 185#define ZYNQMP_DP_FRAC_BYTES_PER_TU 0x1c8 186#define ZYNQMP_DP_INIT_WAIT 0x1cc 187 188/* PHY configuration and status registers */ 189#define ZYNQMP_DP_PHY_RESET 0x200 190#define ZYNQMP_DP_PHY_RESET_PHY_RESET BIT(0) 191#define ZYNQMP_DP_PHY_RESET_GTTX_RESET BIT(1) 192#define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET BIT(8) 193#define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET BIT(9) 194#define ZYNQMP_DP_PHY_RESET_ALL_RESET (ZYNQMP_DP_PHY_RESET_PHY_RESET | \ 195 ZYNQMP_DP_PHY_RESET_GTTX_RESET | \ 196 ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \ 197 ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET) 198#define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0 0x210 199#define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1 0x214 200#define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2 0x218 201#define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3 0x21c 202#define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0 0x220 203#define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1 0x224 204#define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2 0x228 205#define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3 0x22c 206#define ZYNQMP_DP_PHY_CLOCK_SELECT 0x234 207#define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G 0x1 208#define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G 0x3 209#define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G 0x5 210#define ZYNQMP_DP_TX_PHY_POWER_DOWN 0x238 211#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0 BIT(0) 212#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1 BIT(1) 213#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2 BIT(2) 214#define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3 BIT(3) 215#define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL 0xf 216#define ZYNQMP_DP_TRANSMIT_PRBS7 0x230 217#define ZYNQMP_DP_PHY_PRECURSOR_LANE_0 0x23c 218#define ZYNQMP_DP_PHY_PRECURSOR_LANE_1 0x240 219#define ZYNQMP_DP_PHY_PRECURSOR_LANE_2 0x244 220#define ZYNQMP_DP_PHY_PRECURSOR_LANE_3 0x248 221#define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0 0x24c 222#define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1 0x250 223#define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2 0x254 224#define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3 0x258 225#define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 0x24c 226#define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1 0x250 227#define ZYNQMP_DP_PHY_STATUS 0x280 228#define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT 4 229#define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED BIT(6) 230 231/* Audio registers */ 232#define ZYNQMP_DP_TX_AUDIO_CONTROL 0x300 233#define ZYNQMP_DP_TX_AUDIO_CHANNELS 0x304 234#define ZYNQMP_DP_TX_AUDIO_INFO_DATA 0x308 235#define ZYNQMP_DP_TX_M_AUD 0x328 236#define ZYNQMP_DP_TX_N_AUD 0x32c 237#define ZYNQMP_DP_TX_AUDIO_EXT_DATA 0x330 238 239#define ZYNQMP_DP_MAX_LANES 2 240#define ZYNQMP_MAX_FREQ 3000000 241 242#define DP_REDUCED_BIT_RATE 162000 243#define DP_HIGH_BIT_RATE 270000 244#define DP_HIGH_BIT_RATE2 540000 245#define DP_MAX_TRAINING_TRIES 5 246#define DP_V1_2 0x12 247 248/** 249 * struct zynqmp_dp_link_config - Common link config between source and sink 250 * @max_rate: maximum link rate 251 * @max_lanes: maximum number of lanes 252 */ 253struct zynqmp_dp_link_config { 254 int max_rate; 255 u8 max_lanes; 256}; 257 258/** 259 * struct zynqmp_dp_mode - Configured mode of DisplayPort 260 * @bw_code: code for bandwidth(link rate) 261 * @lane_cnt: number of lanes 262 * @pclock: pixel clock frequency of current mode 263 * @fmt: format identifier string 264 */ 265struct zynqmp_dp_mode { 266 const char *fmt; 267 int pclock; 268 u8 bw_code; 269 u8 lane_cnt; 270}; 271 272/** 273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS 274 * @misc0: misc0 configuration (per DP v1.2 spec) 275 * @misc1: misc1 configuration (per DP v1.2 spec) 276 * @bpp: bits per pixel 277 */ 278struct zynqmp_dp_config { 279 u8 misc0; 280 u8 misc1; 281 u8 bpp; 282}; 283 284/** 285 * enum test_pattern - Test patterns for test testing 286 * @TEST_VIDEO: Use regular video input 287 * @TEST_SYMBOL_ERROR: Symbol error measurement pattern 288 * @TEST_PRBS7: Output of the PRBS7 (x^7 + x^6 + 1) polynomial 289 * @TEST_80BIT_CUSTOM: A custom 80-bit pattern 290 * @TEST_CP2520: HBR2 compliance eye pattern 291 * @TEST_TPS1: Link training symbol pattern TPS1 (/D10.2/) 292 * @TEST_TPS2: Link training symbol pattern TPS2 293 * @TEST_TPS3: Link training symbol pattern TPS3 (for HBR2) 294 */ 295enum test_pattern { 296 TEST_VIDEO, 297 TEST_TPS1, 298 TEST_TPS2, 299 TEST_TPS3, 300 TEST_SYMBOL_ERROR, 301 TEST_PRBS7, 302 TEST_80BIT_CUSTOM, 303 TEST_CP2520, 304}; 305 306static const char *const test_pattern_str[] = { 307 [TEST_VIDEO] = "video", 308 [TEST_TPS1] = "tps1", 309 [TEST_TPS2] = "tps2", 310 [TEST_TPS3] = "tps3", 311 [TEST_SYMBOL_ERROR] = "symbol-error", 312 [TEST_PRBS7] = "prbs7", 313 [TEST_80BIT_CUSTOM] = "80bit-custom", 314 [TEST_CP2520] = "cp2520", 315}; 316 317/** 318 * struct zynqmp_dp_test - Configuration for test mode 319 * @pattern: The test pattern 320 * @enhanced: Use enhanced framing 321 * @downspread: Use SSC 322 * @active: Whether test mode is active 323 * @custom: Custom pattern for %TEST_80BIT_CUSTOM 324 * @train_set: Voltage/preemphasis settings 325 * @bw_code: Bandwidth code for the link 326 * @link_cnt: Number of lanes 327 */ 328struct zynqmp_dp_test { 329 enum test_pattern pattern; 330 bool enhanced, downspread, active; 331 u8 custom[10]; 332 u8 train_set[ZYNQMP_DP_MAX_LANES]; 333 u8 bw_code; 334 u8 link_cnt; 335}; 336 337/** 338 * struct zynqmp_dp_train_set_priv - Private data for train_set debugfs files 339 * @dp: DisplayPort IP core structure 340 * @lane: The lane for this file 341 */ 342struct zynqmp_dp_train_set_priv { 343 struct zynqmp_dp *dp; 344 int lane; 345}; 346 347/** 348 * struct zynqmp_dp - Xilinx DisplayPort core 349 * @dev: device structure 350 * @dpsub: Display subsystem 351 * @iomem: device I/O memory for register access 352 * @reset: reset controller 353 * @lock: Mutex protecting this struct and register access (but not AUX) 354 * @irq: irq 355 * @bridge: DRM bridge for the DP encoder 356 * @next_bridge: The downstream bridge 357 * @test: Configuration for test mode 358 * @config: IP core configuration from DTS 359 * @aux: aux channel 360 * @aux_done: Completed when we get an AUX reply or timeout 361 * @ignore_aux_errors: If set, AUX errors are suppressed 362 * @phy: PHY handles for DP lanes 363 * @num_lanes: number of enabled phy lanes 364 * @hpd_work: hot plug detection worker 365 * @hpd_irq_work: hot plug detection IRQ worker 366 * @ignore_hpd: If set, HPD events and IRQs are ignored 367 * @status: connection status 368 * @enabled: flag to indicate if the device is enabled 369 * @dpcd: DP configuration data from currently connected sink device 370 * @link_config: common link configuration between IP core and sink device 371 * @mode: current mode between IP core and sink device 372 * @train_set: set of training data 373 * @debugfs_train_set: Debugfs private data for @train_set 374 * 375 * @lock covers the link configuration in this struct and the device's 376 * registers. It does not cover @aux or @ignore_aux_errors. It is not strictly 377 * required for any of the members which are only modified at probe/remove time 378 * (e.g. @dev). 379 */ 380struct zynqmp_dp { 381 struct drm_dp_aux aux; 382 struct drm_bridge bridge; 383 struct work_struct hpd_work; 384 struct work_struct hpd_irq_work; 385 struct completion aux_done; 386 struct mutex lock; 387 388 struct drm_bridge *next_bridge; 389 struct device *dev; 390 struct zynqmp_dpsub *dpsub; 391 void __iomem *iomem; 392 struct reset_control *reset; 393 struct phy *phy[ZYNQMP_DP_MAX_LANES]; 394 395 enum drm_connector_status status; 396 int irq; 397 bool enabled; 398 bool ignore_aux_errors; 399 bool ignore_hpd; 400 401 struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES]; 402 struct zynqmp_dp_mode mode; 403 struct zynqmp_dp_link_config link_config; 404 struct zynqmp_dp_test test; 405 struct zynqmp_dp_config config; 406 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 407 u8 train_set[ZYNQMP_DP_MAX_LANES]; 408 u8 num_lanes; 409}; 410 411static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge) 412{ 413 return container_of(bridge, struct zynqmp_dp, bridge); 414} 415 416static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val) 417{ 418 writel(val, dp->iomem + offset); 419} 420 421static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset) 422{ 423 return readl(dp->iomem + offset); 424} 425 426static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) 427{ 428 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr); 429} 430 431static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set) 432{ 433 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set); 434} 435 436/* ----------------------------------------------------------------------------- 437 * PHY Handling 438 */ 439 440#define RST_TIMEOUT_MS 1000 441 442static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert) 443{ 444 unsigned long timeout; 445 446 if (assert) 447 reset_control_assert(dp->reset); 448 else 449 reset_control_deassert(dp->reset); 450 451 /* Wait for the (de)assert to complete. */ 452 timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS); 453 while (!time_after_eq(jiffies, timeout)) { 454 bool status = !!reset_control_status(dp->reset); 455 456 if (assert == status) 457 return 0; 458 459 cpu_relax(); 460 } 461 462 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert"); 463 return -ETIMEDOUT; 464} 465 466/** 467 * zynqmp_dp_phy_init - Initialize the phy 468 * @dp: DisplayPort IP core structure 469 * 470 * Initialize the phy. 471 * 472 * Return: 0 if the phy instances are initialized correctly, or the error code 473 * returned from the callee functions. 474 */ 475static int zynqmp_dp_phy_init(struct zynqmp_dp *dp) 476{ 477 int ret; 478 int i; 479 480 for (i = 0; i < dp->num_lanes; i++) { 481 ret = phy_init(dp->phy[i]); 482 if (ret) { 483 dev_err(dp->dev, "failed to init phy lane %d\n", i); 484 return ret; 485 } 486 } 487 488 zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 489 490 /* 491 * Power on lanes in reverse order as only lane 0 waits for the PLL to 492 * lock. 493 */ 494 for (i = dp->num_lanes - 1; i >= 0; i--) { 495 ret = phy_power_on(dp->phy[i]); 496 if (ret) { 497 dev_err(dp->dev, "failed to power on phy lane %d\n", i); 498 return ret; 499 } 500 } 501 502 return 0; 503} 504 505/** 506 * zynqmp_dp_phy_exit - Exit the phy 507 * @dp: DisplayPort IP core structure 508 * 509 * Exit the phy. 510 */ 511static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp) 512{ 513 unsigned int i; 514 int ret; 515 516 for (i = 0; i < dp->num_lanes; i++) { 517 ret = phy_power_off(dp->phy[i]); 518 if (ret) 519 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i, 520 ret); 521 } 522 523 for (i = 0; i < dp->num_lanes; i++) { 524 ret = phy_exit(dp->phy[i]); 525 if (ret) 526 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret); 527 } 528} 529 530/** 531 * zynqmp_dp_phy_probe - Probe the PHYs 532 * @dp: DisplayPort IP core structure 533 * 534 * Probe PHYs for all lanes. Less PHYs may be available than the number of 535 * lanes, which is not considered an error as long as at least one PHY is 536 * found. The caller can check dp->num_lanes to check how many PHYs were found. 537 * 538 * Return: 539 * * 0 - Success 540 * * -ENXIO - No PHY found 541 * * -EPROBE_DEFER - Probe deferral requested 542 * * Other negative value - PHY retrieval failure 543 */ 544static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp) 545{ 546 unsigned int i; 547 548 for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) { 549 char phy_name[16]; 550 struct phy *phy; 551 552 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i); 553 phy = devm_phy_get(dp->dev, phy_name); 554 555 if (IS_ERR(phy)) { 556 switch (PTR_ERR(phy)) { 557 case -ENODEV: 558 if (dp->num_lanes) 559 return 0; 560 561 dev_err(dp->dev, "no PHY found\n"); 562 return -ENXIO; 563 564 case -EPROBE_DEFER: 565 return -EPROBE_DEFER; 566 567 default: 568 dev_err(dp->dev, "failed to get PHY lane %u\n", 569 i); 570 return PTR_ERR(phy); 571 } 572 } 573 574 dp->phy[i] = phy; 575 dp->num_lanes++; 576 } 577 578 return 0; 579} 580 581/** 582 * zynqmp_dp_phy_ready - Check if PHY is ready 583 * @dp: DisplayPort IP core structure 584 * 585 * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times. 586 * This amount of delay was suggested by IP designer. 587 * 588 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready. 589 */ 590static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp) 591{ 592 u32 i, reg, ready; 593 594 ready = (1 << dp->num_lanes) - 1; 595 596 /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */ 597 for (i = 0; ; i++) { 598 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS); 599 if ((reg & ready) == ready) 600 return 0; 601 602 if (i == 100) { 603 dev_err(dp->dev, "PHY isn't ready\n"); 604 return -ENODEV; 605 } 606 607 usleep_range(1000, 1100); 608 } 609 610 return 0; 611} 612 613/* ----------------------------------------------------------------------------- 614 * DisplayPort Link Training 615 */ 616 617/** 618 * zynqmp_dp_max_rate - Calculate and return available max pixel clock 619 * @link_rate: link rate (Kilo-bytes / sec) 620 * @lane_num: number of lanes 621 * @bpp: bits per pixel 622 * 623 * Return: max pixel clock (KHz) supported by current link config. 624 */ 625static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp) 626{ 627 return link_rate * lane_num * 8 / bpp; 628} 629 630/** 631 * zynqmp_dp_mode_configure - Configure the link values 632 * @dp: DisplayPort IP core structure 633 * @pclock: pixel clock for requested display mode 634 * @current_bw: current link rate 635 * 636 * Find the link configuration values, rate and lane count for requested pixel 637 * clock @pclock. The @pclock is stored in the mode to be used in other 638 * functions later. The returned rate is downshifted from the current rate 639 * @current_bw. 640 * 641 * Return: Current link rate code, or -EINVAL. 642 */ 643static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, 644 u8 current_bw) 645{ 646 int max_rate = dp->link_config.max_rate; 647 u8 bw_code; 648 u8 max_lanes = dp->link_config.max_lanes; 649 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate); 650 u8 bpp = dp->config.bpp; 651 u8 lane_cnt; 652 653 /* Downshift from current bandwidth */ 654 switch (current_bw) { 655 case DP_LINK_BW_5_4: 656 bw_code = DP_LINK_BW_2_7; 657 break; 658 case DP_LINK_BW_2_7: 659 bw_code = DP_LINK_BW_1_62; 660 break; 661 case DP_LINK_BW_1_62: 662 dev_err(dp->dev, "can't downshift. already lowest link rate\n"); 663 return -EINVAL; 664 default: 665 /* If not given, start with max supported */ 666 bw_code = max_link_rate_code; 667 break; 668 } 669 670 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { 671 int bw; 672 u32 rate; 673 674 bw = drm_dp_bw_code_to_link_rate(bw_code); 675 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp); 676 if (pclock <= rate) { 677 dp->mode.bw_code = bw_code; 678 dp->mode.lane_cnt = lane_cnt; 679 dp->mode.pclock = pclock; 680 return dp->mode.bw_code; 681 } 682 } 683 684 dev_err(dp->dev, "failed to configure link values\n"); 685 686 return -EINVAL; 687} 688 689/** 690 * zynqmp_dp_adjust_train - Adjust train values 691 * @dp: DisplayPort IP core structure 692 * @link_status: link status from sink which contains requested training values 693 */ 694static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, 695 u8 link_status[DP_LINK_STATUS_SIZE]) 696{ 697 u8 *train_set = dp->train_set; 698 u8 i; 699 700 for (i = 0; i < dp->mode.lane_cnt; i++) { 701 u8 voltage = drm_dp_get_adjust_request_voltage(link_status, i); 702 u8 preemphasis = 703 drm_dp_get_adjust_request_pre_emphasis(link_status, i); 704 705 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3) 706 voltage |= DP_TRAIN_MAX_SWING_REACHED; 707 708 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2) 709 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 710 711 train_set[i] = voltage | preemphasis; 712 } 713} 714 715/** 716 * zynqmp_dp_update_vs_emph - Update the training values 717 * @dp: DisplayPort IP core structure 718 * @train_set: A set of training values 719 * 720 * Update the training values based on the request from sink. The mapped values 721 * are predefined, and values(vs, pe, pc) are from the device manual. 722 * 723 * Return: 0 if vs and emph are updated successfully, or the error code returned 724 * by drm_dp_dpcd_write(). 725 */ 726static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set) 727{ 728 unsigned int i; 729 int ret; 730 731 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, 732 dp->mode.lane_cnt); 733 if (ret < 0) 734 return ret; 735 736 for (i = 0; i < dp->mode.lane_cnt; i++) { 737 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4; 738 union phy_configure_opts opts = { 0 }; 739 u8 train = train_set[i]; 740 741 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) 742 >> DP_TRAIN_VOLTAGE_SWING_SHIFT; 743 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) 744 >> DP_TRAIN_PRE_EMPHASIS_SHIFT; 745 746 phy_configure(dp->phy[i], &opts); 747 748 zynqmp_dp_write(dp, reg, 0x2); 749 } 750 751 return 0; 752} 753 754/** 755 * zynqmp_dp_link_train_cr - Train clock recovery 756 * @dp: DisplayPort IP core structure 757 * 758 * Return: 0 if clock recovery train is done successfully, or corresponding 759 * error code. 760 */ 761static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) 762{ 763 u8 link_status[DP_LINK_STATUS_SIZE]; 764 u8 lane_cnt = dp->mode.lane_cnt; 765 u8 vs = 0, tries = 0; 766 u16 max_tries, i; 767 bool cr_done; 768 int ret; 769 770 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 771 DP_TRAINING_PATTERN_1); 772 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 773 DP_TRAINING_PATTERN_1 | 774 DP_LINK_SCRAMBLING_DISABLE); 775 if (ret < 0) 776 return ret; 777 778 /* 779 * 256 loops should be maximum iterations for 4 lanes and 4 values. 780 * So, This loop should exit before 512 iterations 781 */ 782 for (max_tries = 0; max_tries < 512; max_tries++) { 783 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); 784 if (ret) 785 return ret; 786 787 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); 788 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 789 if (ret < 0) 790 return ret; 791 792 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt); 793 if (cr_done) 794 break; 795 796 for (i = 0; i < lane_cnt; i++) 797 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) 798 break; 799 if (i == lane_cnt) 800 break; 801 802 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) 803 tries++; 804 else 805 tries = 0; 806 807 if (tries == DP_MAX_TRAINING_TRIES) 808 break; 809 810 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 811 zynqmp_dp_adjust_train(dp, link_status); 812 } 813 814 if (!cr_done) 815 return -EIO; 816 817 return 0; 818} 819 820/** 821 * zynqmp_dp_link_train_ce - Train channel equalization 822 * @dp: DisplayPort IP core structure 823 * 824 * Return: 0 if channel equalization train is done successfully, or 825 * corresponding error code. 826 */ 827static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) 828{ 829 u8 link_status[DP_LINK_STATUS_SIZE]; 830 u8 lane_cnt = dp->mode.lane_cnt; 831 u32 pat, tries; 832 int ret; 833 bool ce_done; 834 835 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && 836 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) 837 pat = DP_TRAINING_PATTERN_3; 838 else 839 pat = DP_TRAINING_PATTERN_2; 840 841 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat); 842 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 843 pat | DP_LINK_SCRAMBLING_DISABLE); 844 if (ret < 0) 845 return ret; 846 847 for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) { 848 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set); 849 if (ret) 850 return ret; 851 852 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); 853 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); 854 if (ret < 0) 855 return ret; 856 857 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt); 858 if (ce_done) 859 break; 860 861 zynqmp_dp_adjust_train(dp, link_status); 862 } 863 864 if (!ce_done) 865 return -EIO; 866 867 return 0; 868} 869 870/** 871 * zynqmp_dp_setup() - Set up major link parameters 872 * @dp: DisplayPort IP core structure 873 * @bw_code: The link bandwidth as a multiple of 270 MHz 874 * @lane_cnt: The number of lanes to use 875 * @enhanced: Use enhanced framing 876 * @downspread: Enable spread-spectrum clocking 877 * 878 * Return: 0 on success, or -errno on failure 879 */ 880static int zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt, 881 bool enhanced, bool downspread) 882{ 883 u32 reg; 884 u8 aux_lane_cnt = lane_cnt; 885 int ret; 886 887 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt); 888 if (enhanced) { 889 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1); 890 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 891 } 892 893 if (downspread) { 894 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1); 895 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 896 DP_SPREAD_AMP_0_5); 897 } else { 898 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0); 899 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); 900 } 901 902 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); 903 if (ret < 0) { 904 dev_err(dp->dev, "failed to set lane count\n"); 905 return ret; 906 } 907 908 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 909 DP_SET_ANSI_8B10B); 910 if (ret < 0) { 911 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n"); 912 return ret; 913 } 914 915 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); 916 if (ret < 0) { 917 dev_err(dp->dev, "failed to set DP bandwidth\n"); 918 return ret; 919 } 920 921 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code); 922 switch (bw_code) { 923 case DP_LINK_BW_1_62: 924 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G; 925 break; 926 case DP_LINK_BW_2_7: 927 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G; 928 break; 929 case DP_LINK_BW_5_4: 930 default: 931 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G; 932 break; 933 } 934 935 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg); 936 return zynqmp_dp_phy_ready(dp); 937} 938 939/** 940 * zynqmp_dp_train - Train the link 941 * @dp: DisplayPort IP core structure 942 * 943 * Return: 0 if all trains are done successfully, or corresponding error code. 944 */ 945static int zynqmp_dp_train(struct zynqmp_dp *dp) 946{ 947 int ret; 948 949 ret = zynqmp_dp_setup(dp, dp->mode.bw_code, dp->mode.lane_cnt, 950 drm_dp_enhanced_frame_cap(dp->dpcd), 951 dp->dpcd[DP_MAX_DOWNSPREAD] & 952 DP_MAX_DOWNSPREAD_0_5); 953 if (ret) 954 return ret; 955 956 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1); 957 memset(dp->train_set, 0, sizeof(dp->train_set)); 958 ret = zynqmp_dp_link_train_cr(dp); 959 if (ret) 960 return ret; 961 962 ret = zynqmp_dp_link_train_ce(dp); 963 if (ret) 964 return ret; 965 966 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 967 DP_TRAINING_PATTERN_DISABLE); 968 if (ret < 0) { 969 dev_err(dp->dev, "failed to disable training pattern\n"); 970 return ret; 971 } 972 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, 973 DP_TRAINING_PATTERN_DISABLE); 974 975 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0); 976 977 return 0; 978} 979 980/** 981 * zynqmp_dp_train_loop - Downshift the link rate during training 982 * @dp: DisplayPort IP core structure 983 * 984 * Train the link by downshifting the link rate if training is not successful. 985 */ 986static void zynqmp_dp_train_loop(struct zynqmp_dp *dp) 987{ 988 struct zynqmp_dp_mode *mode = &dp->mode; 989 u8 bw = mode->bw_code; 990 int ret; 991 992 do { 993 if (dp->status == connector_status_disconnected || 994 !dp->enabled) 995 return; 996 997 ret = zynqmp_dp_train(dp); 998 if (!ret) 999 return; 1000 1001 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw); 1002 if (ret < 0) 1003 goto err_out; 1004 1005 bw = ret; 1006 } while (bw >= DP_LINK_BW_1_62); 1007 1008err_out: 1009 dev_err(dp->dev, "failed to train the DP link\n"); 1010} 1011 1012/* ----------------------------------------------------------------------------- 1013 * DisplayPort AUX 1014 */ 1015 1016#define AUX_READ_BIT 0x1 1017 1018/** 1019 * zynqmp_dp_aux_cmd_submit - Submit aux command 1020 * @dp: DisplayPort IP core structure 1021 * @cmd: aux command 1022 * @addr: aux address 1023 * @buf: buffer for command data 1024 * @bytes: number of bytes for @buf 1025 * @reply: reply code to be returned 1026 * 1027 * Submit an aux command. All aux related commands, native or i2c aux 1028 * read/write, are submitted through this function. The function is mapped to 1029 * the transfer function of struct drm_dp_aux. This function involves in 1030 * multiple register reads/writes, thus synchronization is needed, and it is 1031 * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep 1032 * if there's no immediate reply to the command submission. The reply code is 1033 * returned at @reply if @reply != NULL. 1034 * 1035 * Return: 0 if the command is submitted properly, or corresponding error code: 1036 * -EBUSY when there is any request already being processed 1037 * -ETIMEDOUT when receiving reply is timed out 1038 * -EIO when received bytes are less than requested 1039 */ 1040static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, 1041 u8 *buf, u8 bytes, u8 *reply) 1042{ 1043 bool is_read = (cmd & AUX_READ_BIT) ? true : false; 1044 unsigned long time_left; 1045 u32 reg, i; 1046 1047 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1048 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST) 1049 return -EBUSY; 1050 1051 reinit_completion(&dp->aux_done); 1052 1053 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr); 1054 if (!is_read) 1055 for (i = 0; i < bytes; i++) 1056 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO, 1057 buf[i]); 1058 1059 reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT; 1060 if (!buf || !bytes) 1061 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY; 1062 else 1063 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT; 1064 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg); 1065 1066 /* Wait for reply to be delivered upto 2ms */ 1067 time_left = wait_for_completion_timeout(&dp->aux_done, 1068 msecs_to_jiffies(2)); 1069 if (!time_left) 1070 return -ETIMEDOUT; 1071 1072 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1073 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT) 1074 return -ETIMEDOUT; 1075 1076 reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE); 1077 if (reply) 1078 *reply = reg; 1079 1080 if (is_read && 1081 (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK || 1082 reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) { 1083 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT); 1084 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes) 1085 return -EIO; 1086 1087 for (i = 0; i < bytes; i++) 1088 buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA); 1089 } 1090 1091 return 0; 1092} 1093 1094static ssize_t 1095zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1096{ 1097 struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux); 1098 int ret; 1099 unsigned int i, iter; 1100 1101 /* Number of loops = timeout in msec / aux delay (400 usec) */ 1102 iter = zynqmp_dp_aux_timeout_ms * 1000 / 400; 1103 iter = iter ? iter : 1; 1104 1105 for (i = 0; i < iter; i++) { 1106 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address, 1107 msg->buffer, msg->size, 1108 &msg->reply); 1109 if (!ret) { 1110 dev_vdbg(dp->dev, "aux %d retries\n", i); 1111 return msg->size; 1112 } 1113 1114 if (dp->status == connector_status_disconnected) { 1115 dev_dbg(dp->dev, "no connected aux device\n"); 1116 if (dp->ignore_aux_errors) 1117 goto fake_response; 1118 return -ENODEV; 1119 } 1120 1121 usleep_range(400, 500); 1122 } 1123 1124 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret); 1125 1126 if (!dp->ignore_aux_errors) 1127 return ret; 1128 1129fake_response: 1130 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 1131 memset(msg->buffer, 0, msg->size); 1132 return msg->size; 1133} 1134 1135/** 1136 * zynqmp_dp_aux_init - Initialize and register the DP AUX 1137 * @dp: DisplayPort IP core structure 1138 * 1139 * Program the AUX clock divider and filter and register the DP AUX adapter. 1140 * 1141 * Return: 0 on success, error value otherwise 1142 */ 1143static int zynqmp_dp_aux_init(struct zynqmp_dp *dp) 1144{ 1145 unsigned long rate; 1146 unsigned int w; 1147 1148 /* 1149 * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles 1150 * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32, 1151 * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs, 1152 * compute the w / 8 value corresponding to 0.4µs rounded up, and make 1153 * sure it stays below 0.6µs and within the allowable values. 1154 */ 1155 rate = clk_get_rate(dp->dpsub->apb_clk); 1156 w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8; 1157 if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) { 1158 dev_err(dp->dev, "aclk frequency too high\n"); 1159 return -EINVAL; 1160 } 1161 1162 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER, 1163 (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) | 1164 (rate / (1000 * 1000))); 1165 1166 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_REPLY_RECEIVED | 1167 ZYNQMP_DP_INT_REPLY_TIMEOUT); 1168 1169 dp->aux.name = "ZynqMP DP AUX"; 1170 dp->aux.dev = dp->dev; 1171 dp->aux.drm_dev = dp->bridge.dev; 1172 dp->aux.transfer = zynqmp_dp_aux_transfer; 1173 1174 return drm_dp_aux_register(&dp->aux); 1175} 1176 1177/** 1178 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX 1179 * @dp: DisplayPort IP core structure 1180 * 1181 * Unregister the DP AUX adapter. 1182 */ 1183static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp) 1184{ 1185 drm_dp_aux_unregister(&dp->aux); 1186 1187 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_REPLY_RECEIVED | 1188 ZYNQMP_DP_INT_REPLY_TIMEOUT); 1189} 1190 1191/* ----------------------------------------------------------------------------- 1192 * DisplayPort Generic Support 1193 */ 1194 1195/** 1196 * zynqmp_dp_update_misc - Write the misc registers 1197 * @dp: DisplayPort IP core structure 1198 * 1199 * The misc register values are stored in the structure, and this 1200 * function applies the values into the registers. 1201 */ 1202static void zynqmp_dp_update_misc(struct zynqmp_dp *dp) 1203{ 1204 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0); 1205 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1); 1206} 1207 1208/** 1209 * zynqmp_dp_set_format - Set the input format 1210 * @dp: DisplayPort IP core structure 1211 * @info: Display info 1212 * @format: input format 1213 * @bpc: bits per component 1214 * 1215 * Update misc register values based on input @format and @bpc. 1216 * 1217 * Return: 0 on success, or -EINVAL. 1218 */ 1219static int zynqmp_dp_set_format(struct zynqmp_dp *dp, 1220 const struct drm_display_info *info, 1221 enum zynqmp_dpsub_format format, 1222 unsigned int bpc) 1223{ 1224 struct zynqmp_dp_config *config = &dp->config; 1225 unsigned int num_colors; 1226 1227 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK; 1228 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1229 1230 switch (format) { 1231 case ZYNQMP_DPSUB_FORMAT_RGB: 1232 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB; 1233 num_colors = 3; 1234 break; 1235 1236 case ZYNQMP_DPSUB_FORMAT_YCRCB444: 1237 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444; 1238 num_colors = 3; 1239 break; 1240 1241 case ZYNQMP_DPSUB_FORMAT_YCRCB422: 1242 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422; 1243 num_colors = 2; 1244 break; 1245 1246 case ZYNQMP_DPSUB_FORMAT_YONLY: 1247 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; 1248 num_colors = 1; 1249 break; 1250 1251 default: 1252 dev_err(dp->dev, "Invalid colormetry in DT\n"); 1253 return -EINVAL; 1254 } 1255 1256 if (info && info->bpc && bpc > info->bpc) { 1257 dev_warn(dp->dev, 1258 "downgrading requested %ubpc to display limit %ubpc\n", 1259 bpc, info->bpc); 1260 bpc = info->bpc; 1261 } 1262 1263 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK; 1264 1265 switch (bpc) { 1266 case 6: 1267 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6; 1268 break; 1269 case 8: 1270 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1271 break; 1272 case 10: 1273 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10; 1274 break; 1275 case 12: 1276 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12; 1277 break; 1278 case 16: 1279 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16; 1280 break; 1281 default: 1282 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n", 1283 bpc); 1284 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; 1285 bpc = 8; 1286 break; 1287 } 1288 1289 /* Update the current bpp based on the format. */ 1290 config->bpp = bpc * num_colors; 1291 1292 return 0; 1293} 1294 1295/** 1296 * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values 1297 * @dp: DisplayPort IP core structure 1298 * @mode: requested display mode 1299 * 1300 * Set the transfer unit, and calculate all transfer unit size related values. 1301 * Calculation is based on DP and IP core specification. 1302 */ 1303static void 1304zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, 1305 const struct drm_display_mode *mode) 1306{ 1307 u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF; 1308 u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait; 1309 1310 /* Use the max transfer unit size (default) */ 1311 zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu); 1312 1313 vid_kbytes = mode->clock * (dp->config.bpp / 8); 1314 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1315 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000); 1316 zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU, 1317 avg_bytes_per_tu / 1000); 1318 zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU, 1319 avg_bytes_per_tu % 1000); 1320 1321 /* Configure the initial wait cycle based on transfer unit size */ 1322 if (tu < (avg_bytes_per_tu / 1000)) 1323 init_wait = 0; 1324 else if ((avg_bytes_per_tu / 1000) <= 4) 1325 init_wait = tu; 1326 else 1327 init_wait = tu - avg_bytes_per_tu / 1000; 1328 1329 zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait); 1330} 1331 1332/** 1333 * zynqmp_dp_encoder_mode_set_stream - Configure the main stream 1334 * @dp: DisplayPort IP core structure 1335 * @mode: requested display mode 1336 * 1337 * Configure the main stream based on the requested mode @mode. Calculation is 1338 * based on IP core specification. 1339 */ 1340static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, 1341 const struct drm_display_mode *mode) 1342{ 1343 u8 lane_cnt = dp->mode.lane_cnt; 1344 u32 reg, wpl; 1345 1346 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal); 1347 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal); 1348 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY, 1349 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) << 1350 ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) | 1351 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) << 1352 ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT)); 1353 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH, 1354 mode->hsync_end - mode->hsync_start); 1355 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH, 1356 mode->vsync_end - mode->vsync_start); 1357 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay); 1358 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay); 1359 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART, 1360 mode->htotal - mode->hsync_start); 1361 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART, 1362 mode->vtotal - mode->vsync_start); 1363 1364 /* In synchronous mode, set the dividers */ 1365 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) { 1366 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1367 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg); 1368 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock); 1369 } 1370 1371 zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1); 1372 1373 /* Translate to the native 16 bit datapath based on IP core spec */ 1374 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16; 1375 reg = wpl + wpl % lane_cnt - lane_cnt; 1376 zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg); 1377} 1378 1379/* ----------------------------------------------------------------------------- 1380 * Audio 1381 */ 1382 1383void zynqmp_dp_audio_set_channels(struct zynqmp_dp *dp, 1384 unsigned int num_channels) 1385{ 1386 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, num_channels - 1); 1387} 1388 1389void zynqmp_dp_audio_enable(struct zynqmp_dp *dp) 1390{ 1391 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1); 1392} 1393 1394void zynqmp_dp_audio_disable(struct zynqmp_dp *dp) 1395{ 1396 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0); 1397} 1398 1399void zynqmp_dp_audio_write_n_m(struct zynqmp_dp *dp) 1400{ 1401 unsigned int rate; 1402 u32 link_rate; 1403 1404 if (!(dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK)) 1405 return; 1406 1407 link_rate = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); 1408 1409 rate = clk_get_rate(dp->dpsub->aud_clk); 1410 1411 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512); 1412 1413 zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, link_rate); 1414 zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000); 1415} 1416 1417/* ----------------------------------------------------------------------------- 1418 * DISP Configuration 1419 */ 1420 1421/** 1422 * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer 1423 * @dp: DisplayPort IP core structure 1424 * 1425 * Return: The first connected live display layer or NULL if none of the live 1426 * layers are connected. 1427 */ 1428static struct zynqmp_disp_layer * 1429zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp) 1430{ 1431 if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) 1432 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID]; 1433 else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX)) 1434 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]; 1435 else 1436 return NULL; 1437} 1438 1439static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, 1440 struct drm_atomic_state *state) 1441{ 1442 struct zynqmp_disp_layer *layer; 1443 struct drm_bridge_state *bridge_state; 1444 u32 bus_fmt; 1445 1446 layer = zynqmp_dp_disp_connected_live_layer(dp); 1447 if (!layer) 1448 return; 1449 1450 bridge_state = drm_atomic_get_new_bridge_state(state, &dp->bridge); 1451 if (WARN_ON(!bridge_state)) 1452 return; 1453 1454 bus_fmt = bridge_state->input_bus_cfg.format; 1455 zynqmp_disp_layer_set_live_format(layer, bus_fmt); 1456 zynqmp_disp_layer_enable(layer); 1457 1458 if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX]) 1459 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255); 1460 else 1461 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0); 1462 1463 zynqmp_disp_enable(dp->dpsub->disp); 1464} 1465 1466static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp, 1467 struct drm_bridge_state *old_bridge_state) 1468{ 1469 struct zynqmp_disp_layer *layer; 1470 1471 layer = zynqmp_dp_disp_connected_live_layer(dp); 1472 if (!layer) 1473 return; 1474 1475 zynqmp_disp_disable(dp->dpsub->disp); 1476 zynqmp_disp_layer_disable(layer); 1477} 1478 1479/* ----------------------------------------------------------------------------- 1480 * DRM Bridge 1481 */ 1482 1483static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge, 1484 struct drm_encoder *encoder, 1485 enum drm_bridge_attach_flags flags) 1486{ 1487 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1488 int ret; 1489 1490 /* Initialize and register the AUX adapter. */ 1491 ret = zynqmp_dp_aux_init(dp); 1492 if (ret) { 1493 dev_err(dp->dev, "failed to initialize DP aux\n"); 1494 return ret; 1495 } 1496 1497 if (dp->next_bridge) { 1498 ret = drm_bridge_attach(encoder, dp->next_bridge, 1499 bridge, flags); 1500 if (ret < 0) 1501 goto error; 1502 } 1503 1504 /* Now that initialisation is complete, enable interrupts. */ 1505 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL); 1506 1507 return 0; 1508 1509error: 1510 zynqmp_dp_aux_cleanup(dp); 1511 return ret; 1512} 1513 1514static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge) 1515{ 1516 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1517 1518 zynqmp_dp_aux_cleanup(dp); 1519} 1520 1521static enum drm_mode_status 1522zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge, 1523 const struct drm_display_info *info, 1524 const struct drm_display_mode *mode) 1525{ 1526 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1527 int rate; 1528 1529 if (mode->clock > ZYNQMP_MAX_FREQ) { 1530 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1531 mode->name); 1532 drm_mode_debug_printmodeline(mode); 1533 return MODE_CLOCK_HIGH; 1534 } 1535 1536 /* Check with link rate and lane count */ 1537 scoped_guard(mutex, &dp->lock) 1538 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1539 dp->link_config.max_lanes, 1540 dp->config.bpp); 1541 if (mode->clock > rate) { 1542 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n", 1543 mode->name); 1544 drm_mode_debug_printmodeline(mode); 1545 return MODE_CLOCK_HIGH; 1546 } 1547 1548 return MODE_OK; 1549} 1550 1551static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge, 1552 struct drm_atomic_state *state) 1553{ 1554 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1555 const struct drm_crtc_state *crtc_state; 1556 const struct drm_display_mode *adjusted_mode; 1557 const struct drm_display_mode *mode; 1558 struct drm_connector *connector; 1559 struct drm_crtc *crtc; 1560 unsigned int i; 1561 int rate; 1562 int ret; 1563 1564 pm_runtime_get_sync(dp->dev); 1565 1566 guard(mutex)(&dp->lock); 1567 zynqmp_dp_disp_enable(dp, state); 1568 1569 /* 1570 * Retrieve the CRTC mode and adjusted mode. This requires a little 1571 * dance to go from the bridge to the encoder, to the connector and to 1572 * the CRTC. 1573 */ 1574 connector = drm_atomic_get_new_connector_for_encoder(state, 1575 bridge->encoder); 1576 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 1577 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1578 adjusted_mode = &crtc_state->adjusted_mode; 1579 mode = &crtc_state->mode; 1580 1581 zynqmp_dp_set_format(dp, &connector->display_info, 1582 ZYNQMP_DPSUB_FORMAT_RGB, 8); 1583 1584 /* Check again as bpp or format might have been changed */ 1585 rate = zynqmp_dp_max_rate(dp->link_config.max_rate, 1586 dp->link_config.max_lanes, dp->config.bpp); 1587 if (mode->clock > rate) { 1588 dev_err(dp->dev, "mode %s has too high pixel rate\n", 1589 mode->name); 1590 drm_mode_debug_printmodeline(mode); 1591 } 1592 1593 /* Configure the mode */ 1594 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0); 1595 if (ret < 0) { 1596 pm_runtime_put_sync(dp->dev); 1597 return; 1598 } 1599 1600 zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode); 1601 zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode); 1602 1603 /* Enable the encoder */ 1604 dp->enabled = true; 1605 zynqmp_dp_update_misc(dp); 1606 1607 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0); 1608 if (dp->status == connector_status_connected) { 1609 for (i = 0; i < 3; i++) { 1610 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, 1611 DP_SET_POWER_D0); 1612 if (ret == 1) 1613 break; 1614 usleep_range(300, 500); 1615 } 1616 /* Some monitors take time to wake up properly */ 1617 msleep(zynqmp_dp_power_on_delay_ms); 1618 } 1619 if (ret != 1) 1620 dev_dbg(dp->dev, "DP aux failed\n"); 1621 else 1622 zynqmp_dp_train_loop(dp); 1623 zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET, 1624 ZYNQMP_DP_SOFTWARE_RESET_ALL); 1625 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1); 1626} 1627 1628static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge, 1629 struct drm_atomic_state *state) 1630{ 1631 struct drm_bridge_state *old_bridge_state = drm_atomic_get_old_bridge_state(state, 1632 bridge); 1633 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1634 1635 mutex_lock(&dp->lock); 1636 dp->enabled = false; 1637 cancel_work(&dp->hpd_work); 1638 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0); 1639 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); 1640 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 1641 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 1642 1643 zynqmp_dp_disp_disable(dp, old_bridge_state); 1644 mutex_unlock(&dp->lock); 1645 1646 pm_runtime_put_sync(dp->dev); 1647} 1648 1649#define ZYNQMP_DP_MIN_H_BACKPORCH 20 1650 1651static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge, 1652 struct drm_bridge_state *bridge_state, 1653 struct drm_crtc_state *crtc_state, 1654 struct drm_connector_state *conn_state) 1655{ 1656 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1657 struct drm_display_mode *mode = &crtc_state->mode; 1658 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1659 int diff = mode->htotal - mode->hsync_end; 1660 1661 /* 1662 * ZynqMP DP requires horizontal backporch to be greater than 12. 1663 * This limitation may not be compatible with the sink device. 1664 */ 1665 if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) { 1666 int vrefresh = (adjusted_mode->clock * 1000) / 1667 (adjusted_mode->vtotal * adjusted_mode->htotal); 1668 1669 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d", 1670 diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff); 1671 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff; 1672 adjusted_mode->htotal += diff; 1673 adjusted_mode->clock = adjusted_mode->vtotal * 1674 adjusted_mode->htotal * vrefresh / 1000; 1675 } 1676 1677 return 0; 1678} 1679 1680static enum drm_connector_status __zynqmp_dp_bridge_detect(struct zynqmp_dp *dp) 1681{ 1682 struct zynqmp_dp_link_config *link_config = &dp->link_config; 1683 u32 state, i; 1684 int ret; 1685 1686 lockdep_assert_held(&dp->lock); 1687 1688 /* 1689 * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to 1690 * get the HPD signal with some monitors. 1691 */ 1692 for (i = 0; i < 10; i++) { 1693 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); 1694 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) 1695 break; 1696 msleep(100); 1697 } 1698 1699 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) { 1700 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, 1701 sizeof(dp->dpcd)); 1702 if (ret < 0) { 1703 dev_dbg(dp->dev, "DPCD read failed"); 1704 goto disconnected; 1705 } 1706 1707 link_config->max_rate = min_t(int, 1708 drm_dp_max_link_rate(dp->dpcd), 1709 DP_HIGH_BIT_RATE2); 1710 link_config->max_lanes = min_t(u8, 1711 drm_dp_max_lane_count(dp->dpcd), 1712 dp->num_lanes); 1713 1714 dp->status = connector_status_connected; 1715 return connector_status_connected; 1716 } 1717 1718disconnected: 1719 dp->status = connector_status_disconnected; 1720 return connector_status_disconnected; 1721} 1722 1723static enum drm_connector_status 1724zynqmp_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1725{ 1726 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1727 1728 guard(mutex)(&dp->lock); 1729 return __zynqmp_dp_bridge_detect(dp); 1730} 1731 1732static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge, 1733 struct drm_connector *connector) 1734{ 1735 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1736 1737 return drm_edid_read_ddc(connector, &dp->aux.ddc); 1738} 1739 1740static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts) 1741{ 1742 u32 *formats = kzalloc(sizeof(*formats), GFP_KERNEL); 1743 1744 if (formats) 1745 *formats = MEDIA_BUS_FMT_FIXED; 1746 *num_input_fmts = !!formats; 1747 1748 return formats; 1749} 1750 1751static u32 * 1752zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge, 1753 struct drm_bridge_state *bridge_state, 1754 struct drm_crtc_state *crtc_state, 1755 struct drm_connector_state *conn_state, 1756 u32 output_fmt, 1757 unsigned int *num_input_fmts) 1758{ 1759 struct zynqmp_dp *dp = bridge_to_dp(bridge); 1760 struct zynqmp_disp_layer *layer; 1761 1762 layer = zynqmp_dp_disp_connected_live_layer(dp); 1763 if (layer) 1764 return zynqmp_disp_live_layer_formats(layer, num_input_fmts); 1765 else 1766 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts); 1767} 1768 1769/* ----------------------------------------------------------------------------- 1770 * debugfs 1771 */ 1772 1773/** 1774 * zynqmp_dp_set_test_pattern() - Configure the link for a test pattern 1775 * @dp: DisplayPort IP core structure 1776 * @pattern: The test pattern to configure 1777 * @custom: The custom pattern to use if @pattern is %TEST_80BIT_CUSTOM 1778 * 1779 * Return: 0 on success, or negative errno on (DPCD) failure 1780 */ 1781static int zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp, 1782 enum test_pattern pattern, 1783 u8 *const custom) 1784{ 1785 bool scramble = false; 1786 u32 train_pattern = 0; 1787 u32 link_pattern = 0; 1788 u8 dpcd_train = 0; 1789 u8 dpcd_link = 0; 1790 int ret; 1791 1792 switch (pattern) { 1793 case TEST_TPS1: 1794 train_pattern = 1; 1795 break; 1796 case TEST_TPS2: 1797 train_pattern = 2; 1798 break; 1799 case TEST_TPS3: 1800 train_pattern = 3; 1801 break; 1802 case TEST_SYMBOL_ERROR: 1803 scramble = true; 1804 link_pattern = DP_PHY_TEST_PATTERN_ERROR_COUNT; 1805 break; 1806 case TEST_PRBS7: 1807 /* We use a dedicated register to enable PRBS7 */ 1808 dpcd_link = DP_LINK_QUAL_PATTERN_ERROR_RATE; 1809 break; 1810 case TEST_80BIT_CUSTOM: { 1811 const u8 *p = custom; 1812 1813 link_pattern = DP_LINK_QUAL_PATTERN_80BIT_CUSTOM; 1814 1815 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_1, 1816 (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); 1817 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_2, 1818 (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]); 1819 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_3, 1820 (p[9] << 8) | p[8]); 1821 break; 1822 } 1823 case TEST_CP2520: 1824 link_pattern = DP_LINK_QUAL_PATTERN_CP2520_PAT_1; 1825 break; 1826 default: 1827 WARN_ON_ONCE(1); 1828 fallthrough; 1829 case TEST_VIDEO: 1830 scramble = true; 1831 } 1832 1833 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, !scramble); 1834 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, train_pattern); 1835 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_QUAL_PATTERN_SET, link_pattern); 1836 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMIT_PRBS7, pattern == TEST_PRBS7); 1837 1838 dpcd_link = dpcd_link ?: link_pattern; 1839 dpcd_train = train_pattern; 1840 if (!scramble) 1841 dpcd_train |= DP_LINK_SCRAMBLING_DISABLE; 1842 1843 if (dp->dpcd[DP_DPCD_REV] < 0x12) { 1844 if (pattern == TEST_CP2520) 1845 dev_warn(dp->dev, 1846 "can't set sink link quality pattern to CP2520 for DPCD < r1.2; error counters will be invalid\n"); 1847 else 1848 dpcd_train |= FIELD_PREP(DP_LINK_QUAL_PATTERN_11_MASK, 1849 dpcd_link); 1850 } else { 1851 u8 dpcd_link_lane[ZYNQMP_DP_MAX_LANES]; 1852 1853 memset(dpcd_link_lane, dpcd_link, ZYNQMP_DP_MAX_LANES); 1854 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_QUAL_LANE0_SET, 1855 dpcd_link_lane, ZYNQMP_DP_MAX_LANES); 1856 if (ret < 0) 1857 return ret; 1858 } 1859 1860 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, dpcd_train); 1861 return ret < 0 ? ret : 0; 1862} 1863 1864static int zynqmp_dp_test_setup(struct zynqmp_dp *dp) 1865{ 1866 return zynqmp_dp_setup(dp, dp->test.bw_code, dp->test.link_cnt, 1867 dp->test.enhanced, dp->test.downspread); 1868} 1869 1870static ssize_t zynqmp_dp_pattern_read(struct file *file, char __user *user_buf, 1871 size_t count, loff_t *ppos) 1872{ 1873 struct zynqmp_dp *dp = file->private_data; 1874 char buf[16]; 1875 ssize_t ret; 1876 1877 scoped_guard(mutex, &dp->lock) 1878 ret = snprintf(buf, sizeof(buf), "%s\n", 1879 test_pattern_str[dp->test.pattern]); 1880 1881 return simple_read_from_buffer(user_buf, count, ppos, buf, ret); 1882} 1883 1884static ssize_t zynqmp_dp_pattern_write(struct file *file, 1885 const char __user *user_buf, 1886 size_t count, loff_t *ppos) 1887{ 1888 struct zynqmp_dp *dp = file->private_data; 1889 char buf[16]; 1890 ssize_t ret; 1891 int pattern; 1892 1893 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, 1894 count); 1895 if (ret < 0) 1896 return ret; 1897 buf[ret] = '\0'; 1898 1899 pattern = sysfs_match_string(test_pattern_str, buf); 1900 if (pattern < 0) 1901 return -EINVAL; 1902 1903 mutex_lock(&dp->lock); 1904 dp->test.pattern = pattern; 1905 if (dp->test.active) 1906 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 1907 dp->test.custom) ?: ret; 1908 mutex_unlock(&dp->lock); 1909 1910 return ret; 1911} 1912 1913static const struct file_operations fops_zynqmp_dp_pattern = { 1914 .read = zynqmp_dp_pattern_read, 1915 .write = zynqmp_dp_pattern_write, 1916 .open = simple_open, 1917 .llseek = noop_llseek, 1918}; 1919 1920static int zynqmp_dp_enhanced_get(void *data, u64 *val) 1921{ 1922 struct zynqmp_dp *dp = data; 1923 1924 guard(mutex)(&dp->lock); 1925 *val = dp->test.enhanced; 1926 return 0; 1927} 1928 1929static int zynqmp_dp_enhanced_set(void *data, u64 val) 1930{ 1931 struct zynqmp_dp *dp = data; 1932 1933 guard(mutex)(&dp->lock); 1934 dp->test.enhanced = val; 1935 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 1936} 1937 1938DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_enhanced, zynqmp_dp_enhanced_get, 1939 zynqmp_dp_enhanced_set, "%llu\n"); 1940 1941static int zynqmp_dp_downspread_get(void *data, u64 *val) 1942{ 1943 struct zynqmp_dp *dp = data; 1944 1945 guard(mutex)(&dp->lock); 1946 *val = dp->test.downspread; 1947 return 0; 1948} 1949 1950static int zynqmp_dp_downspread_set(void *data, u64 val) 1951{ 1952 struct zynqmp_dp *dp = data; 1953 1954 guard(mutex)(&dp->lock); 1955 dp->test.downspread = val; 1956 1957 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 1958} 1959 1960DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_downspread, zynqmp_dp_downspread_get, 1961 zynqmp_dp_downspread_set, "%llu\n"); 1962 1963static int zynqmp_dp_active_get(void *data, u64 *val) 1964{ 1965 struct zynqmp_dp *dp = data; 1966 1967 guard(mutex)(&dp->lock); 1968 *val = dp->test.active; 1969 return 0; 1970} 1971 1972static int zynqmp_dp_active_set(void *data, u64 val) 1973{ 1974 struct zynqmp_dp *dp = data; 1975 int ret; 1976 1977 guard(mutex)(&dp->lock); 1978 if (val) { 1979 if (val < 2) { 1980 ret = zynqmp_dp_test_setup(dp); 1981 if (ret) 1982 return ret; 1983 } 1984 1985 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 1986 dp->test.custom); 1987 if (ret) 1988 return ret; 1989 1990 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 1991 if (ret) 1992 return ret; 1993 1994 dp->test.active = true; 1995 } else { 1996 int err; 1997 1998 dp->test.active = false; 1999 err = zynqmp_dp_set_test_pattern(dp, TEST_VIDEO, NULL); 2000 if (err) 2001 dev_warn(dp->dev, "could not clear test pattern: %d\n", 2002 err); 2003 zynqmp_dp_train_loop(dp); 2004 } 2005 2006 return 0; 2007} 2008 2009DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_active, zynqmp_dp_active_get, 2010 zynqmp_dp_active_set, "%llu\n"); 2011 2012static ssize_t zynqmp_dp_custom_read(struct file *file, char __user *user_buf, 2013 size_t count, loff_t *ppos) 2014{ 2015 struct zynqmp_dp *dp = file->private_data; 2016 ssize_t ret; 2017 2018 mutex_lock(&dp->lock); 2019 ret = simple_read_from_buffer(user_buf, count, ppos, &dp->test.custom, 2020 sizeof(dp->test.custom)); 2021 mutex_unlock(&dp->lock); 2022 return ret; 2023} 2024 2025static ssize_t zynqmp_dp_custom_write(struct file *file, 2026 const char __user *user_buf, 2027 size_t count, loff_t *ppos) 2028{ 2029 struct zynqmp_dp *dp = file->private_data; 2030 ssize_t ret; 2031 char buf[sizeof(dp->test.custom)]; 2032 2033 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 2034 if (ret < 0) 2035 return ret; 2036 2037 mutex_lock(&dp->lock); 2038 memcpy(dp->test.custom, buf, ret); 2039 if (dp->test.active) 2040 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern, 2041 dp->test.custom) ?: ret; 2042 mutex_unlock(&dp->lock); 2043 return ret; 2044} 2045 2046static const struct file_operations fops_zynqmp_dp_custom = { 2047 .read = zynqmp_dp_custom_read, 2048 .write = zynqmp_dp_custom_write, 2049 .open = simple_open, 2050 .llseek = noop_llseek, 2051}; 2052 2053static int zynqmp_dp_swing_get(void *data, u64 *val) 2054{ 2055 struct zynqmp_dp_train_set_priv *priv = data; 2056 struct zynqmp_dp *dp = priv->dp; 2057 2058 guard(mutex)(&dp->lock); 2059 *val = dp->test.train_set[priv->lane] & DP_TRAIN_VOLTAGE_SWING_MASK; 2060 return 0; 2061} 2062 2063static int zynqmp_dp_swing_set(void *data, u64 val) 2064{ 2065 struct zynqmp_dp_train_set_priv *priv = data; 2066 struct zynqmp_dp *dp = priv->dp; 2067 u8 *train_set = &dp->test.train_set[priv->lane]; 2068 2069 if (val > 3) 2070 return -EINVAL; 2071 2072 guard(mutex)(&dp->lock); 2073 *train_set &= ~(DP_TRAIN_MAX_SWING_REACHED | 2074 DP_TRAIN_VOLTAGE_SWING_MASK); 2075 *train_set |= val; 2076 if (val == 3) 2077 *train_set |= DP_TRAIN_MAX_SWING_REACHED; 2078 2079 if (dp->test.active) 2080 return zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 2081 2082 return 0; 2083} 2084 2085DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_swing, zynqmp_dp_swing_get, 2086 zynqmp_dp_swing_set, "%llu\n"); 2087 2088static int zynqmp_dp_preemphasis_get(void *data, u64 *val) 2089{ 2090 struct zynqmp_dp_train_set_priv *priv = data; 2091 struct zynqmp_dp *dp = priv->dp; 2092 2093 guard(mutex)(&dp->lock); 2094 *val = FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK, 2095 dp->test.train_set[priv->lane]); 2096 return 0; 2097} 2098 2099static int zynqmp_dp_preemphasis_set(void *data, u64 val) 2100{ 2101 struct zynqmp_dp_train_set_priv *priv = data; 2102 struct zynqmp_dp *dp = priv->dp; 2103 u8 *train_set = &dp->test.train_set[priv->lane]; 2104 2105 if (val > 2) 2106 return -EINVAL; 2107 2108 guard(mutex)(&dp->lock); 2109 *train_set &= ~(DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | 2110 DP_TRAIN_PRE_EMPHASIS_MASK); 2111 *train_set |= val; 2112 if (val == 2) 2113 *train_set |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2114 2115 if (dp->test.active) 2116 return zynqmp_dp_update_vs_emph(dp, dp->test.train_set); 2117 2118 return 0; 2119} 2120 2121DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_preemphasis, zynqmp_dp_preemphasis_get, 2122 zynqmp_dp_preemphasis_set, "%llu\n"); 2123 2124static int zynqmp_dp_lanes_get(void *data, u64 *val) 2125{ 2126 struct zynqmp_dp *dp = data; 2127 2128 guard(mutex)(&dp->lock); 2129 *val = dp->test.link_cnt; 2130 return 0; 2131} 2132 2133static int zynqmp_dp_lanes_set(void *data, u64 val) 2134{ 2135 struct zynqmp_dp *dp = data; 2136 2137 if (val > ZYNQMP_DP_MAX_LANES) 2138 return -EINVAL; 2139 2140 guard(mutex)(&dp->lock); 2141 if (val > dp->num_lanes) 2142 return -EINVAL; 2143 2144 dp->test.link_cnt = val; 2145 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 2146} 2147 2148DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_lanes, zynqmp_dp_lanes_get, 2149 zynqmp_dp_lanes_set, "%llu\n"); 2150 2151static int zynqmp_dp_rate_get(void *data, u64 *val) 2152{ 2153 struct zynqmp_dp *dp = data; 2154 2155 guard(mutex)(&dp->lock); 2156 *val = drm_dp_bw_code_to_link_rate(dp->test.bw_code) * 10000ULL; 2157 return 0; 2158} 2159 2160static int zynqmp_dp_rate_set(void *data, u64 val) 2161{ 2162 struct zynqmp_dp *dp = data; 2163 int link_rate; 2164 u8 bw_code; 2165 2166 if (do_div(val, 10000)) 2167 return -EINVAL; 2168 2169 bw_code = drm_dp_link_rate_to_bw_code(val); 2170 link_rate = drm_dp_bw_code_to_link_rate(bw_code); 2171 if (val != link_rate) 2172 return -EINVAL; 2173 2174 if (bw_code != DP_LINK_BW_1_62 && bw_code != DP_LINK_BW_2_7 && 2175 bw_code != DP_LINK_BW_5_4) 2176 return -EINVAL; 2177 2178 guard(mutex)(&dp->lock); 2179 dp->test.bw_code = bw_code; 2180 return dp->test.active ? zynqmp_dp_test_setup(dp) : 0; 2181} 2182 2183DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_rate, zynqmp_dp_rate_get, 2184 zynqmp_dp_rate_set, "%llu\n"); 2185 2186static int zynqmp_dp_ignore_aux_errors_get(void *data, u64 *val) 2187{ 2188 struct zynqmp_dp *dp = data; 2189 2190 guard(mutex)(&dp->lock); 2191 *val = dp->ignore_aux_errors; 2192 return 0; 2193} 2194 2195static int zynqmp_dp_ignore_aux_errors_set(void *data, u64 val) 2196{ 2197 struct zynqmp_dp *dp = data; 2198 2199 if (val != !!val) 2200 return -EINVAL; 2201 2202 guard(mutex)(&dp->lock); 2203 dp->ignore_aux_errors = val; 2204 return 0; 2205} 2206 2207DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_aux_errors, 2208 zynqmp_dp_ignore_aux_errors_get, 2209 zynqmp_dp_ignore_aux_errors_set, "%llu\n"); 2210 2211static int zynqmp_dp_ignore_hpd_get(void *data, u64 *val) 2212{ 2213 struct zynqmp_dp *dp = data; 2214 2215 guard(mutex)(&dp->lock); 2216 *val = dp->ignore_hpd; 2217 return 0; 2218} 2219 2220static int zynqmp_dp_ignore_hpd_set(void *data, u64 val) 2221{ 2222 struct zynqmp_dp *dp = data; 2223 2224 if (val != !!val) 2225 return -EINVAL; 2226 2227 guard(mutex)(&dp->lock); 2228 dp->ignore_hpd = val; 2229 return 0; 2230} 2231 2232DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_hpd, zynqmp_dp_ignore_hpd_get, 2233 zynqmp_dp_ignore_hpd_set, "%llu\n"); 2234 2235static void zynqmp_dp_bridge_debugfs_init(struct drm_bridge *bridge, 2236 struct dentry *root) 2237{ 2238 struct zynqmp_dp *dp = bridge_to_dp(bridge); 2239 struct dentry *test; 2240 int i; 2241 2242 dp->test.bw_code = DP_LINK_BW_5_4; 2243 dp->test.link_cnt = dp->num_lanes; 2244 2245 test = debugfs_create_dir("test", root); 2246#define CREATE_FILE(name) \ 2247 debugfs_create_file(#name, 0600, test, dp, &fops_zynqmp_dp_##name) 2248 CREATE_FILE(pattern); 2249 CREATE_FILE(enhanced); 2250 CREATE_FILE(downspread); 2251 CREATE_FILE(active); 2252 CREATE_FILE(custom); 2253 CREATE_FILE(rate); 2254 CREATE_FILE(lanes); 2255 CREATE_FILE(ignore_aux_errors); 2256 CREATE_FILE(ignore_hpd); 2257 2258 for (i = 0; i < dp->num_lanes; i++) { 2259 static const char fmt[] = "lane%d_preemphasis"; 2260 char name[sizeof(fmt)]; 2261 2262 dp->debugfs_train_set[i].dp = dp; 2263 dp->debugfs_train_set[i].lane = i; 2264 2265 snprintf(name, sizeof(name), fmt, i); 2266 debugfs_create_file(name, 0600, test, 2267 &dp->debugfs_train_set[i], 2268 &fops_zynqmp_dp_preemphasis); 2269 2270 snprintf(name, sizeof(name), "lane%d_swing", i); 2271 debugfs_create_file(name, 0600, test, 2272 &dp->debugfs_train_set[i], 2273 &fops_zynqmp_dp_swing); 2274 } 2275} 2276 2277static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = { 2278 .attach = zynqmp_dp_bridge_attach, 2279 .detach = zynqmp_dp_bridge_detach, 2280 .mode_valid = zynqmp_dp_bridge_mode_valid, 2281 .atomic_enable = zynqmp_dp_bridge_atomic_enable, 2282 .atomic_disable = zynqmp_dp_bridge_atomic_disable, 2283 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2284 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2285 .atomic_reset = drm_atomic_helper_bridge_reset, 2286 .atomic_check = zynqmp_dp_bridge_atomic_check, 2287 .detect = zynqmp_dp_bridge_detect, 2288 .edid_read = zynqmp_dp_bridge_edid_read, 2289 .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts, 2290 .debugfs_init = zynqmp_dp_bridge_debugfs_init, 2291}; 2292 2293/* ----------------------------------------------------------------------------- 2294 * Interrupt Handling 2295 */ 2296 2297/** 2298 * zynqmp_dp_enable_vblank - Enable vblank 2299 * @dp: DisplayPort IP core structure 2300 * 2301 * Enable vblank interrupt 2302 */ 2303void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp) 2304{ 2305 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START); 2306} 2307 2308/** 2309 * zynqmp_dp_disable_vblank - Disable vblank 2310 * @dp: DisplayPort IP core structure 2311 * 2312 * Disable vblank interrupt 2313 */ 2314void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp) 2315{ 2316 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START); 2317} 2318 2319static void zynqmp_dp_hpd_work_func(struct work_struct *work) 2320{ 2321 struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, hpd_work); 2322 enum drm_connector_status status; 2323 2324 scoped_guard(mutex, &dp->lock) { 2325 if (dp->ignore_hpd) 2326 return; 2327 2328 status = __zynqmp_dp_bridge_detect(dp); 2329 } 2330 2331 drm_bridge_hpd_notify(&dp->bridge, status); 2332} 2333 2334static void zynqmp_dp_hpd_irq_work_func(struct work_struct *work) 2335{ 2336 struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, 2337 hpd_irq_work); 2338 u8 status[DP_LINK_STATUS_SIZE + 2]; 2339 int err; 2340 2341 guard(mutex)(&dp->lock); 2342 if (dp->ignore_hpd) 2343 return; 2344 2345 err = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status, 2346 DP_LINK_STATUS_SIZE + 2); 2347 if (err < 0) { 2348 dev_dbg_ratelimited(dp->dev, 2349 "could not read sink status: %d\n", err); 2350 } else { 2351 if (status[4] & DP_LINK_STATUS_UPDATED || 2352 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) || 2353 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) { 2354 zynqmp_dp_train_loop(dp); 2355 } 2356 } 2357} 2358 2359static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data) 2360{ 2361 struct zynqmp_dp *dp = (struct zynqmp_dp *)data; 2362 u32 status, mask; 2363 2364 status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); 2365 /* clear status register as soon as we read it */ 2366 zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); 2367 mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); 2368 2369 /* 2370 * Status register may report some events, which corresponding interrupts 2371 * have been disabled. Filter out those events against interrupts' mask. 2372 */ 2373 status &= ~mask; 2374 2375 if (!status) 2376 return IRQ_NONE; 2377 2378 /* dbg for diagnostic, but not much that the driver can do */ 2379 if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK) 2380 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n"); 2381 if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK) 2382 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); 2383 2384 if (status & ZYNQMP_DP_INT_VBLANK_START) 2385 zynqmp_dpsub_drm_handle_vblank(dp->dpsub); 2386 2387 if (status & ZYNQMP_DP_INT_HPD_EVENT) 2388 schedule_work(&dp->hpd_work); 2389 2390 if (status & ZYNQMP_DP_INT_HPD_IRQ) 2391 schedule_work(&dp->hpd_irq_work); 2392 2393 if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY) 2394 complete(&dp->aux_done); 2395 2396 if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT) 2397 complete(&dp->aux_done); 2398 2399 return IRQ_HANDLED; 2400} 2401 2402/* ----------------------------------------------------------------------------- 2403 * Initialization & Cleanup 2404 */ 2405 2406int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub) 2407{ 2408 struct platform_device *pdev = to_platform_device(dpsub->dev); 2409 struct drm_bridge *bridge; 2410 struct zynqmp_dp *dp; 2411 int ret; 2412 2413 dp = devm_drm_bridge_alloc(&pdev->dev, struct zynqmp_dp, bridge, &zynqmp_dp_bridge_funcs); 2414 if (IS_ERR(dp)) 2415 return PTR_ERR(dp); 2416 2417 dp->dev = &pdev->dev; 2418 dp->dpsub = dpsub; 2419 dp->status = connector_status_disconnected; 2420 mutex_init(&dp->lock); 2421 init_completion(&dp->aux_done); 2422 2423 INIT_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func); 2424 INIT_WORK(&dp->hpd_irq_work, zynqmp_dp_hpd_irq_work_func); 2425 2426 /* Acquire all resources (IOMEM, IRQ and PHYs). */ 2427 dp->iomem = devm_platform_ioremap_resource_byname(pdev, "dp"); 2428 if (IS_ERR(dp->iomem)) 2429 return PTR_ERR(dp->iomem); 2430 2431 dp->irq = platform_get_irq(pdev, 0); 2432 if (dp->irq < 0) 2433 return dp->irq; 2434 2435 dp->reset = devm_reset_control_get(dp->dev, NULL); 2436 if (IS_ERR(dp->reset)) 2437 return dev_err_probe(dp->dev, PTR_ERR(dp->reset), 2438 "failed to get reset\n"); 2439 2440 ret = zynqmp_dp_reset(dp, true); 2441 if (ret < 0) 2442 return ret; 2443 2444 ret = zynqmp_dp_reset(dp, false); 2445 if (ret < 0) 2446 return ret; 2447 2448 ret = zynqmp_dp_phy_probe(dp); 2449 if (ret) 2450 goto err_reset; 2451 2452 /* Initialize the bridge. */ 2453 bridge = &dp->bridge; 2454 bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 2455 | DRM_BRIDGE_OP_HPD; 2456 bridge->type = DRM_MODE_CONNECTOR_DisplayPort; 2457 bridge->of_node = dp->dev->of_node; 2458 dpsub->bridge = bridge; 2459 2460 /* 2461 * Acquire the next bridge in the chain. Ignore errors caused by port@5 2462 * not being connected for backward-compatibility with older DTs. 2463 */ 2464 ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 5, 0, NULL, 2465 &dp->next_bridge); 2466 if (ret < 0 && ret != -ENODEV) 2467 goto err_reset; 2468 2469 /* Initialize the hardware. */ 2470 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK; 2471 zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8); 2472 2473 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 2474 ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL); 2475 zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); 2476 zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1); 2477 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 2478 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 2479 2480 ret = zynqmp_dp_phy_init(dp); 2481 if (ret) 2482 goto err_reset; 2483 2484 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1); 2485 2486 /* 2487 * Now that the hardware is initialized and won't generate spurious 2488 * interrupts, request the IRQ. 2489 */ 2490 ret = devm_request_irq(dp->dev, dp->irq, zynqmp_dp_irq_handler, 2491 IRQF_SHARED, dev_name(dp->dev), dp); 2492 if (ret < 0) 2493 goto err_phy_exit; 2494 2495 dpsub->dp = dp; 2496 2497 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n", 2498 dp->num_lanes); 2499 2500 return 0; 2501 2502err_phy_exit: 2503 zynqmp_dp_phy_exit(dp); 2504err_reset: 2505 zynqmp_dp_reset(dp, true); 2506 return ret; 2507} 2508 2509void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub) 2510{ 2511 struct zynqmp_dp *dp = dpsub->dp; 2512 2513 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL); 2514 devm_free_irq(dp->dev, dp->irq, dp); 2515 2516 cancel_work_sync(&dp->hpd_irq_work); 2517 cancel_work_sync(&dp->hpd_work); 2518 2519 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); 2520 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); 2521 2522 zynqmp_dp_phy_exit(dp); 2523 zynqmp_dp_reset(dp, true); 2524 mutex_destroy(&dp->lock); 2525}
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