FILE
xe_wa.c
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/xe/xe_wa.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6#include "xe_wa.h" 7 8#include <drm/drm_managed.h> 9#include <kunit/visibility.h> 10#include <linux/compiler_types.h> 11#include <linux/fault-inject.h> 12 13#include <generated/xe_device_wa_oob.h> 14#include <generated/xe_wa_oob.h> 15 16#include "regs/xe_engine_regs.h" 17#include "regs/xe_gt_regs.h" 18#include "regs/xe_guc_regs.h" 19#include "regs/xe_regs.h" 20#include "xe_device_types.h" 21#include "xe_force_wake.h" 22#include "xe_gt.h" 23#include "xe_hw_engine_types.h" 24#include "xe_mmio.h" 25#include "xe_platform_types.h" 26#include "xe_rtp.h" 27#include "xe_sriov.h" 28#include "xe_step.h" 29 30/** 31 * DOC: Hardware workarounds 32 * 33 * Hardware workarounds are register programming documented to be executed in 34 * the driver that fall outside of the normal programming sequences for a 35 * platform. There are some basic categories of workarounds, depending on 36 * how/when they are applied: 37 * 38 * - LRC workarounds: workarounds that touch registers that are 39 * saved/restored to/from the HW context image. The list is emitted (via Load 40 * Register Immediate commands) once when initializing the device and saved in 41 * the default context. That default context is then used on every context 42 * creation to have a "primed golden context", i.e. a context image that 43 * already contains the changes needed to all the registers. See 44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling. 45 * 46 * - Engine workarounds: the list of these WAs is applied whenever the specific 47 * engine is reset. It's also possible that a set of engine classes share a 48 * common power domain and they are reset together. This happens on some 49 * platforms with render and compute engines. In this case (at least) one of 50 * them need to keeep the workaround programming: the approach taken in the 51 * driver is to tie those workarounds to the first compute/render engine that 52 * is registered. When executing with GuC submission, engine resets are 53 * outside of kernel driver control, hence the list of registers involved is 54 * written once, on engine initialization, and then passed to GuC, that 55 * saves/restores their values before/after the reset takes place. See 56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference. 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * - Workaround batchbuffers: buffers that get executed automatically by the 68 * hardware on every HW context restore. These buffers are created and 69 * programmed in the default context so the hardware always go through those 70 * programming sequences when switching contexts. The support for workaround 71 * batchbuffers is enabled via these hardware mechanisms: 72 * 73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer 74 * and an offset are provided in the default context, pointing the hardware 75 * to jump to that location when that offset is reached in the context 76 * restore. When a context is being restored, this is executed after the 77 * ring context, in the middle (or beginning) of the engine context image. 78 * 79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A 80 * batchbuffer is provided in the default context, pointing the hardware to 81 * a buffer to continue executing after the engine registers are restored 82 * in a context restore sequence. 83 * 84 * Below is the timeline for a context restore sequence: 85 * 86 * .. code:: 87 * 88 * INDIRECT_CTX_OFFSET 89 * |----------->| 90 * .------------.------------.-------------.------------.--------------.-----------. 91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring | 92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution | 93 * `------------'------------'-------------'------------'--------------'-----------' 94 * 95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 96 * a central place. Those are peppered around the rest of the code, as needed. 97 * There's a central place to control which workarounds are enabled: 98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and 99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds. 100 * These files only record which workarounds are enabled: during early device 101 * initialization those rules are evaluated and recorded by the driver. Then 102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to 103 * implement them. 104 * 105 * .. [1] Technically, some registers are powercontext saved & restored, so they 106 * survive a suspend/resume. In practice, writing them again is not too 107 * costly and simplifies things, so it's the approach taken in the driver. 108 * 109 * .. note:: 110 * Hardware workarounds in xe work the same way as in i915, with the 111 * difference of how they are maintained in the code. In xe it uses the 112 * xe_rtp infrastructure so the workarounds can be kept in tables, following 113 * a more declarative approach rather than procedural. 114 */ 115 116#undef XE_REG_MCR 117#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 118 119__diag_push(); 120__diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 121 122static const struct xe_rtp_entry_sr gt_was[] = { 123 { XE_RTP_NAME("14011060649"), 124 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 125 ENGINE_CLASS(VIDEO_DECODE), 126 FUNC(xe_rtp_match_even_instance)), 127 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 128 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 129 }, 130 { XE_RTP_NAME("14011059788"), 131 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 132 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 133 }, 134 { XE_RTP_NAME("14015795083"), 135 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 136 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 137 }, 138 139 /* DG1 */ 140 141 { XE_RTP_NAME("1409420604"), 142 XE_RTP_RULES(PLATFORM(DG1)), 143 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 144 }, 145 { XE_RTP_NAME("1408615072"), 146 XE_RTP_RULES(PLATFORM(DG1)), 147 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 148 }, 149 150 /* DG2 */ 151 152 { XE_RTP_NAME("22010523718"), 153 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 154 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 155 }, 156 { XE_RTP_NAME("14011006942"), 157 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 158 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 159 }, 160 { XE_RTP_NAME("14014830051"), 161 XE_RTP_RULES(PLATFORM(DG2)), 162 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 163 }, 164 { XE_RTP_NAME("18018781329"), 165 XE_RTP_RULES(PLATFORM(DG2)), 166 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 167 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 168 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 169 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 170 }, 171 { XE_RTP_NAME("1509235366"), 172 XE_RTP_RULES(PLATFORM(DG2)), 173 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 174 INVALIDATION_BROADCAST_MODE_DIS | 175 GLOBAL_INVALIDATION_MODE)) 176 }, 177 178 /* PVC */ 179 180 { XE_RTP_NAME("18018781329"), 181 XE_RTP_RULES(PLATFORM(PVC)), 182 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 183 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 184 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 185 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 186 }, 187 { XE_RTP_NAME("16016694945"), 188 XE_RTP_RULES(PLATFORM(PVC)), 189 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 190 }, 191 192 /* Xe_LPG */ 193 194 { XE_RTP_NAME("14015795083"), 195 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 196 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 197 }, 198 { XE_RTP_NAME("14018575942"), 199 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 200 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 201 }, 202 { XE_RTP_NAME("22016670082"), 203 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 204 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 205 }, 206 207 /* Xe_LPM+ */ 208 209 { XE_RTP_NAME("16021867713"), 210 XE_RTP_RULES(MEDIA_VERSION(1300), 211 ENGINE_CLASS(VIDEO_DECODE)), 212 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 213 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 214 }, 215 { XE_RTP_NAME("22016670082"), 216 XE_RTP_RULES(MEDIA_VERSION(1300)), 217 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 218 }, 219 220 /* Xe2_LPG */ 221 222 { XE_RTP_NAME("16020975621"), 223 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 224 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 225 }, 226 { XE_RTP_NAME("14018157293"), 227 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 228 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 229 SET(XEHPC_L3CLOS_MASK(1), ~0), 230 SET(XEHPC_L3CLOS_MASK(2), ~0), 231 SET(XEHPC_L3CLOS_MASK(3), ~0)) 232 }, 233 234 /* Xe2_LPM */ 235 236 { XE_RTP_NAME("14017421178"), 237 XE_RTP_RULES(MEDIA_VERSION(2000), 238 ENGINE_CLASS(VIDEO_DECODE)), 239 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 240 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 241 }, 242 { XE_RTP_NAME("16021867713"), 243 XE_RTP_RULES(MEDIA_VERSION(2000), 244 ENGINE_CLASS(VIDEO_DECODE)), 245 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 246 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 247 }, 248 { XE_RTP_NAME("14019449301"), 249 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 250 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 251 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 252 }, 253 254 /* Xe2_HPG */ 255 256 { XE_RTP_NAME("16025250150"), 257 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 258 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2, 259 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK | 260 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK | 261 LSN_DIM_Z_WGT_MASK, 262 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 263 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 264 LSN_DIM_Z_WGT(1)), 265 SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS)) 266 }, 267 268 /* Xe2_HPM */ 269 270 { XE_RTP_NAME("16021867713"), 271 XE_RTP_RULES(MEDIA_VERSION(1301), 272 ENGINE_CLASS(VIDEO_DECODE)), 273 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 274 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 275 }, 276 { XE_RTP_NAME("14019449301"), 277 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 278 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 279 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 280 }, 281 282 /* Xe3_LPG */ 283 284 { XE_RTP_NAME("14021871409"), 285 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 286 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 287 }, 288 289 /* Xe3_LPM */ 290 291 { XE_RTP_NAME("16021867713"), 292 XE_RTP_RULES(MEDIA_VERSION(3000), 293 ENGINE_CLASS(VIDEO_DECODE)), 294 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 295 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 296 }, 297 { XE_RTP_NAME("16021865536"), 298 XE_RTP_RULES(MEDIA_VERSION(3000), 299 ENGINE_CLASS(VIDEO_DECODE)), 300 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 301 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 302 }, 303 { XE_RTP_NAME("16021865536"), 304 XE_RTP_RULES(MEDIA_VERSION(3002), 305 ENGINE_CLASS(VIDEO_DECODE)), 306 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 307 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 308 }, 309 { XE_RTP_NAME("16021867713"), 310 XE_RTP_RULES(MEDIA_VERSION(3002), 311 ENGINE_CLASS(VIDEO_DECODE)), 312 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 313 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 314 }, 315 { XE_RTP_NAME("14021486841"), 316 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 317 ENGINE_CLASS(VIDEO_DECODE)), 318 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 319 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 320 }, 321 { XE_RTP_NAME("16028005424"), 322 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)), 323 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) 324 }, 325}; 326 327static const struct xe_rtp_entry_sr engine_was[] = { 328 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 329 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 330 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 331 FF_TESSELATION_DOP_GATE_DISABLE)) 332 }, 333 { XE_RTP_NAME("1409804808"), 334 XE_RTP_RULES(GRAPHICS_VERSION(1200), 335 ENGINE_CLASS(RENDER), 336 IS_INTEGRATED), 337 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 338 }, 339 { XE_RTP_NAME("14010229206, 1409085225"), 340 XE_RTP_RULES(GRAPHICS_VERSION(1200), 341 ENGINE_CLASS(RENDER), 342 IS_INTEGRATED), 343 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 344 }, 345 { XE_RTP_NAME("1606931601"), 346 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 347 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 348 }, 349 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 350 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 351 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 352 FF_DOP_CLOCK_GATE_DISABLE)) 353 }, 354 { XE_RTP_NAME("1406941453"), 355 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 356 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 357 }, 358 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 359 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 360 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 361 FFSC_PERCTX_PREEMPT_CTRL)) 362 }, 363 364 /* TGL */ 365 366 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 367 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 368 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 369 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 370 RC_SEMA_IDLE_MSG_DISABLE)) 371 }, 372 373 /* RKL */ 374 375 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 376 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 377 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 378 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 379 RC_SEMA_IDLE_MSG_DISABLE)) 380 }, 381 382 /* ADL-P */ 383 384 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 385 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 386 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 387 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 388 RC_SEMA_IDLE_MSG_DISABLE)) 389 }, 390 391 /* DG2 */ 392 393 { XE_RTP_NAME("22013037850"), 394 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 395 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 396 DISABLE_128B_EVICTION_COMMAND_UDW)) 397 }, 398 { XE_RTP_NAME("22014226127"), 399 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 400 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 401 }, 402 { XE_RTP_NAME("18017747507"), 403 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 404 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 405 POLYGON_TRIFAN_LINELOOP_DISABLE)) 406 }, 407 { XE_RTP_NAME("22012826095, 22013059131"), 408 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 409 FUNC(xe_rtp_match_first_render_or_compute)), 410 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 411 MAXREQS_PER_BANK, 412 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 413 }, 414 { XE_RTP_NAME("22013059131"), 415 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 416 FUNC(xe_rtp_match_first_render_or_compute)), 417 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 418 }, 419 { XE_RTP_NAME("14015227452"), 420 XE_RTP_RULES(PLATFORM(DG2), 421 FUNC(xe_rtp_match_first_render_or_compute)), 422 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 423 }, 424 { XE_RTP_NAME("18028616096"), 425 XE_RTP_RULES(PLATFORM(DG2), 426 FUNC(xe_rtp_match_first_render_or_compute)), 427 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 428 }, 429 { XE_RTP_NAME("22015475538"), 430 XE_RTP_RULES(PLATFORM(DG2), 431 FUNC(xe_rtp_match_first_render_or_compute)), 432 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 433 }, 434 { XE_RTP_NAME("22012654132"), 435 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 436 FUNC(xe_rtp_match_first_render_or_compute)), 437 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 438 /* 439 * Register can't be read back for verification on 440 * DG2 due to Wa_14012342262 441 */ 442 .read_mask = 0)) 443 }, 444 { XE_RTP_NAME("1509727124"), 445 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 446 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 447 }, 448 { XE_RTP_NAME("22012856258"), 449 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 450 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 451 }, 452 { XE_RTP_NAME("22010960976, 14013347512"), 453 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 454 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 455 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 456 }, 457 { XE_RTP_NAME("14015150844"), 458 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 459 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 460 XE_RTP_NOCHECK)) 461 }, 462 463 /* PVC */ 464 465 { XE_RTP_NAME("22014226127"), 466 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 467 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 468 }, 469 { XE_RTP_NAME("14015227452"), 470 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 471 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 472 }, 473 { XE_RTP_NAME("18020744125"), 474 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 475 ENGINE_CLASS(COMPUTE)), 476 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 477 }, 478 { XE_RTP_NAME("14014999345"), 479 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 480 GRAPHICS_STEP(B0, C0)), 481 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 482 }, 483 484 /* Xe_LPG */ 485 486 { XE_RTP_NAME("14017856879"), 487 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 488 FUNC(xe_rtp_match_first_render_or_compute)), 489 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 490 }, 491 { XE_RTP_NAME("14015150844"), 492 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 493 FUNC(xe_rtp_match_first_render_or_compute)), 494 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 495 XE_RTP_NOCHECK)) 496 }, 497 { XE_RTP_NAME("14020495402"), 498 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 499 FUNC(xe_rtp_match_first_render_or_compute)), 500 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 501 }, 502 503 /* Xe2_LPG */ 504 505 { XE_RTP_NAME("18032247524"), 506 XE_RTP_RULES(GRAPHICS_VERSION(2004), 507 FUNC(xe_rtp_match_first_render_or_compute)), 508 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 509 }, 510 { XE_RTP_NAME("16018712365"), 511 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 512 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 513 }, 514 { XE_RTP_NAME("14018957109"), 515 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 516 FUNC(xe_rtp_match_first_render_or_compute)), 517 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 518 }, 519 { XE_RTP_NAME("14020338487"), 520 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 521 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 522 }, 523 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 524 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 525 FUNC(xe_rtp_match_first_render_or_compute)), 526 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 527 }, 528 { XE_RTP_NAME("14019322943"), 529 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 530 FUNC(xe_rtp_match_first_render_or_compute)), 531 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 532 }, 533 { XE_RTP_NAME("14018471104"), 534 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 535 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 536 }, 537 /* 538 * These two workarounds are the same, just applying to different 539 * engines. Although Wa_18032095049 (for the RCS) isn't required on 540 * all steppings, disabling these reports has no impact for our 541 * driver or the GuC, so we go ahead and treat it the same as 542 * Wa_16021639441 which does apply to all steppings. 543 */ 544 { XE_RTP_NAME("18032095049, 16021639441"), 545 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 546 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 547 GHWSP_CSB_REPORT_DIS | 548 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 549 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 550 }, 551 { XE_RTP_NAME("16018610683"), 552 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 553 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 554 }, 555 { XE_RTP_NAME("14021402888"), 556 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 557 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 558 }, 559 { XE_RTP_NAME("13012615864"), 560 XE_RTP_RULES(GRAPHICS_VERSION(2004), 561 FUNC(xe_rtp_match_first_render_or_compute)), 562 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 563 }, 564 565 /* Xe2_HPG */ 566 567 { XE_RTP_NAME("16018712365"), 568 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 569 FUNC(xe_rtp_match_first_render_or_compute)), 570 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 571 }, 572 { XE_RTP_NAME("16018737384"), 573 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 574 FUNC(xe_rtp_match_first_render_or_compute)), 575 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 576 }, 577 { XE_RTP_NAME("14020338487"), 578 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 579 FUNC(xe_rtp_match_first_render_or_compute)), 580 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 581 }, 582 { XE_RTP_NAME("18032247524"), 583 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 584 FUNC(xe_rtp_match_first_render_or_compute)), 585 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 586 }, 587 { XE_RTP_NAME("14018471104"), 588 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 589 FUNC(xe_rtp_match_first_render_or_compute)), 590 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 591 }, 592 /* 593 * Although this workaround isn't required for the RCS, disabling these 594 * reports has no impact for our driver or the GuC, so we go ahead and 595 * apply this to all engines for simplicity. 596 */ 597 { XE_RTP_NAME("16021639441"), 598 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)), 599 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 600 GHWSP_CSB_REPORT_DIS | 601 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 602 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 603 }, 604 { XE_RTP_NAME("14019811474"), 605 XE_RTP_RULES(GRAPHICS_VERSION(2001), 606 FUNC(xe_rtp_match_first_render_or_compute)), 607 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 608 }, 609 { XE_RTP_NAME("14021402888"), 610 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 611 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 612 }, 613 { XE_RTP_NAME("14021821874, 14022954250"), 614 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 615 FUNC(xe_rtp_match_first_render_or_compute)), 616 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 617 }, 618 { XE_RTP_NAME("13012615864"), 619 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 620 FUNC(xe_rtp_match_first_render_or_compute)), 621 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 622 }, 623 { XE_RTP_NAME("18041344222"), 624 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), 625 FUNC(xe_rtp_match_first_render_or_compute), 626 FUNC(xe_rtp_match_not_sriov_vf), 627 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 628 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 629 }, 630 631 /* Xe2_LPM */ 632 633 { XE_RTP_NAME("16021639441"), 634 XE_RTP_RULES(MEDIA_VERSION(2000)), 635 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 636 GHWSP_CSB_REPORT_DIS | 637 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 638 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 639 }, 640 641 /* Xe2_HPM */ 642 643 { XE_RTP_NAME("16021639441"), 644 XE_RTP_RULES(MEDIA_VERSION(1301)), 645 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 646 GHWSP_CSB_REPORT_DIS | 647 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 648 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 649 }, 650 651 /* Xe3_LPG */ 652 653 { XE_RTP_NAME("14021402888"), 654 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 655 FUNC(xe_rtp_match_first_render_or_compute)), 656 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 657 }, 658 { XE_RTP_NAME("18034896535"), 659 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 660 FUNC(xe_rtp_match_first_render_or_compute)), 661 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 662 }, 663 { XE_RTP_NAME("16024792527"), 664 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 665 FUNC(xe_rtp_match_first_render_or_compute)), 666 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 667 SMP_FORCE_128B_OVERFETCH)) 668 }, 669 { XE_RTP_NAME("14023061436"), 670 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 671 FUNC(xe_rtp_match_first_render_or_compute), OR, 672 GRAPHICS_VERSION_RANGE(3003, 3005), 673 FUNC(xe_rtp_match_first_render_or_compute)), 674 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 675 }, 676 { XE_RTP_NAME("13012615864"), 677 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR, 678 GRAPHICS_VERSION_RANGE(3003, 3005), 679 FUNC(xe_rtp_match_first_render_or_compute)), 680 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 681 }, 682 { XE_RTP_NAME("16023105232"), 683 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR, 684 GRAPHICS_VERSION_RANGE(2001, 3001)), 685 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE, 686 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 687 }, 688 { XE_RTP_NAME("14021402888"), 689 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)), 690 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 691 }, 692 { XE_RTP_NAME("18041344222"), 693 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 694 FUNC(xe_rtp_match_first_render_or_compute), 695 FUNC(xe_rtp_match_not_sriov_vf), 696 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)), 697 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE)) 698 }, 699}; 700 701static const struct xe_rtp_entry_sr lrc_was[] = { 702 { XE_RTP_NAME("16011163337"), 703 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 704 /* read verification is ignored due to 1608008084. */ 705 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 706 FF_MODE2_GS_TIMER_MASK, 707 FF_MODE2_GS_TIMER_224)) 708 }, 709 { XE_RTP_NAME("1604555607"), 710 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 711 /* read verification is ignored due to 1608008084. */ 712 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 713 FF_MODE2_TDS_TIMER_MASK, 714 FF_MODE2_TDS_TIMER_128)) 715 }, 716 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 717 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 718 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 719 DISABLE_CPS_AWARE_COLOR_PIPE)) 720 }, 721 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 722 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 723 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 724 PREEMPT_GPGPU_LEVEL_MASK, 725 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 726 }, 727 { XE_RTP_NAME("1806527549"), 728 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 729 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 730 }, 731 { XE_RTP_NAME("1606376872"), 732 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 733 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 734 }, 735 736 /* DG1 */ 737 738 { XE_RTP_NAME("1409044764"), 739 XE_RTP_RULES(PLATFORM(DG1)), 740 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 741 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 742 }, 743 { XE_RTP_NAME("22010493298"), 744 XE_RTP_RULES(PLATFORM(DG1)), 745 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 746 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 747 }, 748 749 /* DG2 */ 750 751 { XE_RTP_NAME("16013271637"), 752 XE_RTP_RULES(PLATFORM(DG2)), 753 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 754 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 755 }, 756 { XE_RTP_NAME("14014947963"), 757 XE_RTP_RULES(PLATFORM(DG2)), 758 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 759 PREEMPTION_VERTEX_COUNT, 760 0x4000)) 761 }, 762 { XE_RTP_NAME("18018764978"), 763 XE_RTP_RULES(PLATFORM(DG2)), 764 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 765 SCOREBOARD_STALL_FLUSH_CONTROL)) 766 }, 767 { XE_RTP_NAME("18019271663"), 768 XE_RTP_RULES(PLATFORM(DG2)), 769 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 770 }, 771 { XE_RTP_NAME("14019877138"), 772 XE_RTP_RULES(PLATFORM(DG2)), 773 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 774 }, 775 776 /* PVC */ 777 778 { XE_RTP_NAME("16017236439"), 779 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 780 FUNC(xe_rtp_match_even_instance)), 781 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 782 BCS_SWCTRL_DISABLE_256B, 783 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 784 }, 785 786 /* Xe_LPG */ 787 788 { XE_RTP_NAME("18019271663"), 789 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 790 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 791 }, 792 { XE_RTP_NAME("14019877138"), 793 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 794 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 795 }, 796 797 /* Xe2_LPG */ 798 799 { XE_RTP_NAME("16020518922"), 800 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 801 ENGINE_CLASS(RENDER)), 802 XE_RTP_ACTIONS(SET(FF_MODE, 803 DIS_TE_AUTOSTRIP | 804 DIS_MESH_PARTIAL_AUTOSTRIP | 805 DIS_MESH_AUTOSTRIP), 806 SET(VFLSKPD, 807 DIS_PARTIAL_AUTOSTRIP | 808 DIS_AUTOSTRIP)) 809 }, 810 { XE_RTP_NAME("14019386621"), 811 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 812 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 813 }, 814 { XE_RTP_NAME("14019877138"), 815 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 816 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 817 }, 818 { XE_RTP_NAME("14020013138"), 819 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 820 ENGINE_CLASS(RENDER)), 821 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 822 }, 823 { XE_RTP_NAME("14019988906"), 824 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 825 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 826 }, 827 { XE_RTP_NAME("16020183090"), 828 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 829 ENGINE_CLASS(RENDER)), 830 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 831 }, 832 { XE_RTP_NAME("18033852989"), 833 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 834 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 835 }, 836 { XE_RTP_NAME("14021567978"), 837 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 838 ENGINE_CLASS(RENDER)), 839 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 840 }, 841 { XE_RTP_NAME("14020756599"), 842 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 843 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 844 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 845 }, 846 { XE_RTP_NAME("14021490052"), 847 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 848 XE_RTP_ACTIONS(SET(FF_MODE, 849 DIS_MESH_PARTIAL_AUTOSTRIP | 850 DIS_MESH_AUTOSTRIP), 851 SET(VFLSKPD, 852 DIS_PARTIAL_AUTOSTRIP | 853 DIS_AUTOSTRIP)) 854 }, 855 { XE_RTP_NAME("15016589081"), 856 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 857 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 858 }, 859 860 /* Xe2_HPG */ 861 { XE_RTP_NAME("15010599737"), 862 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 863 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 864 }, 865 { XE_RTP_NAME("14019386621"), 866 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 867 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 868 }, 869 { XE_RTP_NAME("14020756599"), 870 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 871 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 872 }, 873 { XE_RTP_NAME("14019988906"), 874 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 875 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 876 }, 877 { XE_RTP_NAME("14019877138"), 878 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 879 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 880 }, 881 { XE_RTP_NAME("14021490052"), 882 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 883 XE_RTP_ACTIONS(SET(FF_MODE, 884 DIS_MESH_PARTIAL_AUTOSTRIP | 885 DIS_MESH_AUTOSTRIP), 886 SET(VFLSKPD, 887 DIS_PARTIAL_AUTOSTRIP | 888 DIS_AUTOSTRIP)) 889 }, 890 { XE_RTP_NAME("15016589081"), 891 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 892 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 893 }, 894 { XE_RTP_NAME("22021007897"), 895 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)), 896 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 897 }, 898 { XE_RTP_NAME("18033852989"), 899 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 900 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 901 }, 902 903 /* Xe3_LPG */ 904 { XE_RTP_NAME("14021490052"), 905 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 906 ENGINE_CLASS(RENDER)), 907 XE_RTP_ACTIONS(SET(FF_MODE, 908 DIS_MESH_PARTIAL_AUTOSTRIP | 909 DIS_MESH_AUTOSTRIP), 910 SET(VFLSKPD, 911 DIS_PARTIAL_AUTOSTRIP | 912 DIS_AUTOSTRIP)) 913 }, 914 { XE_RTP_NAME("22021007897"), 915 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 916 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE)) 917 }, 918 { XE_RTP_NAME("14024681466"), 919 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)), 920 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX)) 921 }, 922 { XE_RTP_NAME("15016589081"), 923 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 924 ENGINE_CLASS(RENDER)), 925 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 926 }, 927}; 928 929static __maybe_unused const struct xe_rtp_entry oob_was[] = { 930#include <generated/xe_wa_oob.c> 931 {} 932}; 933 934static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 935 936static __maybe_unused const struct xe_rtp_entry device_oob_was[] = { 937#include <generated/xe_device_wa_oob.c> 938 {} 939}; 940 941static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT); 942 943__diag_pop(); 944 945/** 946 * xe_wa_process_device_oob - process OOB workaround table 947 * @xe: device instance to process workarounds for 948 * 949 * process OOB workaround table for this device, marking in @xe the 950 * workarounds that are active. 951 */ 952 953void xe_wa_process_device_oob(struct xe_device *xe) 954{ 955 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe); 956 957 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)); 958 959 xe->wa_active.oob_initialized = true; 960 xe_rtp_process(&ctx, device_oob_was); 961} 962 963/** 964 * xe_wa_process_gt_oob - process GT OOB workaround table 965 * @gt: GT instance to process workarounds for 966 * 967 * Process OOB workaround table for this platform, marking in @gt the 968 * workarounds that are active. 969 */ 970void xe_wa_process_gt_oob(struct xe_gt *gt) 971{ 972 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 973 974 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 975 ARRAY_SIZE(oob_was)); 976 gt->wa_active.oob_initialized = true; 977 xe_rtp_process(&ctx, oob_was); 978} 979 980/** 981 * xe_wa_process_gt - process GT workaround table 982 * @gt: GT instance to process workarounds for 983 * 984 * Process GT workaround table for this platform, saving in @gt all the 985 * workarounds that need to be applied at the GT level. 986 */ 987void xe_wa_process_gt(struct xe_gt *gt) 988{ 989 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 990 991 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 992 ARRAY_SIZE(gt_was)); 993 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 994} 995EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 996 997/** 998 * xe_wa_process_engine - process engine workaround table 999 * @hwe: engine instance to process workarounds for 1000 * 1001 * Process engine workaround table for this platform, saving in @hwe all the 1002 * workarounds that need to be applied at the engine level that match this 1003 * engine. 1004 */ 1005void xe_wa_process_engine(struct xe_hw_engine *hwe) 1006{ 1007 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 1008 1009 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 1010 ARRAY_SIZE(engine_was)); 1011 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 1012} 1013 1014/** 1015 * xe_wa_process_lrc - process context workaround table 1016 * @hwe: engine instance to process workarounds for 1017 * 1018 * Process context workaround table for this platform, saving in @hwe all the 1019 * workarounds that need to be applied on context restore. These are workarounds 1020 * touching registers that are part of the HW context image. 1021 */ 1022void xe_wa_process_lrc(struct xe_hw_engine *hwe) 1023{ 1024 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 1025 1026 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 1027 ARRAY_SIZE(lrc_was)); 1028 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 1029} 1030 1031/** 1032 * xe_wa_device_init - initialize device with workaround oob bookkeeping 1033 * @xe: Xe device instance to initialize 1034 * 1035 * Returns 0 for success, negative with error code otherwise 1036 */ 1037int xe_wa_device_init(struct xe_device *xe) 1038{ 1039 unsigned long *p; 1040 1041 p = drmm_kzalloc(&xe->drm, 1042 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)), 1043 GFP_KERNEL); 1044 1045 if (!p) 1046 return -ENOMEM; 1047 1048 xe->wa_active.oob = p; 1049 1050 return 0; 1051} 1052 1053/** 1054 * xe_wa_gt_init - initialize gt with workaround bookkeeping 1055 * @gt: GT instance to initialize 1056 * 1057 * Returns 0 for success, negative error code otherwise. 1058 */ 1059int xe_wa_gt_init(struct xe_gt *gt) 1060{ 1061 struct xe_device *xe = gt_to_xe(gt); 1062 size_t n_oob, n_lrc, n_engine, n_gt, total; 1063 unsigned long *p; 1064 1065 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 1066 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 1067 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 1068 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 1069 total = n_gt + n_engine + n_lrc + n_oob; 1070 1071 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 1072 if (!p) 1073 return -ENOMEM; 1074 1075 gt->wa_active.gt = p; 1076 p += n_gt; 1077 gt->wa_active.engine = p; 1078 p += n_engine; 1079 gt->wa_active.lrc = p; 1080 p += n_lrc; 1081 gt->wa_active.oob = p; 1082 1083 return 0; 1084} 1085ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */ 1086 1087void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p) 1088{ 1089 size_t idx; 1090 1091 drm_printf(p, "Device OOB Workarounds\n"); 1092 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was)) 1093 if (device_oob_was[idx].name) 1094 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name); 1095} 1096 1097/** 1098 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer. 1099 * @gt: the &xe_gt 1100 * @p: the &drm_printer 1101 * 1102 * Return: always 0. 1103 */ 1104int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p) 1105{ 1106 size_t idx; 1107 1108 drm_printf(p, "GT Workarounds\n"); 1109 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 1110 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 1111 1112 drm_puts(p, "\n"); 1113 drm_printf(p, "Engine Workarounds\n"); 1114 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 1115 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 1116 1117 drm_puts(p, "\n"); 1118 drm_printf(p, "LRC Workarounds\n"); 1119 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 1120 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 1121 1122 drm_puts(p, "\n"); 1123 drm_printf(p, "OOB Workarounds\n"); 1124 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 1125 if (oob_was[idx].name) 1126 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 1127 return 0; 1128} 1129 1130/* 1131 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 1132 * adding anything to this function; most workarounds should be implemented 1133 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 1134 * which are relatively rare. Since the registers these workarounds target are 1135 * outside the GT, they should only need to be applied once at device 1136 * probe/resume; they will not lose their values on any kind of GT or engine 1137 * reset. 1138 * 1139 * TODO: We may want to move this over to xe_rtp in the future once we have 1140 * enough workarounds to justify the work. 1141 */ 1142void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 1143{ 1144 struct xe_mmio *mmio = &tile->mmio; 1145 1146 if (IS_SRIOV_VF(tile->xe)) 1147 return; 1148 1149 if (XE_DEVICE_WA(tile->xe, 22010954014)) 1150 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 1151}
~/
Read-only file preview.