xe_reg_whitelist.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#include "xe_reg_whitelist.h"
  7
  8#include "regs/xe_engine_regs.h"
  9#include "regs/xe_gt_regs.h"
 10#include "regs/xe_oa_regs.h"
 11#include "regs/xe_regs.h"
 12#include "xe_gt_types.h"
 13#include "xe_gt_printk.h"
 14#include "xe_platform_types.h"
 15#include "xe_reg_sr.h"
 16#include "xe_rtp.h"
 17#include "xe_step.h"
 18
 19#undef XE_REG_MCR
 20#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 21
 22static bool match_not_render(const struct xe_device *xe,
 23			     const struct xe_gt *gt,
 24			     const struct xe_hw_engine *hwe)
 25{
 26	return hwe->class != XE_ENGINE_CLASS_RENDER;
 27}
 28
 29static const struct xe_rtp_entry_sr register_whitelist[] = {
 30	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
 31	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 32	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
 33				   RING_FORCE_TO_NONPRIV_ACCESS_RD |
 34				   RING_FORCE_TO_NONPRIV_RANGE_4))
 35	},
 36	{ XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
 37	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 38	  XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
 39	},
 40	{ XE_RTP_NAME("1806527549"),
 41	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
 42	  XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
 43	},
 44	{ XE_RTP_NAME("allow_read_ctx_timestamp"),
 45	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
 46	  XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
 47				RING_FORCE_TO_NONPRIV_ACCESS_RD,
 48				XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 49	},
 50	{ XE_RTP_NAME("16014440446"),
 51	  XE_RTP_RULES(PLATFORM(PVC)),
 52	  XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
 53				   RING_FORCE_TO_NONPRIV_DENY |
 54				   RING_FORCE_TO_NONPRIV_RANGE_64),
 55			 WHITELIST(XE_REG(0x4500),
 56				   RING_FORCE_TO_NONPRIV_DENY |
 57				   RING_FORCE_TO_NONPRIV_RANGE_64))
 58	},
 59	{ XE_RTP_NAME("16017236439"),
 60	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),
 61	  XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
 62				   RING_FORCE_TO_NONPRIV_DENY,
 63				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 64	},
 65	{ XE_RTP_NAME("16020183090"),
 66	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
 67		       ENGINE_CLASS(RENDER)),
 68	  XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
 69	},
 70	{ XE_RTP_NAME("oa_reg_render"),
 71	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
 72		       ENGINE_CLASS(RENDER)),
 73	  XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
 74				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
 75			 WHITELIST(OAG_OASTATUS,
 76				   RING_FORCE_TO_NONPRIV_ACCESS_RD),
 77			 WHITELIST(OAG_OAHEADPTR,
 78				   RING_FORCE_TO_NONPRIV_ACCESS_RD |
 79				   RING_FORCE_TO_NONPRIV_RANGE_4))
 80	},
 81	{ XE_RTP_NAME("oa_reg_compute"),
 82	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
 83		       ENGINE_CLASS(COMPUTE)),
 84	  XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
 85				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
 86			 WHITELIST(OAG_OASTATUS,
 87				   RING_FORCE_TO_NONPRIV_ACCESS_RD),
 88			 WHITELIST(OAG_OAHEADPTR,
 89				   RING_FORCE_TO_NONPRIV_ACCESS_RD |
 90				   RING_FORCE_TO_NONPRIV_RANGE_4))
 91	},
 92	{ XE_RTP_NAME("14024997852"),
 93	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
 94	  XE_RTP_ACTIONS(WHITELIST(FF_MODE,
 95				   RING_FORCE_TO_NONPRIV_ACCESS_RW),
 96			 WHITELIST(VFLSKPD,
 97				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
 98	},
 99};
100
101static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
102{
103	struct xe_reg_sr *sr = &hwe->reg_whitelist;
104	struct xe_reg_sr_entry *entry;
105	struct drm_printer p;
106	unsigned long reg;
107	unsigned int slot;
108
109	xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name);
110	p = xe_gt_dbg_printer(hwe->gt);
111
112	slot = 0;
113	xa_for_each(&sr->xa, reg, entry) {
114		struct xe_reg_sr_entry hwe_entry = {
115			.reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot),
116			.set_bits = entry->reg.addr | entry->set_bits,
117			.clr_bits = ~0u,
118			.read_mask = entry->read_mask,
119		};
120
121		if (slot == RING_MAX_NONPRIV_SLOTS) {
122			xe_gt_err(hwe->gt,
123				  "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n",
124				  hwe->name, RING_MAX_NONPRIV_SLOTS);
125			break;
126		}
127
128		xe_reg_whitelist_print_entry(&p, 0, reg, entry);
129		xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt);
130
131		slot++;
132	}
133}
134
135/**
136 * xe_reg_whitelist_process_engine - process table of registers to whitelist
137 * @hwe: engine instance to process whitelist for
138 *
139 * Process wwhitelist table for this platform, saving in @hwe all the
140 * registers that need to be whitelisted by the hardware so they can be accessed
141 * by userspace.
142 */
143void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
144{
145	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
146
147	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
148			     &hwe->reg_whitelist);
149	whitelist_apply_to_hwe(hwe);
150}
151
152/**
153 * xe_reg_whitelist_print_entry - print one whitelist entry
154 * @p: DRM printer
155 * @indent: indent level
156 * @reg: register allowed/denied
157 * @entry: save-restore entry
158 *
159 * Print details about the entry added to allow/deny access
160 */
161void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
162				  u32 reg, struct xe_reg_sr_entry *entry)
163{
164	u32 val = entry->set_bits;
165	const char *access_str = "(invalid)";
166	unsigned int range_bit = 2;
167	u32 range_start, range_end;
168	bool deny;
169
170	deny = val & RING_FORCE_TO_NONPRIV_DENY;
171
172	switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
173	case RING_FORCE_TO_NONPRIV_RANGE_4:
174		range_bit = 4;
175		break;
176	case RING_FORCE_TO_NONPRIV_RANGE_16:
177		range_bit = 6;
178		break;
179	case RING_FORCE_TO_NONPRIV_RANGE_64:
180		range_bit = 8;
181		break;
182	}
183
184	range_start = reg & REG_GENMASK(25, range_bit);
185	range_end = range_start | REG_GENMASK(range_bit, 0);
186
187	switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
188	case RING_FORCE_TO_NONPRIV_ACCESS_RW:
189		access_str = "rw";
190		break;
191	case RING_FORCE_TO_NONPRIV_ACCESS_RD:
192		access_str = "read";
193		break;
194	case RING_FORCE_TO_NONPRIV_ACCESS_WR:
195		access_str = "write";
196		break;
197	}
198
199	drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
200			  range_start, range_end,
201			  deny ? "deny" : "allow",
202			  access_str);
203}
204
205/**
206 * xe_reg_whitelist_dump - print all whitelist entries
207 * @sr: Save/restore entries
208 * @p: DRM printer
209 */
210void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
211{
212	struct xe_reg_sr_entry *entry;
213	unsigned long reg;
214
215	if (!sr->name || xa_empty(&sr->xa))
216		return;
217
218	drm_printf(p, "%s\n", sr->name);
219	xa_for_each(&sr->xa, reg, entry)
220		xe_reg_whitelist_print_entry(p, 1, reg, entry);
221}