xe_pcode_api.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2022 Intel Corporation
 4 */
 5
 6/* Internal to xe_pcode */
 7
 8#include "regs/xe_reg_defs.h"
 9
10#define PCODE_MAILBOX			XE_REG(0x138124)
11#define   PCODE_READY			REG_BIT(31)
12#define   PCODE_MB_PARAM2		REG_GENMASK(23, 16)
13#define   PCODE_MB_PARAM1		REG_GENMASK(15, 8)
14#define   PCODE_MB_COMMAND		REG_GENMASK(7, 0)
15#define   PCODE_ERROR_MASK		0xFF
16#define     PCODE_SUCCESS		0x0
17#define     PCODE_ILLEGAL_CMD		0x1
18#define     PCODE_TIMEOUT		0x2
19#define     PCODE_ILLEGAL_DATA		0x3
20#define     PCODE_ILLEGAL_SUBCOMMAND	0x4
21#define     PCODE_LOCKED		0x6
22#define     PCODE_GT_RATIO_OUT_OF_RANGE	0x10
23#define     PCODE_REJECTED		0x11
24
25#define PCODE_DATA0			XE_REG(0x138128)
26#define PCODE_DATA1			XE_REG(0x13812C)
27
28/* Min Freq QOS Table */
29#define   PCODE_WRITE_MIN_FREQ_TABLE	0x8
30#define   PCODE_READ_MIN_FREQ_TABLE	0x9
31#define   PCODE_FREQ_RING_RATIO_SHIFT	16
32
33/* PCODE Init */
34#define   DGFX_PCODE_STATUS		0x7E
35#define     DGFX_GET_INIT_STATUS	0x0
36#define     DGFX_INIT_STATUS_COMPLETE	0x1
37#define     DGFX_LINK_DOWNGRADE_STATUS	REG_BIT(31)
38
39#define   PCODE_POWER_SETUP			0x7C
40#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
41#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
42#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
43#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
44#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
45
46#define	READ_PSYSGPU_POWER_LIMIT		0x6
47#define	WRITE_PSYSGPU_POWER_LIMIT		0x7
48#define	READ_PACKAGE_POWER_LIMIT		0x8
49#define	WRITE_PACKAGE_POWER_LIMIT		0x9
50#define	READ_PL_FROM_FW				0x1
51#define	READ_PL_FROM_PCODE			0x0
52
53#define   PCODE_LATE_BINDING			0x5C
54#define     GET_CAPABILITY_STATUS		0x0
55#define       V1_FAN_SUPPORTED			REG_BIT(0)
56#define       VR_PARAMS_SUPPORTED		REG_BIT(3)
57#define       V1_FAN_PROVISIONED		REG_BIT(16)
58#define       VR_PARAMS_PROVISIONED		REG_BIT(19)
59#define     GET_VERSION_LOW			0x1
60#define     GET_VERSION_HIGH			0x2
61#define       MAJOR_VERSION_MASK		REG_GENMASK(31, 16)
62#define       MINOR_VERSION_MASK		REG_GENMASK(15, 0)
63#define       HOTFIX_VERSION_MASK		REG_GENMASK(31, 16)
64#define       BUILD_VERSION_MASK		REG_GENMASK(15, 0)
65#define       FAN_TABLE				1
66#define       VR_CONFIG				2
67
68#define   PCODE_FREQUENCY_CONFIG		0x6e
69/* Frequency Config Sub Commands (param1) */
70#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
71#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
72/* Domain IDs (param2) */
73#define     PCODE_MBOX_DOMAIN_HBM		0x2
74
75#define   FAN_SPEED_CONTROL			0x7D
76#define     FSC_READ_NUM_FANS			0x4
77
78#define PCODE_SCRATCH(x)		XE_REG(0x138320 + ((x) * 4))
79/* PCODE_SCRATCH0 */
80#define   AUXINFO_REG_OFFSET		REG_GENMASK(17, 15)
81#define   OVERFLOW_REG_OFFSET		REG_GENMASK(14, 12)
82#define   HISTORY_TRACKING		REG_BIT(11)
83#define   OVERFLOW_SUPPORT		REG_BIT(10)
84#define   AUXINFO_SUPPORT		REG_BIT(9)
85#define   BOOT_STATUS			REG_GENMASK(3, 1)
86#define      CRITICAL_FAILURE		4
87#define      NON_CRITICAL_FAILURE	7
88
89/* Auxiliary info bits */
90#define   AUXINFO_HISTORY_OFFSET	REG_GENMASK(31, 29)
91
92#define BMG_PCIE_CAP			XE_REG(0x138340)
93#define   LINK_DOWNGRADE		REG_GENMASK(1, 0)
94#define     DOWNGRADE_CAPABLE		2