xe_pci_types.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2023 Intel Corporation
 4 */
 5
 6#ifndef _XE_PCI_TYPES_H_
 7#define _XE_PCI_TYPES_H_
 8
 9#include <linux/types.h>
10
11#include "xe_platform_types.h"
12
13struct xe_subplatform_desc {
14	enum xe_subplatform subplatform;
15	const char *name;
16	const u16 *pciidlist;
17};
18
19struct xe_device_desc {
20	/* Should only ever be set for platforms without GMD_ID */
21	const struct xe_ip *pre_gmdid_graphics_ip;
22	/* Should only ever be set for platforms without GMD_ID */
23	const struct xe_ip *pre_gmdid_media_ip;
24
25	const char *platform_name;
26	const struct xe_subplatform_desc *subplatforms;
27
28	enum xe_platform platform;
29
30	u8 dma_mask_size;
31	u8 max_remote_tiles:2;
32	u8 max_gt_per_tile:2;
33	u8 va_bits;
34	u8 vm_max_level;
35	u8 vram_flags;
36
37	u8 require_force_probe:1;
38	u8 is_dgfx:1;
39
40	u8 has_display:1;
41	u8 has_fan_control:1;
42	u8 has_flat_ccs:1;
43	u8 has_gsc_nvm:1;
44	u8 has_heci_gscfi:1;
45	u8 has_heci_cscfi:1;
46	u8 has_late_bind:1;
47	u8 has_llc:1;
48	u8 has_mbx_power_limits:1;
49	u8 has_pxp:1;
50	u8 has_sriov:1;
51	u8 needs_scratch:1;
52	u8 skip_guc_pc:1;
53	u8 skip_mtcfg:1;
54	u8 skip_pcode:1;
55	u8 needs_shared_vf_gt_wq:1;
56};
57
58struct xe_graphics_desc {
59	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */
60
61	u8 has_asid:1;
62	u8 has_atomic_enable_pte_bit:1;
63	u8 has_indirect_ring_state:1;
64	u8 has_range_tlb_inval:1;
65	u8 has_usm:1;
66	u8 has_64bit_timestamp:1;
67};
68
69struct xe_media_desc {
70	u64 hw_engine_mask;	/* hardware engines provided by media IP */
71
72	u8 has_indirect_ring_state:1;
73};
74
75struct xe_ip {
76	unsigned int verx100;
77	const char *name;
78	const void *desc;
79};
80
81#endif