xe_pci.c

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2021 Intel Corporation
   4 */
   5
   6#include "xe_pci.h"
   7
   8#include <kunit/static_stub.h>
   9#include <linux/device/driver.h>
  10#include <linux/module.h>
  11#include <linux/pci.h>
  12#include <linux/pm_runtime.h>
  13
  14#include <drm/drm_color_mgmt.h>
  15#include <drm/drm_drv.h>
  16#include <drm/intel/pciids.h>
  17
  18#include "display/xe_display.h"
  19#include "regs/xe_gt_regs.h"
  20#include "regs/xe_regs.h"
  21#include "xe_configfs.h"
  22#include "xe_device.h"
  23#include "xe_drv.h"
  24#include "xe_gt.h"
  25#include "xe_gt_sriov_vf.h"
  26#include "xe_guc.h"
  27#include "xe_macros.h"
  28#include "xe_mmio.h"
  29#include "xe_module.h"
  30#include "xe_pci_sriov.h"
  31#include "xe_pci_types.h"
  32#include "xe_pm.h"
  33#include "xe_printk.h"
  34#include "xe_sriov.h"
  35#include "xe_step.h"
  36#include "xe_survivability_mode.h"
  37#include "xe_tile.h"
  38
  39enum toggle_d3cold {
  40	D3COLD_DISABLE,
  41	D3COLD_ENABLE,
  42};
  43
  44__diag_push();
  45__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
  46
  47#define PLATFORM(x)		\
  48	.platform = XE_##x,	\
  49	.platform_name = #x
  50
  51#define NOP(x)	x
  52
  53static const struct xe_graphics_desc graphics_xelp = {
  54	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
  55};
  56
  57#define XE_HP_FEATURES \
  58	.has_range_tlb_inval = true
  59
  60static const struct xe_graphics_desc graphics_xehpg = {
  61	.hw_engine_mask =
  62		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
  63		BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
  64		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
  65
  66	XE_HP_FEATURES,
  67};
  68
  69static const struct xe_graphics_desc graphics_xehpc = {
  70	.hw_engine_mask =
  71		BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
  72		BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
  73		BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
  74		BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
  75		BIT(XE_HW_ENGINE_BCS8) |
  76		BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
  77		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
  78
  79	XE_HP_FEATURES,
  80
  81	.has_asid = 1,
  82	.has_atomic_enable_pte_bit = 1,
  83	.has_usm = 1,
  84};
  85
  86static const struct xe_graphics_desc graphics_xelpg = {
  87	.hw_engine_mask =
  88		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
  89		BIT(XE_HW_ENGINE_CCS0),
  90
  91	XE_HP_FEATURES,
  92};
  93
  94#define XE2_GFX_FEATURES \
  95	.has_asid = 1, \
  96	.has_atomic_enable_pte_bit = 1, \
  97	.has_range_tlb_inval = 1, \
  98	.has_usm = 1, \
  99	.has_64bit_timestamp = 1, \
 100	.hw_engine_mask = \
 101		BIT(XE_HW_ENGINE_RCS0) | \
 102		BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
 103		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
 104
 105static const struct xe_graphics_desc graphics_xe2 = {
 106	XE2_GFX_FEATURES,
 107};
 108
 109static const struct xe_graphics_desc graphics_xe3p_xpc = {
 110	XE2_GFX_FEATURES,
 111	.hw_engine_mask =
 112		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
 113		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
 114};
 115
 116static const struct xe_media_desc media_xem = {
 117	.hw_engine_mask =
 118		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
 119		GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
 120};
 121
 122static const struct xe_media_desc media_xelpmp = {
 123	.hw_engine_mask =
 124		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
 125		GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
 126		BIT(XE_HW_ENGINE_GSCCS0)
 127};
 128
 129/* Pre-GMDID Graphics IPs */
 130static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp };
 131static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp };
 132static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg };
 133static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc };
 134
 135/* GMDID-based Graphics IPs */
 136static const struct xe_ip graphics_ips[] = {
 137	{ 1270, "Xe_LPG", &graphics_xelpg },
 138	{ 1271, "Xe_LPG", &graphics_xelpg },
 139	{ 1274, "Xe_LPG+", &graphics_xelpg },
 140	{ 2001, "Xe2_HPG", &graphics_xe2 },
 141	{ 2002, "Xe2_HPG", &graphics_xe2 },
 142	{ 2004, "Xe2_LPG", &graphics_xe2 },
 143	{ 3000, "Xe3_LPG", &graphics_xe2 },
 144	{ 3001, "Xe3_LPG", &graphics_xe2 },
 145	{ 3003, "Xe3_LPG", &graphics_xe2 },
 146	{ 3004, "Xe3_LPG", &graphics_xe2 },
 147	{ 3005, "Xe3_LPG", &graphics_xe2 },
 148	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
 149};
 150
 151/* Pre-GMDID Media IPs */
 152static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem };
 153static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem };
 154
 155/* GMDID-based Media IPs */
 156static const struct xe_ip media_ips[] = {
 157	{ 1300, "Xe_LPM+", &media_xelpmp },
 158	{ 1301, "Xe2_HPM", &media_xelpmp },
 159	{ 2000, "Xe2_LPM", &media_xelpmp },
 160	{ 3000, "Xe3_LPM", &media_xelpmp },
 161	{ 3002, "Xe3_LPM", &media_xelpmp },
 162	{ 3500, "Xe3p_LPM", &media_xelpmp },
 163	{ 3503, "Xe3p_HPM", &media_xelpmp },
 164};
 165
 166static const struct xe_device_desc tgl_desc = {
 167	.pre_gmdid_graphics_ip = &graphics_ip_xelp,
 168	.pre_gmdid_media_ip = &media_ip_xem,
 169	PLATFORM(TIGERLAKE),
 170	.dma_mask_size = 39,
 171	.has_display = true,
 172	.has_llc = true,
 173	.has_sriov = true,
 174	.max_gt_per_tile = 1,
 175	.require_force_probe = true,
 176	.va_bits = 48,
 177	.vm_max_level = 3,
 178};
 179
 180static const struct xe_device_desc rkl_desc = {
 181	.pre_gmdid_graphics_ip = &graphics_ip_xelp,
 182	.pre_gmdid_media_ip = &media_ip_xem,
 183	PLATFORM(ROCKETLAKE),
 184	.dma_mask_size = 39,
 185	.has_display = true,
 186	.has_llc = true,
 187	.max_gt_per_tile = 1,
 188	.require_force_probe = true,
 189	.va_bits = 48,
 190	.vm_max_level = 3,
 191};
 192
 193static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
 194
 195static const struct xe_device_desc adl_s_desc = {
 196	.pre_gmdid_graphics_ip = &graphics_ip_xelp,
 197	.pre_gmdid_media_ip = &media_ip_xem,
 198	PLATFORM(ALDERLAKE_S),
 199	.dma_mask_size = 39,
 200	.has_display = true,
 201	.has_llc = true,
 202	.has_sriov = true,
 203	.max_gt_per_tile = 1,
 204	.require_force_probe = true,
 205	.subplatforms = (const struct xe_subplatform_desc[]) {
 206		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
 207		{},
 208	},
 209	.va_bits = 48,
 210	.vm_max_level = 3,
 211};
 212
 213static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
 214
 215static const struct xe_device_desc adl_p_desc = {
 216	.pre_gmdid_graphics_ip = &graphics_ip_xelp,
 217	.pre_gmdid_media_ip = &media_ip_xem,
 218	PLATFORM(ALDERLAKE_P),
 219	.dma_mask_size = 39,
 220	.has_display = true,
 221	.has_llc = true,
 222	.has_sriov = true,
 223	.max_gt_per_tile = 1,
 224	.require_force_probe = true,
 225	.subplatforms = (const struct xe_subplatform_desc[]) {
 226		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
 227		{},
 228	},
 229	.va_bits = 48,
 230	.vm_max_level = 3,
 231};
 232
 233static const struct xe_device_desc adl_n_desc = {
 234	.pre_gmdid_graphics_ip = &graphics_ip_xelp,
 235	.pre_gmdid_media_ip = &media_ip_xem,
 236	PLATFORM(ALDERLAKE_N),
 237	.dma_mask_size = 39,
 238	.has_display = true,
 239	.has_llc = true,
 240	.has_sriov = true,
 241	.max_gt_per_tile = 1,
 242	.require_force_probe = true,
 243	.va_bits = 48,
 244	.vm_max_level = 3,
 245};
 246
 247#define DGFX_FEATURES \
 248	.is_dgfx = 1
 249
 250static const struct xe_device_desc dg1_desc = {
 251	.pre_gmdid_graphics_ip = &graphics_ip_xelpp,
 252	.pre_gmdid_media_ip = &media_ip_xem,
 253	DGFX_FEATURES,
 254	PLATFORM(DG1),
 255	.dma_mask_size = 39,
 256	.has_display = true,
 257	.has_gsc_nvm = 1,
 258	.has_heci_gscfi = 1,
 259	.max_gt_per_tile = 1,
 260	.require_force_probe = true,
 261	.va_bits = 48,
 262	.vm_max_level = 3,
 263};
 264
 265static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
 266static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
 267static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 268
 269#define DG2_FEATURES \
 270	DGFX_FEATURES, \
 271	PLATFORM(DG2), \
 272	.has_flat_ccs = 1, \
 273	.has_gsc_nvm = 1, \
 274	.has_heci_gscfi = 1, \
 275	.subplatforms = (const struct xe_subplatform_desc[]) { \
 276		{ XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
 277		{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
 278		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
 279		{ } \
 280	}, \
 281	.va_bits = 48, \
 282	.vm_max_level = 3, \
 283	.vram_flags = XE_VRAM_FLAGS_NEED64K
 284
 285static const struct xe_device_desc ats_m_desc = {
 286	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
 287	.pre_gmdid_media_ip = &media_ip_xehpm,
 288	.dma_mask_size = 46,
 289	.max_gt_per_tile = 1,
 290	.require_force_probe = true,
 291
 292	DG2_FEATURES,
 293	.has_display = false,
 294	.has_sriov = true,
 295};
 296
 297static const struct xe_device_desc dg2_desc = {
 298	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
 299	.pre_gmdid_media_ip = &media_ip_xehpm,
 300	.dma_mask_size = 46,
 301	.max_gt_per_tile = 1,
 302	.require_force_probe = true,
 303
 304	DG2_FEATURES,
 305	.has_display = true,
 306	.has_fan_control = true,
 307	.has_mbx_power_limits = false,
 308};
 309
 310static const __maybe_unused struct xe_device_desc pvc_desc = {
 311	.pre_gmdid_graphics_ip = &graphics_ip_xehpc,
 312	DGFX_FEATURES,
 313	PLATFORM(PVC),
 314	.dma_mask_size = 52,
 315	.has_display = false,
 316	.has_gsc_nvm = 1,
 317	.has_heci_gscfi = 1,
 318	.max_gt_per_tile = 1,
 319	.max_remote_tiles = 1,
 320	.require_force_probe = true,
 321	.va_bits = 57,
 322	.vm_max_level = 4,
 323	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 324	.has_mbx_power_limits = false,
 325};
 326
 327static const struct xe_device_desc mtl_desc = {
 328	/* .graphics and .media determined via GMD_ID */
 329	.require_force_probe = true,
 330	PLATFORM(METEORLAKE),
 331	.dma_mask_size = 46,
 332	.has_display = true,
 333	.has_pxp = true,
 334	.max_gt_per_tile = 2,
 335	.va_bits = 48,
 336	.vm_max_level = 3,
 337};
 338
 339static const struct xe_device_desc lnl_desc = {
 340	PLATFORM(LUNARLAKE),
 341	.dma_mask_size = 46,
 342	.has_display = true,
 343	.has_flat_ccs = 1,
 344	.has_pxp = true,
 345	.max_gt_per_tile = 2,
 346	.needs_scratch = true,
 347	.va_bits = 48,
 348	.vm_max_level = 4,
 349};
 350
 351static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
 352
 353static const struct xe_device_desc bmg_desc = {
 354	DGFX_FEATURES,
 355	PLATFORM(BATTLEMAGE),
 356	.dma_mask_size = 46,
 357	.has_display = true,
 358	.has_fan_control = true,
 359	.has_flat_ccs = 1,
 360	.has_mbx_power_limits = true,
 361	.has_gsc_nvm = 1,
 362	.has_heci_cscfi = 1,
 363	.has_late_bind = true,
 364	.has_sriov = true,
 365	.max_gt_per_tile = 2,
 366	.needs_scratch = true,
 367	.subplatforms = (const struct xe_subplatform_desc[]) {
 368		{ XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
 369		{ }
 370	},
 371	.va_bits = 48,
 372	.vm_max_level = 4,
 373};
 374
 375static const struct xe_device_desc ptl_desc = {
 376	PLATFORM(PANTHERLAKE),
 377	.dma_mask_size = 46,
 378	.has_display = true,
 379	.has_flat_ccs = 1,
 380	.has_sriov = true,
 381	.max_gt_per_tile = 2,
 382	.needs_scratch = true,
 383	.needs_shared_vf_gt_wq = true,
 384	.va_bits = 48,
 385	.vm_max_level = 4,
 386};
 387
 388static const struct xe_device_desc nvls_desc = {
 389	PLATFORM(NOVALAKE_S),
 390	.dma_mask_size = 46,
 391	.has_display = true,
 392	.has_flat_ccs = 1,
 393	.max_gt_per_tile = 2,
 394	.require_force_probe = true,
 395	.va_bits = 48,
 396	.vm_max_level = 4,
 397};
 398
 399static const struct xe_device_desc cri_desc = {
 400	DGFX_FEATURES,
 401	PLATFORM(CRESCENTISLAND),
 402	.dma_mask_size = 52,
 403	.has_display = false,
 404	.has_flat_ccs = false,
 405	.has_mbx_power_limits = true,
 406	.has_sriov = true,
 407	.max_gt_per_tile = 2,
 408	.require_force_probe = true,
 409	.va_bits = 57,
 410	.vm_max_level = 4,
 411};
 412
 413#undef PLATFORM
 414__diag_pop();
 415
 416/*
 417 * Make sure any device matches here are from most specific to most
 418 * general.  For example, since the Quanta match is based on the subsystem
 419 * and subvendor IDs, we need it to come before the more general IVB
 420 * PCI ID matches, otherwise we'll use the wrong info struct above.
 421 */
 422static const struct pci_device_id pciidlist[] = {
 423	INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
 424	INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
 425	INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
 426	INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
 427	INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
 428	INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
 429	INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
 430	INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
 431	INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
 432	INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
 433	INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
 434	INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
 435	INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
 436	INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
 437	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
 438	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 439	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 440	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 441	INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
 442	{ }
 443};
 444MODULE_DEVICE_TABLE(pci, pciidlist);
 445
 446/* is device_id present in comma separated list of ids */
 447static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
 448{
 449	char *s, *p, *tok;
 450	bool ret;
 451
 452	if (!devices || !*devices)
 453		return false;
 454
 455	/* match everything */
 456	if (negative && strcmp(devices, "!*") == 0)
 457		return true;
 458	if (!negative && strcmp(devices, "*") == 0)
 459		return true;
 460
 461	s = kstrdup(devices, GFP_KERNEL);
 462	if (!s)
 463		return false;
 464
 465	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
 466		u16 val;
 467
 468		if (negative && tok[0] == '!')
 469			tok++;
 470		else if ((negative && tok[0] != '!') ||
 471			 (!negative && tok[0] == '!'))
 472			continue;
 473
 474		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
 475			ret = true;
 476			break;
 477		}
 478	}
 479
 480	kfree(s);
 481
 482	return ret;
 483}
 484
 485static bool id_forced(u16 device_id)
 486{
 487	return device_id_in_list(device_id, xe_modparam.force_probe, false);
 488}
 489
 490static bool id_blocked(u16 device_id)
 491{
 492	return device_id_in_list(device_id, xe_modparam.force_probe, true);
 493}
 494
 495static const struct xe_subplatform_desc *
 496find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
 497{
 498	const struct xe_subplatform_desc *sp;
 499	const u16 *id;
 500
 501	for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
 502		for (id = sp->pciidlist; *id; id++)
 503			if (*id == xe->info.devid)
 504				return sp;
 505
 506	return NULL;
 507}
 508
 509enum xe_gmdid_type {
 510	GMDID_GRAPHICS,
 511	GMDID_MEDIA
 512};
 513
 514static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
 515{
 516	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
 517	struct xe_reg gmdid_reg = GMD_ID;
 518	u32 val;
 519
 520	KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
 521
 522	if (IS_SRIOV_VF(xe)) {
 523		/*
 524		 * To get the value of the GMDID register, VFs must obtain it
 525		 * from the GuC using MMIO communication.
 526		 *
 527		 * Note that at this point the GTs are not initialized and only
 528		 * tile-level access to MMIO registers is possible. To use our
 529		 * existing GuC communication functions we must create a dummy
 530		 * GT structure and perform at least basic xe_gt and xe_guc
 531		 * initialization.
 532		 */
 533		struct xe_gt *gt __free(kfree) = NULL;
 534		int err;
 535
 536		/* Don't try to read media ver if media GT is not allowed */
 537		if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
 538			*ver = *revid = 0;
 539			return 0;
 540		}
 541
 542		gt = kzalloc(sizeof(*gt), GFP_KERNEL);
 543		if (!gt)
 544			return -ENOMEM;
 545
 546		gt->tile = &xe->tiles[0];
 547		if (type == GMDID_MEDIA) {
 548			gt->info.id = 1;
 549			gt->info.type = XE_GT_TYPE_MEDIA;
 550		} else {
 551			gt->info.id = 0;
 552			gt->info.type = XE_GT_TYPE_MAIN;
 553		}
 554
 555		xe_gt_mmio_init(gt);
 556		xe_guc_comm_init_early(&gt->uc.guc);
 557
 558		err = xe_gt_sriov_vf_bootstrap(gt);
 559		if (err)
 560			return err;
 561
 562		val = xe_gt_sriov_vf_gmdid(gt);
 563	} else {
 564		/*
 565		 * GMD_ID is a GT register, but at this point in the driver
 566		 * init we haven't fully initialized the GT yet so we need to
 567		 * read the register with the tile's MMIO accessor.  That means
 568		 * we need to apply the GSI offset manually since it won't get
 569		 * automatically added as it would if we were using a GT mmio
 570		 * accessor.
 571		 */
 572		if (type == GMDID_MEDIA)
 573			gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
 574
 575		val = xe_mmio_read32(mmio, gmdid_reg);
 576	}
 577
 578	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
 579	*revid = REG_FIELD_GET(GMD_ID_REVID, val);
 580
 581	return 0;
 582}
 583
 584static const struct xe_ip *find_graphics_ip(unsigned int verx100)
 585{
 586	KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100);
 587
 588	for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++)
 589		if (graphics_ips[i].verx100 == verx100)
 590			return &graphics_ips[i];
 591	return NULL;
 592}
 593
 594static const struct xe_ip *find_media_ip(unsigned int verx100)
 595{
 596	KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100);
 597
 598	for (int i = 0; i < ARRAY_SIZE(media_ips); i++)
 599		if (media_ips[i].verx100 == verx100)
 600			return &media_ips[i];
 601	return NULL;
 602}
 603
 604/*
 605 * Read IP version from hardware and select graphics/media IP descriptors
 606 * based on the result.
 607 */
 608static int handle_gmdid(struct xe_device *xe,
 609			const struct xe_ip **graphics_ip,
 610			const struct xe_ip **media_ip,
 611			u32 *graphics_revid,
 612			u32 *media_revid)
 613{
 614	u32 ver;
 615	int ret;
 616
 617	*graphics_ip = NULL;
 618	*media_ip = NULL;
 619
 620	ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
 621	if (ret)
 622		return ret;
 623
 624	*graphics_ip = find_graphics_ip(ver);
 625	if (!*graphics_ip) {
 626		drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
 627			ver / 100, ver % 100);
 628	}
 629
 630	ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
 631	if (ret)
 632		return ret;
 633
 634	/* Media may legitimately be fused off / not present */
 635	if (ver == 0)
 636		return 0;
 637
 638	*media_ip = find_media_ip(ver);
 639	if (!*media_ip) {
 640		drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
 641			ver / 100, ver % 100);
 642	}
 643
 644	return 0;
 645}
 646
 647/*
 648 * Initialize device info content that only depends on static driver_data
 649 * passed to the driver at probe time from PCI ID table.
 650 */
 651static int xe_info_init_early(struct xe_device *xe,
 652			      const struct xe_device_desc *desc,
 653			      const struct xe_subplatform_desc *subplatform_desc)
 654{
 655	int err;
 656
 657	xe->info.platform_name = desc->platform_name;
 658	xe->info.platform = desc->platform;
 659	xe->info.subplatform = subplatform_desc ?
 660		subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
 661
 662	xe->info.dma_mask_size = desc->dma_mask_size;
 663	xe->info.va_bits = desc->va_bits;
 664	xe->info.vm_max_level = desc->vm_max_level;
 665	xe->info.vram_flags = desc->vram_flags;
 666
 667	xe->info.is_dgfx = desc->is_dgfx;
 668	xe->info.has_fan_control = desc->has_fan_control;
 669	/* runtime fusing may force flat_ccs to disabled later */
 670	xe->info.has_flat_ccs = desc->has_flat_ccs;
 671	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
 672	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 673	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
 674	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
 675	xe->info.has_late_bind = desc->has_late_bind;
 676	xe->info.has_llc = desc->has_llc;
 677	xe->info.has_pxp = desc->has_pxp;
 678	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 679		desc->has_sriov;
 680	xe->info.skip_guc_pc = desc->skip_guc_pc;
 681	xe->info.skip_mtcfg = desc->skip_mtcfg;
 682	xe->info.skip_pcode = desc->skip_pcode;
 683	xe->info.needs_scratch = desc->needs_scratch;
 684	xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
 685
 686	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
 687				 xe_modparam.probe_display &&
 688				 desc->has_display;
 689
 690	xe_assert(xe, desc->max_gt_per_tile > 0);
 691	xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
 692	xe->info.max_gt_per_tile = desc->max_gt_per_tile;
 693	xe->info.tile_count = 1 + desc->max_remote_tiles;
 694
 695	err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
 696	if (err)
 697		return err;
 698
 699	return 0;
 700}
 701
 702/*
 703 * Possibly override number of tile based on configuration register.
 704 */
 705static void xe_info_probe_tile_count(struct xe_device *xe)
 706{
 707	struct xe_mmio *mmio;
 708	u8 tile_count;
 709	u32 mtcfg;
 710
 711	KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe);
 712
 713	/*
 714	 * Probe for tile count only for platforms that support multiple
 715	 * tiles.
 716	 */
 717	if (xe->info.tile_count == 1)
 718		return;
 719
 720	if (xe->info.skip_mtcfg)
 721		return;
 722
 723	mmio = xe_root_tile_mmio(xe);
 724
 725	/*
 726	 * Although the per-tile mmio regs are not yet initialized, this
 727	 * is fine as it's going to the root tile's mmio, that's
 728	 * guaranteed to be initialized earlier in xe_mmio_probe_early()
 729	 */
 730	mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);
 731	tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
 732
 733	if (tile_count < xe->info.tile_count) {
 734		drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
 735			 xe->info.tile_count, tile_count);
 736		xe->info.tile_count = tile_count;
 737	}
 738}
 739
 740static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
 741				      const struct xe_graphics_desc *graphics_desc,
 742				      const struct xe_media_desc *media_desc)
 743{
 744	struct xe_device *xe = tile_to_xe(tile);
 745	struct xe_gt *gt;
 746
 747	if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) {
 748		xe_info(xe, "Primary GT disabled via configfs\n");
 749		return NULL;
 750	}
 751
 752	gt = xe_gt_alloc(tile);
 753	if (IS_ERR(gt))
 754		return gt;
 755
 756	gt->info.type = XE_GT_TYPE_MAIN;
 757	gt->info.id = tile->id * xe->info.max_gt_per_tile;
 758	gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
 759	gt->info.engine_mask = graphics_desc->hw_engine_mask;
 760
 761	/*
 762	 * Before media version 13, the media IP was part of the primary GT
 763	 * so we need to add the media engines to the primary GT's engine list.
 764	 */
 765	if (MEDIA_VER(xe) < 13 && media_desc)
 766		gt->info.engine_mask |= media_desc->hw_engine_mask;
 767
 768	return gt;
 769}
 770
 771static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
 772				    const struct xe_media_desc *media_desc)
 773{
 774	struct xe_device *xe = tile_to_xe(tile);
 775	struct xe_gt *gt;
 776
 777	if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
 778		xe_info(xe, "Media GT disabled via configfs\n");
 779		return NULL;
 780	}
 781
 782	if (MEDIA_VER(xe) < 13 || !media_desc)
 783		return NULL;
 784
 785	gt = xe_gt_alloc(tile);
 786	if (IS_ERR(gt))
 787		return gt;
 788
 789	gt->info.type = XE_GT_TYPE_MEDIA;
 790	gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
 791	gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
 792	gt->info.engine_mask = media_desc->hw_engine_mask;
 793
 794	return gt;
 795}
 796
 797/*
 798 * Initialize device info content that does require knowledge about
 799 * graphics / media IP version.
 800 * Make sure that GT / tile structures allocated by the driver match the data
 801 * present in device info.
 802 */
 803static int xe_info_init(struct xe_device *xe,
 804			const struct xe_device_desc *desc)
 805{
 806	u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
 807	const struct xe_ip *graphics_ip;
 808	const struct xe_ip *media_ip;
 809	const struct xe_graphics_desc *graphics_desc;
 810	const struct xe_media_desc *media_desc;
 811	struct xe_tile *tile;
 812	struct xe_gt *gt;
 813	int ret;
 814	u8 id;
 815
 816	/*
 817	 * If this platform supports GMD_ID, we'll detect the proper IP
 818	 * descriptor to use from hardware registers.
 819	 * desc->pre_gmdid_graphics_ip will only ever be set at this point for
 820	 * platforms before GMD_ID. In that case the IP descriptions and
 821	 * versions are simply derived from that.
 822	 */
 823	if (desc->pre_gmdid_graphics_ip) {
 824		graphics_ip = desc->pre_gmdid_graphics_ip;
 825		media_ip = desc->pre_gmdid_media_ip;
 826		xe->info.step = xe_step_pre_gmdid_get(xe);
 827	} else {
 828		xe_assert(xe, !desc->pre_gmdid_media_ip);
 829		ret = handle_gmdid(xe, &graphics_ip, &media_ip,
 830				   &graphics_gmdid_revid, &media_gmdid_revid);
 831		if (ret)
 832			return ret;
 833
 834		xe->info.step = xe_step_gmdid_get(xe,
 835						  graphics_gmdid_revid,
 836						  media_gmdid_revid);
 837	}
 838
 839	/*
 840	 * If we couldn't detect the graphics IP, that's considered a fatal
 841	 * error and we should abort driver load.  Failing to detect media
 842	 * IP is non-fatal; we'll just proceed without enabling media support.
 843	 */
 844	if (!graphics_ip)
 845		return -ENODEV;
 846
 847	xe->info.graphics_verx100 = graphics_ip->verx100;
 848	xe->info.graphics_name = graphics_ip->name;
 849	graphics_desc = graphics_ip->desc;
 850
 851	if (media_ip) {
 852		xe->info.media_verx100 = media_ip->verx100;
 853		xe->info.media_name = media_ip->name;
 854		media_desc = media_ip->desc;
 855	} else {
 856		xe->info.media_name = "none";
 857		media_desc = NULL;
 858	}
 859
 860	xe->info.has_asid = graphics_desc->has_asid;
 861	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
 862	if (xe->info.platform != XE_PVC)
 863		xe->info.has_device_atomics_on_smem = 1;
 864
 865	xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
 866	xe->info.has_usm = graphics_desc->has_usm;
 867	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
 868	xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20;
 869
 870	xe_info_probe_tile_count(xe);
 871
 872	for_each_remote_tile(tile, xe, id) {
 873		int err;
 874
 875		err = xe_tile_init_early(tile, xe, id);
 876		if (err)
 877			return err;
 878	}
 879
 880	/* Allocate any GT and VRAM structures necessary for the platform. */
 881	for_each_tile(tile, xe, id) {
 882		int err;
 883
 884		err = xe_tile_alloc_vram(tile);
 885		if (err)
 886			return err;
 887
 888		tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
 889		if (IS_ERR(tile->primary_gt))
 890			return PTR_ERR(tile->primary_gt);
 891
 892		/*
 893		 * It's not currently possible to probe a device with the
 894		 * primary GT disabled.  With some work, this may be future in
 895		 * the possible for igpu platforms (although probably not for
 896		 * dgpu's since access to the primary GT's BCS engines is
 897		 * required for VRAM management).
 898		 */
 899		if (!tile->primary_gt) {
 900			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
 901			return -ENODEV;
 902		}
 903
 904		tile->media_gt = alloc_media_gt(tile, media_desc);
 905		if (IS_ERR(tile->media_gt))
 906			return PTR_ERR(tile->media_gt);
 907	}
 908
 909	/*
 910	 * Now that we have tiles and GTs defined, let's loop over valid GTs
 911	 * in order to define gt_count.
 912	 */
 913	for_each_gt(gt, xe, id)
 914		xe->info.gt_count++;
 915
 916	return 0;
 917}
 918
 919static void xe_pci_remove(struct pci_dev *pdev)
 920{
 921	struct xe_device *xe = pdev_to_xe_device(pdev);
 922
 923	if (IS_SRIOV_PF(xe))
 924		xe_pci_sriov_configure(pdev, 0);
 925
 926	if (xe_survivability_mode_is_boot_enabled(xe))
 927		return;
 928
 929	xe_device_remove(xe);
 930	xe_pm_fini(xe);
 931}
 932
 933/*
 934 * Probe the PCI device, initialize various parts of the driver.
 935 *
 936 * Fault injection is used to test the error paths of some initialization
 937 * functions called either directly from xe_pci_probe() or indirectly for
 938 * example through xe_device_probe(). Those functions use the kernel fault
 939 * injection capabilities infrastructure, see
 940 * Documentation/fault-injection/fault-injection.rst for details. The macro
 941 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution
 942 * at runtime and use a provided return value. The first requirement for
 943 * error injectable functions is proper handling of the error code by the
 944 * caller for recovery, which is always the case here. The second
 945 * requirement is that no state is changed before the first error return.
 946 * It is not strictly fulfilled for all initialization functions using the
 947 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those
 948 * error cases at probe time, the error code is simply propagated up by the
 949 * caller. Therefore there is no consequence on those specific callers when
 950 * function error injection skips the whole function.
 951 */
 952static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 953{
 954	const struct xe_device_desc *desc = (const void *)ent->driver_data;
 955	const struct xe_subplatform_desc *subplatform_desc;
 956	struct xe_device *xe;
 957	int err;
 958
 959	xe_configfs_check_device(pdev);
 960
 961	if (desc->require_force_probe && !id_forced(pdev->device)) {
 962		dev_info(&pdev->dev,
 963			 "Your graphics device %04x is not officially supported\n"
 964			 "by xe driver in this kernel version. To force Xe probe,\n"
 965			 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
 966			 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
 967			 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
 968			 pdev->device, pdev->device, pdev->device,
 969			 pdev->device, pdev->device);
 970		return -ENODEV;
 971	}
 972
 973	if (id_blocked(pdev->device)) {
 974		dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
 975			 pdev->vendor, pdev->device);
 976		return -ENODEV;
 977	}
 978
 979	if (xe_display_driver_probe_defer(pdev))
 980		return -EPROBE_DEFER;
 981
 982	err = pcim_enable_device(pdev);
 983	if (err)
 984		return err;
 985
 986	xe = xe_device_create(pdev, ent);
 987	if (IS_ERR(xe))
 988		return PTR_ERR(xe);
 989
 990	pci_set_drvdata(pdev, &xe->drm);
 991
 992	xe_pm_assert_unbounded_bridge(xe);
 993	subplatform_desc = find_subplatform(xe, desc);
 994
 995	pci_set_master(pdev);
 996
 997	err = xe_info_init_early(xe, desc, subplatform_desc);
 998	if (err)
 999		return err;
1000
1001	xe_vram_resize_bar(xe);
1002
1003	err = xe_device_probe_early(xe);
1004	/*
1005	 * In Boot Survivability mode, no drm card is exposed and driver
1006	 * is loaded with bare minimum to allow for firmware to be
1007	 * flashed through mei. Return success, if survivability mode
1008	 * is enabled due to pcode failure or configfs being set
1009	 */
1010	if (xe_survivability_mode_is_boot_enabled(xe))
1011		return 0;
1012
1013	if (err)
1014		return err;
1015
1016	err = xe_info_init(xe, desc);
1017	if (err)
1018		return err;
1019
1020	err = xe_display_probe(xe);
1021	if (err)
1022		return err;
1023
1024	drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
1025		desc->platform_name,
1026		subplatform_desc ? subplatform_desc->name : "",
1027		xe->info.devid, xe->info.revid,
1028		xe->info.is_dgfx,
1029		xe->info.graphics_name,
1030		xe->info.graphics_verx100 / 100,
1031		xe->info.graphics_verx100 % 100,
1032		xe->info.media_name,
1033		xe->info.media_verx100 / 100,
1034		xe->info.media_verx100 % 100,
1035		str_yes_no(xe->info.probe_display),
1036		xe->info.dma_mask_size, xe->info.tile_count,
1037		xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
1038
1039	drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
1040		xe_step_name(xe->info.step.graphics),
1041		xe_step_name(xe->info.step.media),
1042		xe_step_name(xe->info.step.basedie));
1043
1044	drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
1045		str_yes_no(xe_device_has_sriov(xe)),
1046		xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
1047
1048	err = xe_pm_init_early(xe);
1049	if (err)
1050		return err;
1051
1052	err = xe_device_probe(xe);
1053	if (err)
1054		return err;
1055
1056	err = xe_pm_init(xe);
1057	if (err)
1058		goto err_driver_cleanup;
1059
1060	drm_dbg(&xe->drm, "d3cold: capable=%s\n",
1061		str_yes_no(xe->d3cold.capable));
1062
1063	return 0;
1064
1065err_driver_cleanup:
1066	xe_pci_remove(pdev);
1067	return err;
1068}
1069
1070static void xe_pci_shutdown(struct pci_dev *pdev)
1071{
1072	xe_device_shutdown(pdev_to_xe_device(pdev));
1073}
1074
1075#ifdef CONFIG_PM_SLEEP
1076static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
1077{
1078	struct xe_device *xe = pdev_to_xe_device(pdev);
1079	struct pci_dev *root_pdev;
1080
1081	if (!xe->d3cold.capable)
1082		return;
1083
1084	root_pdev = pcie_find_root_port(pdev);
1085	if (!root_pdev)
1086		return;
1087
1088	switch (toggle) {
1089	case D3COLD_DISABLE:
1090		pci_d3cold_disable(root_pdev);
1091		break;
1092	case D3COLD_ENABLE:
1093		pci_d3cold_enable(root_pdev);
1094		break;
1095	}
1096}
1097
1098static int xe_pci_suspend(struct device *dev)
1099{
1100	struct pci_dev *pdev = to_pci_dev(dev);
1101	struct xe_device *xe = pdev_to_xe_device(pdev);
1102	int err;
1103
1104	if (xe_survivability_mode_is_boot_enabled(xe))
1105		return -EBUSY;
1106
1107	err = xe_pm_suspend(xe);
1108	if (err)
1109		return err;
1110
1111	/*
1112	 * Enabling D3Cold is needed for S2Idle/S0ix.
1113	 * It is save to allow here since xe_pm_suspend has evicted
1114	 * the local memory and the direct complete optimization is disabled.
1115	 */
1116	d3cold_toggle(pdev, D3COLD_ENABLE);
1117
1118	pci_save_state(pdev);
1119	pci_disable_device(pdev);
1120	pci_set_power_state(pdev, PCI_D3cold);
1121
1122	return 0;
1123}
1124
1125static int xe_pci_resume(struct device *dev)
1126{
1127	struct pci_dev *pdev = to_pci_dev(dev);
1128	int err;
1129
1130	/* Give back the D3Cold decision to the runtime P M*/
1131	d3cold_toggle(pdev, D3COLD_DISABLE);
1132
1133	err = pci_set_power_state(pdev, PCI_D0);
1134	if (err)
1135		return err;
1136
1137	pci_restore_state(pdev);
1138
1139	err = pci_enable_device(pdev);
1140	if (err)
1141		return err;
1142
1143	pci_set_master(pdev);
1144
1145	err = xe_pm_resume(pdev_to_xe_device(pdev));
1146	if (err)
1147		return err;
1148
1149	return 0;
1150}
1151
1152static int xe_pci_runtime_suspend(struct device *dev)
1153{
1154	struct pci_dev *pdev = to_pci_dev(dev);
1155	struct xe_device *xe = pdev_to_xe_device(pdev);
1156	int err;
1157
1158	err = xe_pm_runtime_suspend(xe);
1159	if (err)
1160		return err;
1161
1162	pci_save_state(pdev);
1163
1164	if (xe->d3cold.allowed) {
1165		d3cold_toggle(pdev, D3COLD_ENABLE);
1166		pci_disable_device(pdev);
1167		pci_ignore_hotplug(pdev);
1168		pci_set_power_state(pdev, PCI_D3cold);
1169	} else {
1170		d3cold_toggle(pdev, D3COLD_DISABLE);
1171		pci_set_power_state(pdev, PCI_D3hot);
1172	}
1173
1174	return 0;
1175}
1176
1177static int xe_pci_runtime_resume(struct device *dev)
1178{
1179	struct pci_dev *pdev = to_pci_dev(dev);
1180	struct xe_device *xe = pdev_to_xe_device(pdev);
1181	int err;
1182
1183	err = pci_set_power_state(pdev, PCI_D0);
1184	if (err)
1185		return err;
1186
1187	pci_restore_state(pdev);
1188
1189	if (xe->d3cold.allowed) {
1190		err = pci_enable_device(pdev);
1191		if (err)
1192			return err;
1193
1194		pci_set_master(pdev);
1195	}
1196
1197	return xe_pm_runtime_resume(xe);
1198}
1199
1200static int xe_pci_runtime_idle(struct device *dev)
1201{
1202	struct pci_dev *pdev = to_pci_dev(dev);
1203	struct xe_device *xe = pdev_to_xe_device(pdev);
1204
1205	xe_pm_d3cold_allowed_toggle(xe);
1206
1207	return 0;
1208}
1209
1210static const struct dev_pm_ops xe_pm_ops = {
1211	SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1212	SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1213};
1214#endif
1215
1216static struct pci_driver xe_pci_driver = {
1217	.name = DRIVER_NAME,
1218	.id_table = pciidlist,
1219	.probe = xe_pci_probe,
1220	.remove = xe_pci_remove,
1221	.shutdown = xe_pci_shutdown,
1222	.sriov_configure = xe_pci_sriov_configure,
1223#ifdef CONFIG_PM_SLEEP
1224	.driver.pm = &xe_pm_ops,
1225#endif
1226};
1227
1228/**
1229 * xe_pci_to_pf_device() - Get PF &xe_device.
1230 * @pdev: the VF &pci_dev device
1231 *
1232 * Return: pointer to PF &xe_device, NULL otherwise.
1233 */
1234struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
1235{
1236	struct drm_device *drm;
1237
1238	drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver);
1239	if (IS_ERR(drm))
1240		return NULL;
1241
1242	return to_xe_device(drm);
1243}
1244
1245int xe_register_pci_driver(void)
1246{
1247	return pci_register_driver(&xe_pci_driver);
1248}
1249
1250void xe_unregister_pci_driver(void)
1251{
1252	pci_unregister_driver(&xe_pci_driver);
1253}
1254
1255#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1256#include "tests/xe_pci.c"
1257#endif