xe_guc_fwif.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#ifndef _XE_GUC_FWIF_H
  7#define _XE_GUC_FWIF_H
  8
  9#include <linux/bits.h>
 10
 11#include "abi/guc_capture_abi.h"
 12#include "abi/guc_klvs_abi.h"
 13#include "xe_hw_engine_types.h"
 14
 15#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4
 16#define G2H_LEN_DW_DEREGISTER_CONTEXT		3
 17#define G2H_LEN_DW_TLB_INVALIDATE		3
 18#define G2H_LEN_DW_G2G_NOTIFY_MIN		3
 19
 20#define GUC_ID_MAX			65535
 21#define GUC_ID_UNKNOWN			0xffffffff
 22
 23#define GUC_CONTEXT_DISABLE		0
 24#define GUC_CONTEXT_ENABLE		1
 25
 26#define GUC_CLIENT_PRIORITY_KMD_HIGH	0
 27#define GUC_CLIENT_PRIORITY_HIGH	1
 28#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
 29#define GUC_CLIENT_PRIORITY_NORMAL	3
 30#define GUC_CLIENT_PRIORITY_NUM		4
 31
 32#define GUC_RENDER_ENGINE		0
 33#define GUC_VIDEO_ENGINE		1
 34#define GUC_BLITTER_ENGINE		2
 35#define GUC_VIDEOENHANCE_ENGINE		3
 36#define GUC_VIDEO_ENGINE2		4
 37#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
 38
 39#define GUC_RENDER_CLASS		0
 40#define GUC_VIDEO_CLASS			1
 41#define GUC_VIDEOENHANCE_CLASS		2
 42#define GUC_BLITTER_CLASS		3
 43#define GUC_COMPUTE_CLASS		4
 44#define GUC_GSC_OTHER_CLASS		5
 45#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
 46#define GUC_MAX_ENGINE_CLASSES		16
 47#define GUC_MAX_INSTANCES_PER_CLASS	32
 48
 49#define GUC_CONTEXT_NORMAL			0
 50#define GUC_CONTEXT_COMPRESSION_SAVE		1
 51#define GUC_CONTEXT_COMPRESSION_RESTORE	2
 52#define GUC_CONTEXT_COUNT			(GUC_CONTEXT_COMPRESSION_RESTORE + 1)
 53
 54/* Helper for context registration H2G */
 55struct guc_ctxt_registration_info {
 56	u32 flags;
 57	u32 context_idx;
 58	u32 engine_class;
 59	u32 engine_submit_mask;
 60	u32 wq_desc_lo;
 61	u32 wq_desc_hi;
 62	u32 wq_base_lo;
 63	u32 wq_base_hi;
 64	u32 wq_size;
 65	u32 hwlrca_lo;
 66	u32 hwlrca_hi;
 67};
 68#define CONTEXT_REGISTRATION_FLAG_KMD	BIT(0)
 69#define CONTEXT_REGISTRATION_FLAG_TYPE	GENMASK(2, 1)
 70
 71/* 32-bit KLV structure as used by policy updates and others */
 72struct guc_klv_generic_dw_t {
 73	u32 kl;
 74	u32 value;
 75} __packed;
 76
 77/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
 78struct guc_update_exec_queue_policy_header {
 79	u32 action;
 80	u32 guc_id;
 81} __packed;
 82
 83struct guc_update_exec_queue_policy {
 84	struct guc_update_exec_queue_policy_header header;
 85	struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
 86} __packed;
 87
 88/* GUC_CTL_* - Parameters for loading the GuC */
 89#define GUC_CTL_LOG_PARAMS		0
 90#define   GUC_LOG_VALID			BIT(0)
 91#define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)
 92#define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)
 93#define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)
 94#define   GUC_LOG_CRASH			REG_GENMASK(5, 4)
 95#define   GUC_LOG_DEBUG			REG_GENMASK(9, 6)
 96#define   GUC_LOG_CAPTURE		REG_GENMASK(11, 10)
 97#define   GUC_LOG_BUF_ADDR		REG_GENMASK(31, 12)
 98
 99#define GUC_CTL_WA			1
100#define   GUC_WA_GAM_CREDITS		BIT(10)
101#define   GUC_WA_DUAL_QUEUE		BIT(11)
102#define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)
103#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)
104#define   GUC_WA_PRE_PARSER		BIT(14)
105#define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)
106#define   GUC_WA_POLLCS			BIT(18)
107#define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)
108#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)
109#define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6	BIT(22)
110#define   GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6	BIT(25)
111
112#define GUC_CTL_FEATURE			2
113#define   GUC_CTL_ENABLE_SLPC		BIT(2)
114#define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
115#define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
116#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
117#define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
118
119#define GUC_CTL_DEBUG			3
120#define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
121#define	  GUC_LOG_VERBOSITY_MAX		3
122#define	  GUC_LOG_DESTINATION		REG_GENMASK(5, 4)
123#define   GUC_LOG_DISABLED		BIT(6)
124#define   GUC_PROFILE_ENABLED		BIT(7)
125
126#define GUC_CTL_ADS			4
127#define   GUC_ADS_ADDR			REG_GENMASK(21, 1)
128
129#define GUC_CTL_DEVID			5
130
131#define GUC_CTL_MAX_DWORDS		14
132
133/* Scheduling policy settings */
134
135#define GLOBAL_POLICY_MAX_NUM_WI 15
136
137/* Don't reset an engine upon preemption failure */
138#define GLOBAL_POLICY_DISABLE_ENGINE_RESET				BIT(0)
139
140#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
141
142struct guc_policies {
143	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
144	/*
145	 * In micro seconds. How much time to allow before DPC processing is
146	 * called back via interrupt (to prevent DPC queue drain starving).
147	 * Typically 1000s of micro seconds (example only, not granularity).
148	 */
149	u32 dpc_promote_time;
150
151	/* Must be set to take these new values. */
152	u32 is_valid;
153
154	/*
155	 * Max number of WIs to process per call. A large value may keep CS
156	 * idle.
157	 */
158	u32 max_num_work_items;
159
160	u32 global_flags;
161	u32 reserved[4];
162} __packed;
163
164/* Generic GT SysInfo data types */
165#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED		0
166#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK	1
167#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI	2
168#define GUC_GENERIC_GT_SYSINFO_MAX			16
169
170/* HW info */
171struct guc_gt_system_info {
172	u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
173	u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
174	u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
175} __packed;
176
177/* GuC Additional Data Struct */
178struct guc_ads {
179	struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
180	u32 reserved0;
181	u32 scheduler_policies;
182	u32 gt_system_info;
183	u32 reserved1;
184	u32 control_data;
185	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
186	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
187	u32 private_data;
188	u32 um_init_data;
189	u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
190	u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
191	u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
192	u32 wa_klv_addr_lo;
193	u32 wa_klv_addr_hi;
194	u32 wa_klv_size;
195	u32 reserved[11];
196} __packed;
197
198/* Engine usage stats */
199struct guc_engine_usage_record {
200	u32 current_context_index;
201	u32 last_switch_in_stamp;
202	u32 reserved0;
203	u32 total_runtime;
204	u32 reserved1[4];
205} __packed;
206
207struct guc_engine_usage {
208	struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
209} __packed;
210
211/* Engine Activity stats */
212struct guc_engine_activity {
213	u16 change_num;
214	u16 quanta_ratio;
215	u32 last_update_tick;
216	u64 active_ticks;
217} __packed;
218
219struct guc_engine_activity_data {
220	struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
221} __packed;
222
223struct guc_engine_activity_metadata {
224	u32 guc_tsc_frequency_hz;
225	u32 lag_latency_usec;
226	u32 global_change_num;
227	u32 reserved;
228} __packed;
229
230/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
231enum xe_guc_recv_message {
232	XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
233	XE_GUC_RECV_MSG_EXCEPTION = BIT(30),
234};
235
236/* Page fault structures */
237struct access_counter_desc {
238	u32 dw0;
239#define ACCESS_COUNTER_TYPE	BIT(0)
240#define ACCESS_COUNTER_SUBG_LO	GENMASK(31, 1)
241
242	u32 dw1;
243#define ACCESS_COUNTER_SUBG_HI	BIT(0)
244#define ACCESS_COUNTER_RSVD0	GENMASK(2, 1)
245#define ACCESS_COUNTER_ENG_INSTANCE	GENMASK(8, 3)
246#define ACCESS_COUNTER_ENG_CLASS	GENMASK(11, 9)
247#define ACCESS_COUNTER_ASID	GENMASK(31, 12)
248
249	u32 dw2;
250#define ACCESS_COUNTER_VFID	GENMASK(5, 0)
251#define ACCESS_COUNTER_RSVD1	GENMASK(7, 6)
252#define ACCESS_COUNTER_GRANULARITY	GENMASK(10, 8)
253#define ACCESS_COUNTER_RSVD2	GENMASK(16, 11)
254#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)
255
256	u32 dw3;
257#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)
258} __packed;
259
260enum guc_um_queue_type {
261	GUC_UM_HW_QUEUE_PAGE_FAULT = 0,
262	GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,
263	GUC_UM_HW_QUEUE_ACCESS_COUNTER,
264	GUC_UM_HW_QUEUE_MAX
265};
266
267struct guc_um_queue_params {
268	u64 base_dpa;
269	u32 base_ggtt_address;
270	u32 size_in_bytes;
271	u32 rsvd[4];
272} __packed;
273
274struct guc_um_init_params {
275	u64 page_response_timeout_in_us;
276	u32 rsvd[6];
277	struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];
278} __packed;
279
280enum xe_guc_fault_reply_type {
281	PFR_ACCESS = 0,
282	PFR_ENGINE,
283	PFR_VFID,
284	PFR_ALL,
285	PFR_INVALID
286};
287
288enum xe_guc_response_desc_type {
289	TLB_INVALIDATION_DESC = 0,
290	FAULT_RESPONSE_DESC
291};
292
293struct xe_guc_pagefault_desc {
294	u32 dw0;
295#define PFD_FAULT_LEVEL		GENMASK(2, 0)
296#define PFD_SRC_ID		GENMASK(10, 3)
297#define PFD_RSVD_0		GENMASK(17, 11)
298#define XE2_PFD_TRVA_FAULT	BIT(18)
299#define PFD_ENG_INSTANCE	GENMASK(24, 19)
300#define PFD_ENG_CLASS		GENMASK(27, 25)
301#define PFD_PDATA_LO		GENMASK(31, 28)
302
303	u32 dw1;
304#define PFD_PDATA_HI		GENMASK(11, 0)
305#define PFD_PDATA_HI_SHIFT	4
306#define PFD_ASID		GENMASK(31, 12)
307
308	u32 dw2;
309#define PFD_ACCESS_TYPE		GENMASK(1, 0)
310#define PFD_FAULT_TYPE		GENMASK(3, 2)
311#define PFD_VFID		GENMASK(9, 4)
312#define PFD_RSVD_1		GENMASK(11, 10)
313#define PFD_VIRTUAL_ADDR_LO	GENMASK(31, 12)
314#define PFD_VIRTUAL_ADDR_LO_SHIFT 12
315
316	u32 dw3;
317#define PFD_VIRTUAL_ADDR_HI	GENMASK(31, 0)
318#define PFD_VIRTUAL_ADDR_HI_SHIFT 32
319} __packed;
320
321struct xe_guc_pagefault_reply {
322	u32 dw0;
323#define PFR_VALID		BIT(0)
324#define PFR_SUCCESS		BIT(1)
325#define PFR_REPLY		GENMASK(4, 2)
326#define PFR_RSVD_0		GENMASK(9, 5)
327#define PFR_DESC_TYPE		GENMASK(11, 10)
328#define PFR_ASID		GENMASK(31, 12)
329
330	u32 dw1;
331#define PFR_VFID		GENMASK(5, 0)
332#define PFR_RSVD_1		BIT(6)
333#define PFR_ENG_INSTANCE	GENMASK(12, 7)
334#define PFR_ENG_CLASS		GENMASK(15, 13)
335#define PFR_PDATA		GENMASK(31, 16)
336
337	u32 dw2;
338#define PFR_RSVD_2		GENMASK(31, 0)
339} __packed;
340
341struct xe_guc_acc_desc {
342	u32 dw0;
343#define ACC_TYPE	BIT(0)
344#define ACC_TRIGGER	0
345#define ACC_NOTIFY	1
346#define ACC_SUBG_LO	GENMASK(31, 1)
347
348	u32 dw1;
349#define ACC_SUBG_HI	BIT(0)
350#define ACC_RSVD0	GENMASK(2, 1)
351#define ACC_ENG_INSTANCE	GENMASK(8, 3)
352#define ACC_ENG_CLASS	GENMASK(11, 9)
353#define ACC_ASID	GENMASK(31, 12)
354
355	u32 dw2;
356#define ACC_VFID	GENMASK(5, 0)
357#define ACC_RSVD1	GENMASK(7, 6)
358#define ACC_GRANULARITY	GENMASK(10, 8)
359#define ACC_RSVD2	GENMASK(16, 11)
360#define ACC_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)
361
362	u32 dw3;
363#define ACC_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)
364} __packed;
365
366#endif