xe_gt_ccs_mode.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#include <drm/drm_managed.h>
  7
  8#include "regs/xe_gt_regs.h"
  9#include "xe_assert.h"
 10#include "xe_gt.h"
 11#include "xe_gt_ccs_mode.h"
 12#include "xe_gt_printk.h"
 13#include "xe_gt_sysfs.h"
 14#include "xe_mmio.h"
 15#include "xe_pm.h"
 16#include "xe_sriov.h"
 17
 18static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
 19{
 20	u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */
 21	int num_slices = hweight32(CCS_MASK(gt));
 22	struct xe_device *xe = gt_to_xe(gt);
 23	int width, cslice = 0;
 24	u32 config = 0;
 25
 26	xe_assert(xe, xe_gt_ccs_mode_enabled(gt));
 27
 28	xe_assert(xe, num_engines && num_engines <= num_slices);
 29	xe_assert(xe, !(num_slices % num_engines));
 30
 31	/*
 32	 * Loop over all available slices and assign each a user engine.
 33	 * For example, if there are four compute slices available, the
 34	 * assignment of compute slices to compute engines would be,
 35	 *
 36	 * With 1 engine (ccs0):
 37	 *   slice 0, 1, 2, 3: ccs0
 38	 *
 39	 * With 2 engines (ccs0, ccs1):
 40	 *   slice 0, 2: ccs0
 41	 *   slice 1, 3: ccs1
 42	 *
 43	 * With 4 engines (ccs0, ccs1, ccs2, ccs3):
 44	 *   slice 0: ccs0
 45	 *   slice 1: ccs1
 46	 *   slice 2: ccs2
 47	 *   slice 3: ccs3
 48	 */
 49	for (width = num_slices / num_engines; width; width--) {
 50		struct xe_hw_engine *hwe;
 51		enum xe_hw_engine_id id;
 52
 53		for_each_hw_engine(hwe, gt, id) {
 54			if (hwe->class != XE_ENGINE_CLASS_COMPUTE)
 55				continue;
 56
 57			if (hwe->logical_instance >= num_engines)
 58				break;
 59
 60			config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0;
 61
 62			/* If a slice is fused off, leave disabled */
 63			while ((CCS_MASK(gt) & BIT(cslice)) == 0)
 64				cslice++;
 65
 66			mode &= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK);
 67			mode |= CCS_MODE_CSLICE(cslice, hwe->instance);
 68			cslice++;
 69		}
 70	}
 71
 72	/*
 73	 * Mask bits need to be set for the register. Though only Xe2+
 74	 * platforms require setting of mask bits, it won't harm for older
 75	 * platforms as these bits are unused there.
 76	 */
 77	mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
 78	xe_mmio_write32(&gt->mmio, CCS_MODE, mode);
 79
 80	xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
 81		  mode, config, num_engines, num_slices);
 82}
 83
 84void xe_gt_apply_ccs_mode(struct xe_gt *gt)
 85{
 86	if (!gt->ccs_mode || IS_SRIOV_VF(gt_to_xe(gt)))
 87		return;
 88
 89	__xe_gt_apply_ccs_mode(gt, gt->ccs_mode);
 90}
 91
 92static ssize_t
 93num_cslices_show(struct device *kdev,
 94		 struct device_attribute *attr, char *buf)
 95{
 96	struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
 97
 98	return sysfs_emit(buf, "%u\n", hweight32(CCS_MASK(gt)));
 99}
100
101static DEVICE_ATTR_RO(num_cslices);
102
103static ssize_t
104ccs_mode_show(struct device *kdev,
105	      struct device_attribute *attr, char *buf)
106{
107	struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
108
109	return sysfs_emit(buf, "%u\n", gt->ccs_mode);
110}
111
112static ssize_t
113ccs_mode_store(struct device *kdev, struct device_attribute *attr,
114	       const char *buff, size_t count)
115{
116	struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
117	struct xe_device *xe = gt_to_xe(gt);
118	u32 num_engines, num_slices;
119	int ret;
120
121	if (IS_SRIOV(xe)) {
122		xe_gt_dbg(gt, "Can't change compute mode when running as %s\n",
123			  xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
124		return -EOPNOTSUPP;
125	}
126
127	ret = kstrtou32(buff, 0, &num_engines);
128	if (ret)
129		return ret;
130
131	/*
132	 * Ensure number of engines specified is valid and there is an
133	 * exact multiple of engines for slices.
134	 */
135	num_slices = hweight32(CCS_MASK(gt));
136	if (!num_engines || num_engines > num_slices || num_slices % num_engines) {
137		xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n",
138			  num_engines, num_slices);
139		return -EINVAL;
140	}
141
142	/* CCS mode can only be updated when there are no drm clients */
143	mutex_lock(&xe->drm.filelist_mutex);
144	if (!list_empty(&xe->drm.filelist)) {
145		mutex_unlock(&xe->drm.filelist_mutex);
146		xe_gt_dbg(gt, "Rejecting compute mode change as there are active drm clients\n");
147		return -EBUSY;
148	}
149
150	if (gt->ccs_mode != num_engines) {
151		xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);
152		gt->ccs_mode = num_engines;
153		xe_gt_record_user_engines(gt);
154		guard(xe_pm_runtime)(xe);
155		xe_gt_reset(gt);
156	}
157
158	mutex_unlock(&xe->drm.filelist_mutex);
159
160	return count;
161}
162
163static DEVICE_ATTR_RW(ccs_mode);
164
165static const struct attribute *gt_ccs_mode_attrs[] = {
166	&dev_attr_ccs_mode.attr,
167	&dev_attr_num_cslices.attr,
168	NULL,
169};
170
171static void xe_gt_ccs_mode_sysfs_fini(void *arg)
172{
173	struct xe_gt *gt = arg;
174
175	sysfs_remove_files(gt->sysfs, gt_ccs_mode_attrs);
176}
177
178/**
179 * xe_gt_ccs_mode_sysfs_init - Initialize CCS mode sysfs interfaces
180 * @gt: GT structure
181 *
182 * Through a per-gt 'ccs_mode' sysfs interface, the user can enable a fixed
183 * number of compute hardware engines to which the available compute slices
184 * are to be allocated. This user configuration change triggers a gt reset
185 * and it is expected that there are no open drm clients while doing so.
186 * The number of available compute slices is exposed to user through a per-gt
187 * 'num_cslices' sysfs interface.
188 *
189 * Returns: Returns error value for failure and 0 for success.
190 */
191int xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt)
192{
193	struct xe_device *xe = gt_to_xe(gt);
194	int err;
195
196	if (!xe_gt_ccs_mode_enabled(gt))
197		return 0;
198
199	err = sysfs_create_files(gt->sysfs, gt_ccs_mode_attrs);
200	if (err)
201		return err;
202
203	return devm_add_action_or_reset(xe->drm.dev, xe_gt_ccs_mode_sysfs_fini, gt);
204}