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xe_ggtt_types.h

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linux-6.19.14/drivers/gpu/drm/xe/xe_ggtt_types.h C
 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2022 Intel Corporation
 4 */
 5
 6#ifndef _XE_GGTT_TYPES_H_
 7#define _XE_GGTT_TYPES_H_
 8
 9#include <drm/drm_mm.h>
10
11#include "xe_pt_types.h"
12
13struct xe_bo;
14struct xe_gt;
15
16/**
17 * struct xe_ggtt - Main GGTT struct
18 *
19 * In general, each tile can contains its own Global Graphics Translation Table
20 * (GGTT) instance.
21 */
22struct xe_ggtt {
23	/** @tile: Back pointer to tile where this GGTT belongs */
24	struct xe_tile *tile;
25	/** @size: Total size of this GGTT */
26	u64 size;
27
28#define XE_GGTT_FLAGS_64K       BIT(0)
29#define XE_GGTT_FLAGS_ONLINE	BIT(1)
30	/**
31	 * @flags: Flags for this GGTT
32	 * Acceptable flags:
33	 * - %XE_GGTT_FLAGS_64K - if PTE size is 64K. Otherwise, regular is 4K.
34	 * - %XE_GGTT_FLAGS_ONLINE - is GGTT online, protected by ggtt->lock
35	 *   after init
36	 */
37	unsigned int flags;
38	/** @scratch: Internal object allocation used as a scratch page */
39	struct xe_bo *scratch;
40	/** @lock: Mutex lock to protect GGTT data */
41	struct mutex lock;
42	/**
43	 *  @gsm: The iomem pointer to the actual location of the translation
44	 * table located in the GSM for easy PTE manipulation
45	 */
46	u64 __iomem *gsm;
47	/** @pt_ops: Page Table operations per platform */
48	const struct xe_ggtt_pt_ops *pt_ops;
49	/** @mm: The memory manager used to manage individual GGTT allocations */
50	struct drm_mm mm;
51	/** @access_count: counts GGTT writes */
52	unsigned int access_count;
53	/** @wq: Dedicated unordered work queue to process node removals */
54	struct workqueue_struct *wq;
55};
56
57/**
58 * struct xe_ggtt_node - A node in GGTT.
59 *
60 * This struct needs to be initialized (only-once) with xe_ggtt_node_init() before any node
61 * insertion, reservation, or 'ballooning'.
62 * It will, then, be finalized by either xe_ggtt_node_remove() or xe_ggtt_node_deballoon().
63 */
64struct xe_ggtt_node {
65	/** @ggtt: Back pointer to xe_ggtt where this region will be inserted at */
66	struct xe_ggtt *ggtt;
67	/** @base: A drm_mm_node */
68	struct drm_mm_node base;
69	/** @delayed_removal_work: The work struct for the delayed removal */
70	struct work_struct delayed_removal_work;
71	/** @invalidate_on_remove: If it needs invalidation upon removal */
72	bool invalidate_on_remove;
73};
74
75/**
76 * struct xe_ggtt_pt_ops - GGTT Page table operations
77 * Which can vary from platform to platform.
78 */
79struct xe_ggtt_pt_ops {
80	/** @pte_encode_flags: Encode PTE flags for a given BO */
81	u64 (*pte_encode_flags)(struct xe_bo *bo, u16 pat_index);
82	/** @ggtt_set_pte: Directly write into GGTT's PTE */
83	void (*ggtt_set_pte)(struct xe_ggtt *ggtt, u64 addr, u64 pte);
84	/** @ggtt_get_pte: Directly read from GGTT's PTE */
85	u64 (*ggtt_get_pte)(struct xe_ggtt *ggtt, u64 addr);
86};
87
88#endif
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