xe_device_types.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022-2023 Intel Corporation
  4 */
  5
  6#ifndef _XE_DEVICE_TYPES_H_
  7#define _XE_DEVICE_TYPES_H_
  8
  9#include <linux/pci.h>
 10
 11#include <drm/drm_device.h>
 12#include <drm/drm_file.h>
 13#include <drm/ttm/ttm_device.h>
 14
 15#include "xe_devcoredump_types.h"
 16#include "xe_heci_gsc.h"
 17#include "xe_late_bind_fw_types.h"
 18#include "xe_lmtt_types.h"
 19#include "xe_memirq_types.h"
 20#include "xe_oa_types.h"
 21#include "xe_pagefault_types.h"
 22#include "xe_platform_types.h"
 23#include "xe_pmu_types.h"
 24#include "xe_pt_types.h"
 25#include "xe_sriov_pf_types.h"
 26#include "xe_sriov_types.h"
 27#include "xe_sriov_vf_types.h"
 28#include "xe_sriov_vf_ccs_types.h"
 29#include "xe_step_types.h"
 30#include "xe_survivability_mode_types.h"
 31#include "xe_tile_sriov_vf_types.h"
 32#include "xe_validation.h"
 33
 34#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
 35#define TEST_VM_OPS_ERROR
 36#endif
 37
 38struct dram_info;
 39struct intel_display;
 40struct intel_dg_nvm_dev;
 41struct xe_ggtt;
 42struct xe_i2c;
 43struct xe_pat_ops;
 44struct xe_pxp;
 45struct xe_vram_region;
 46
 47/**
 48 * enum xe_wedged_mode - possible wedged modes
 49 * @XE_WEDGED_MODE_NEVER: Device will never be declared wedged.
 50 * @XE_WEDGED_MODE_UPON_CRITICAL_ERROR: Device will be declared wedged only
 51 *	when critical error occurs like GT reset failure or firmware failure.
 52 *	This is the default mode.
 53 * @XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET: Device will be declared wedged on
 54 *	any hang. In this mode, engine resets are disabled to avoid automatic
 55 *	recovery attempts. This mode is primarily intended for debugging hangs.
 56 */
 57enum xe_wedged_mode {
 58	XE_WEDGED_MODE_NEVER = 0,
 59	XE_WEDGED_MODE_UPON_CRITICAL_ERROR = 1,
 60	XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET = 2,
 61};
 62
 63#define XE_BO_INVALID_OFFSET	LONG_MAX
 64
 65#define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100)
 66#define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100)
 67#define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100)
 68#define MEDIA_VERx100(xe) ((xe)->info.media_verx100)
 69#define IS_DGFX(xe) ((xe)->info.is_dgfx)
 70
 71#define XE_VRAM_FLAGS_NEED64K		BIT(0)
 72
 73#define XE_GT0		0
 74#define XE_GT1		1
 75#define XE_MAX_TILES_PER_DEVICE	(XE_GT1 + 1)
 76
 77#define XE_MAX_ASID	(BIT(20))
 78
 79#define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step)	\
 80	((_xe)->info.platform == (_platform) &&			\
 81	 (_xe)->info.step.graphics >= (min_step) &&		\
 82	 (_xe)->info.step.graphics < (max_step))
 83#define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step)	\
 84	((_xe)->info.platform == (_platform) &&				\
 85	 (_xe)->info.subplatform == (sub) &&				\
 86	 (_xe)->info.step.graphics >= (min_step) &&			\
 87	 (_xe)->info.step.graphics < (max_step))
 88
 89#define tile_to_xe(tile__)								\
 90	_Generic(tile__,								\
 91		 const struct xe_tile * : (const struct xe_device *)((tile__)->xe),	\
 92		 struct xe_tile * : (tile__)->xe)
 93
 94/**
 95 * struct xe_mmio - register mmio structure
 96 *
 97 * Represents an MMIO region that the CPU may use to access registers.  A
 98 * region may share its IO map with other regions (e.g., all GTs within a
 99 * tile share the same map with their parent tile, but represent different
100 * subregions of the overall IO space).
101 */
102struct xe_mmio {
103	/** @tile: Backpointer to tile, used for tracing */
104	struct xe_tile *tile;
105
106	/** @regs: Map used to access registers. */
107	void __iomem *regs;
108
109	/**
110	 * @sriov_vf_gt: Backpointer to GT.
111	 *
112	 * This pointer is only set for GT MMIO regions and only when running
113	 * as an SRIOV VF structure
114	 */
115	struct xe_gt *sriov_vf_gt;
116
117	/**
118	 * @regs_size: Length of the register region within the map.
119	 *
120	 * The size of the iomap set in *regs is generally larger than the
121	 * register mmio space since it includes unused regions and/or
122	 * non-register regions such as the GGTT PTEs.
123	 */
124	size_t regs_size;
125
126	/** @adj_limit: adjust MMIO address if address is below this value */
127	u32 adj_limit;
128
129	/** @adj_offset: offset to add to MMIO address when adjusting */
130	u32 adj_offset;
131};
132
133/**
134 * struct xe_tile - hardware tile structure
135 *
136 * From a driver perspective, a "tile" is effectively a complete GPU, containing
137 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
138 *
139 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
140 * device and designate one "root" tile as being responsible for external PCI
141 * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each
142 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
143 * with each tile similarly.  Device-wide interrupts can be enabled/disabled
144 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
145 * have interrupts that need servicing.
146 */
147struct xe_tile {
148	/** @xe: Backpointer to tile's PCI device */
149	struct xe_device *xe;
150
151	/** @id: ID of the tile */
152	u8 id;
153
154	/**
155	 * @primary_gt: Primary GT
156	 */
157	struct xe_gt *primary_gt;
158
159	/**
160	 * @media_gt: Media GT
161	 *
162	 * Only present on devices with media version >= 13.
163	 */
164	struct xe_gt *media_gt;
165
166	/**
167	 * @mmio: MMIO info for a tile.
168	 *
169	 * Each tile has its own 16MB space in BAR0, laid out as:
170	 * * 0-4MB: registers
171	 * * 4MB-8MB: reserved
172	 * * 8MB-16MB: global GTT
173	 */
174	struct xe_mmio mmio;
175
176	/** @mem: memory management info for tile */
177	struct {
178		/**
179		 * @mem.kernel_vram: kernel-dedicated VRAM info for tile.
180		 *
181		 * Although VRAM is associated with a specific tile, it can
182		 * still be accessed by all tiles' GTs.
183		 */
184		struct xe_vram_region *kernel_vram;
185
186		/**
187		 * @mem.vram: general purpose VRAM info for tile.
188		 *
189		 * Although VRAM is associated with a specific tile, it can
190		 * still be accessed by all tiles' GTs.
191		 */
192		struct xe_vram_region *vram;
193
194		/** @mem.ggtt: Global graphics translation table */
195		struct xe_ggtt *ggtt;
196
197		/**
198		 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
199		 *
200		 * Media GT shares a pool with its primary GT.
201		 */
202		struct xe_sa_manager *kernel_bb_pool;
203	} mem;
204
205	/** @sriov: tile level virtualization data */
206	union {
207		struct {
208			/** @sriov.pf.lmtt: Local Memory Translation Table. */
209			struct xe_lmtt lmtt;
210		} pf;
211		struct {
212			/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
213			struct xe_ggtt_node *ggtt_balloon[2];
214			/** @sriov.vf.self_config: VF configuration data */
215			struct xe_tile_sriov_vf_selfconfig self_config;
216		} vf;
217	} sriov;
218
219	/** @memirq: Memory Based Interrupts. */
220	struct xe_memirq memirq;
221
222	/** @csc_hw_error_work: worker to report CSC HW errors */
223	struct work_struct csc_hw_error_work;
224
225	/** @pcode: tile's PCODE */
226	struct {
227		/** @pcode.lock: protecting tile's PCODE mailbox data */
228		struct mutex lock;
229	} pcode;
230
231	/** @migrate: Migration helper for vram blits and clearing */
232	struct xe_migrate *migrate;
233
234	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
235	struct kobject *sysfs;
236
237	/** @debugfs: debugfs directory associated with this tile */
238	struct dentry *debugfs;
239};
240
241/**
242 * struct xe_device - Top level struct of Xe device
243 */
244struct xe_device {
245	/** @drm: drm device */
246	struct drm_device drm;
247
248#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
249	/** @display: display device data, must be placed after drm device member */
250	struct intel_display *display;
251#endif
252
253	/** @devcoredump: device coredump */
254	struct xe_devcoredump devcoredump;
255
256	/** @info: device info */
257	struct intel_device_info {
258		/** @info.platform_name: platform name */
259		const char *platform_name;
260		/** @info.graphics_name: graphics IP name */
261		const char *graphics_name;
262		/** @info.media_name: media IP name */
263		const char *media_name;
264		/** @info.graphics_verx100: graphics IP version */
265		u32 graphics_verx100;
266		/** @info.media_verx100: media IP version */
267		u32 media_verx100;
268		/** @info.mem_region_mask: mask of valid memory regions */
269		u32 mem_region_mask;
270		/** @info.platform: Xe platform enum */
271		enum xe_platform platform;
272		/** @info.subplatform: Xe subplatform enum */
273		enum xe_subplatform subplatform;
274		/** @info.devid: device ID */
275		u16 devid;
276		/** @info.revid: device revision */
277		u8 revid;
278		/** @info.step: stepping information for each IP */
279		struct xe_step_info step;
280		/** @info.dma_mask_size: DMA address bits */
281		u8 dma_mask_size;
282		/** @info.vram_flags: Vram flags */
283		u8 vram_flags;
284		/** @info.tile_count: Number of tiles */
285		u8 tile_count;
286		/** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
287		u8 max_gt_per_tile;
288		/** @info.gt_count: Total number of GTs for entire device */
289		u8 gt_count;
290		/** @info.vm_max_level: Max VM level */
291		u8 vm_max_level;
292		/** @info.va_bits: Maximum bits of a virtual address */
293		u8 va_bits;
294
295		/*
296		 * Keep all flags below alphabetically sorted
297		 */
298
299		/** @info.force_execlist: Forced execlist submission */
300		u8 force_execlist:1;
301		/** @info.has_asid: Has address space ID */
302		u8 has_asid:1;
303		/** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
304		u8 has_atomic_enable_pte_bit:1;
305		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
306		u8 has_device_atomics_on_smem:1;
307		/** @info.has_fan_control: Device supports fan control */
308		u8 has_fan_control:1;
309		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
310		u8 has_flat_ccs:1;
311		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
312		u8 has_gsc_nvm:1;
313		/** @info.has_heci_cscfi: device has heci cscfi */
314		u8 has_heci_cscfi:1;
315		/** @info.has_heci_gscfi: device has heci gscfi */
316		u8 has_heci_gscfi:1;
317		/** @info.has_late_bind: Device has firmware late binding support */
318		u8 has_late_bind:1;
319		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
320		u8 has_llc:1;
321		/** @info.has_mbx_power_limits: Device has support to manage power limits using
322		 * pcode mailbox commands.
323		 */
324		u8 has_mbx_power_limits:1;
325		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
326		u8 has_mem_copy_instr:1;
327		/** @info.has_pxp: Device has PXP support */
328		u8 has_pxp:1;
329		/** @info.has_range_tlb_inval: Has range based TLB invalidations */
330		u8 has_range_tlb_inval:1;
331		/** @info.has_sriov: Supports SR-IOV */
332		u8 has_sriov:1;
333		/** @info.has_usm: Device has unified shared memory support */
334		u8 has_usm:1;
335		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
336		u8 has_64bit_timestamp:1;
337		/** @info.is_dgfx: is discrete device */
338		u8 is_dgfx:1;
339		/** @info.needs_scratch: needs scratch page for oob prefetch to work */
340		u8 needs_scratch:1;
341		/**
342		 * @info.probe_display: Probe display hardware.  If set to
343		 * false, the driver will behave as if there is no display
344		 * hardware present and will not try to read/write to it in any
345		 * way.  The display hardware, if it exists, will not be
346		 * exposed to userspace and will be left untouched in whatever
347		 * state the firmware or bootloader left it in.
348		 */
349		u8 probe_display:1;
350		/** @info.skip_guc_pc: Skip GuC based PM feature init */
351		u8 skip_guc_pc:1;
352		/** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
353		u8 skip_mtcfg:1;
354		/** @info.skip_pcode: skip access to PCODE uC */
355		u8 skip_pcode:1;
356		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */
357		u8 needs_shared_vf_gt_wq:1;
358	} info;
359
360	/** @wa_active: keep track of active workarounds */
361	struct {
362		/** @wa_active.oob: bitmap with active OOB workarounds */
363		unsigned long *oob;
364
365		/**
366		 * @wa_active.oob_initialized: Mark oob as initialized to help detecting misuse
367		 * of XE_DEVICE_WA() - it can only be called on initialization after
368		 * Device OOB WAs have been processed.
369		 */
370		bool oob_initialized;
371	} wa_active;
372
373	/** @survivability: survivability information for device */
374	struct xe_survivability survivability;
375
376	/** @irq: device interrupt state */
377	struct {
378		/** @irq.lock: lock for processing irq's on this device */
379		spinlock_t lock;
380
381		/** @irq.enabled: interrupts enabled on this device */
382		atomic_t enabled;
383
384		/** @irq.msix: irq info for platforms that support MSI-X */
385		struct {
386			/** @irq.msix.nvec: number of MSI-X interrupts */
387			u16 nvec;
388			/** @irq.msix.indexes: used to allocate MSI-X indexes */
389			struct xarray indexes;
390		} msix;
391	} irq;
392
393	/** @ttm: ttm device */
394	struct ttm_device ttm;
395
396	/** @mmio: mmio info for device */
397	struct {
398		/** @mmio.size: size of MMIO space for device */
399		size_t size;
400		/** @mmio.regs: pointer to MMIO space for device */
401		void __iomem *regs;
402	} mmio;
403
404	/** @mem: memory info for device */
405	struct {
406		/** @mem.vram: VRAM info for device */
407		struct xe_vram_region *vram;
408		/** @mem.sys_mgr: system TTM manager */
409		struct ttm_resource_manager sys_mgr;
410		/** @mem.sys_mgr: system memory shrinker. */
411		struct xe_shrinker *shrinker;
412	} mem;
413
414	/** @sriov: device level virtualization data */
415	struct {
416		/** @sriov.__mode: SR-IOV mode (Don't access directly!) */
417		enum xe_sriov_mode __mode;
418
419		union {
420			/** @sriov.pf: PF specific data */
421			struct xe_device_pf pf;
422			/** @sriov.vf: VF specific data */
423			struct xe_device_vf vf;
424		};
425
426		/** @sriov.wq: workqueue used by the virtualization workers */
427		struct workqueue_struct *wq;
428	} sriov;
429
430	/** @usm: unified memory state */
431	struct {
432		/** @usm.asid: convert a ASID to VM */
433		struct xarray asid_to_vm;
434		/** @usm.next_asid: next ASID, used to cyclical alloc asids */
435		u32 next_asid;
436		/** @usm.lock: protects UM state */
437		struct rw_semaphore lock;
438		/** @usm.pf_wq: page fault work queue, unbound, high priority */
439		struct workqueue_struct *pf_wq;
440		/*
441		 * We pick 4 here because, in the current implementation, it
442		 * yields the best bandwidth utilization of the kernel paging
443		 * engine.
444		 */
445#define XE_PAGEFAULT_QUEUE_COUNT	4
446		/** @usm.pf_queue: Page fault queues */
447		struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
448	} usm;
449
450	/** @pinned: pinned BO state */
451	struct {
452		/** @pinned.lock: protected pinned BO list state */
453		spinlock_t lock;
454		/** @pinned.early: early pinned lists */
455		struct {
456			/** @pinned.early.kernel_bo_present: pinned kernel BO that are present */
457			struct list_head kernel_bo_present;
458			/** @pinned.early.evicted: pinned BO that have been evicted */
459			struct list_head evicted;
460		} early;
461		/** @pinned.late: late pinned lists */
462		struct {
463			/** @pinned.late.kernel_bo_present: pinned kernel BO that are present */
464			struct list_head kernel_bo_present;
465			/** @pinned.late.evicted: pinned BO that have been evicted */
466			struct list_head evicted;
467			/** @pinned.external: pinned external and dma-buf. */
468			struct list_head external;
469		} late;
470	} pinned;
471
472	/** @ufence_wq: user fence wait queue */
473	wait_queue_head_t ufence_wq;
474
475	/** @preempt_fence_wq: used to serialize preempt fences */
476	struct workqueue_struct *preempt_fence_wq;
477
478	/** @ordered_wq: used to serialize compute mode resume */
479	struct workqueue_struct *ordered_wq;
480
481	/** @unordered_wq: used to serialize unordered work */
482	struct workqueue_struct *unordered_wq;
483
484	/** @destroy_wq: used to serialize user destroy work, like queue */
485	struct workqueue_struct *destroy_wq;
486
487	/** @tiles: device tiles */
488	struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE];
489
490	/**
491	 * @mem_access: keep track of memory access in the device, possibly
492	 * triggering additional actions when they occur.
493	 */
494	struct {
495		/**
496		 * @mem_access.vram_userfault: Encapsulate vram_userfault
497		 * related stuff
498		 */
499		struct {
500			/**
501			 * @mem_access.vram_userfault.lock: Protects access to
502			 * @vram_usefault.list Using mutex instead of spinlock
503			 * as lock is applied to entire list operation which
504			 * may sleep
505			 */
506			struct mutex lock;
507
508			/**
509			 * @mem_access.vram_userfault.list: Keep list of userfaulted
510			 * vram bo, which require to release their mmap mappings
511			 * at runtime suspend path
512			 */
513			struct list_head list;
514		} vram_userfault;
515	} mem_access;
516
517	/**
518	 * @pat: Encapsulate PAT related stuff
519	 */
520	struct {
521		/** @pat.ops: Internal operations to abstract platforms */
522		const struct xe_pat_ops *ops;
523		/** @pat.table: PAT table to program in the HW */
524		const struct xe_pat_table_entry *table;
525		/** @pat.n_entries: Number of PAT entries */
526		int n_entries;
527		/** @pat.ats_entry: PAT entry for PCIe ATS responses */
528		const struct xe_pat_table_entry *pat_ats;
529		/** @pat.pta_entry: PAT entry for page table accesses */
530		const struct xe_pat_table_entry *pat_pta;
531		u32 idx[__XE_CACHE_LEVEL_COUNT];
532	} pat;
533
534	/** @d3cold: Encapsulate d3cold related stuff */
535	struct {
536		/** @d3cold.capable: Indicates if root port is d3cold capable */
537		bool capable;
538
539		/** @d3cold.allowed: Indicates if d3cold is a valid device state */
540		bool allowed;
541
542		/**
543		 * @d3cold.vram_threshold:
544		 *
545		 * This represents the permissible threshold(in megabytes)
546		 * for vram save/restore. d3cold will be disallowed,
547		 * when vram_usages is above or equals the threshold value
548		 * to avoid the vram save/restore latency.
549		 * Default threshold value is 300mb.
550		 */
551		u32 vram_threshold;
552		/** @d3cold.lock: protect vram_threshold */
553		struct mutex lock;
554	} d3cold;
555
556	/** @pm_notifier: Our PM notifier to perform actions in response to various PM events. */
557	struct notifier_block pm_notifier;
558	/** @pm_block: Completion to block validating tasks on suspend / hibernate prepare */
559	struct completion pm_block;
560	/** @rebind_resume_list: List of wq items to kick on resume. */
561	struct list_head rebind_resume_list;
562	/** @rebind_resume_lock: Lock to protect the rebind_resume_list */
563	struct mutex rebind_resume_lock;
564
565	/** @pmt: Support the PMT driver callback interface */
566	struct {
567		/** @pmt.lock: protect access for telemetry data */
568		struct mutex lock;
569	} pmt;
570
571	/**
572	 * @pm_callback_task: Track the active task that is running in either
573	 * the runtime_suspend or runtime_resume callbacks.
574	 */
575	struct task_struct *pm_callback_task;
576
577	/** @hwmon: hwmon subsystem integration */
578	struct xe_hwmon *hwmon;
579
580	/** @heci_gsc: graphics security controller */
581	struct xe_heci_gsc heci_gsc;
582
583	/** @nvm: discrete graphics non-volatile memory */
584	struct intel_dg_nvm_dev *nvm;
585
586	/** @late_bind: xe mei late bind interface */
587	struct xe_late_bind late_bind;
588
589	/** @oa: oa observation subsystem */
590	struct xe_oa oa;
591
592	/** @pxp: Encapsulate Protected Xe Path support */
593	struct xe_pxp *pxp;
594
595	/** @needs_flr_on_fini: requests function-reset on fini */
596	bool needs_flr_on_fini;
597
598	/** @wedged: Struct to control Wedged States and mode */
599	struct {
600		/** @wedged.flag: Xe device faced a critical error and is now blocked. */
601		atomic_t flag;
602		/** @wedged.mode: Mode controlled by kernel parameter and debugfs */
603		int mode;
604		/** @wedged.method: Recovery method to be sent in the drm device wedged uevent */
605		unsigned long method;
606		/** @wedged.inconsistent_reset: Inconsistent reset policy state between GTs */
607		bool inconsistent_reset;
608	} wedged;
609
610	/** @bo_device: Struct to control async free of BOs */
611	struct xe_bo_dev {
612		/** @bo_device.async_free: Free worker */
613		struct work_struct async_free;
614		/** @bo_device.async_list: List of BOs to be freed */
615		struct llist_head async_list;
616	} bo_device;
617
618	/** @pmu: performance monitoring unit */
619	struct xe_pmu pmu;
620
621	/** @i2c: I2C host controller */
622	struct xe_i2c *i2c;
623
624	/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
625	u32 atomic_svm_timeslice_ms;
626
627#ifdef TEST_VM_OPS_ERROR
628	/**
629	 * @vm_inject_error_position: inject errors at different places in VM
630	 * bind IOCTL based on this value
631	 */
632	u8 vm_inject_error_position;
633#endif
634
635#if IS_ENABLED(CONFIG_TRACE_GPU_MEM)
636	/**
637	 * @global_total_pages: global GPU page usage tracked for gpu_mem
638	 * tracepoints
639	 */
640	atomic64_t global_total_pages;
641#endif
642	/** @val: The domain for exhaustive eviction, which is currently per device. */
643	struct xe_validation_device val;
644
645	/** @psmi: GPU debugging via additional validation HW */
646	struct {
647		/** @psmi.capture_obj: PSMI buffer for VRAM */
648		struct xe_bo *capture_obj[XE_MAX_TILES_PER_DEVICE + 1];
649		/** @psmi.region_mask: Mask of valid memory regions */
650		u8 region_mask;
651	} psmi;
652
653#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
654	/** @g2g_test_array: for testing G2G communications */
655	u32 *g2g_test_array;
656	/** @g2g_test_count: for testing G2G communications */
657	atomic_t g2g_test_count;
658#endif
659
660	/* private: */
661
662#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
663	/*
664	 * Any fields below this point are the ones used by display.
665	 * They are temporarily added here so xe_device can be desguised as
666	 * drm_i915_private during build. After cleanup these should go away,
667	 * migrating to the right sub-structs
668	 */
669	const struct dram_info *dram_info;
670
671	/*
672	 * edram size in MB.
673	 * Cannot be determined by PCIID. You must always read a register.
674	 */
675	u32 edram_size_mb;
676
677	struct intel_uncore {
678		spinlock_t lock;
679	} uncore;
680#endif
681};
682
683/**
684 * struct xe_file - file handle for Xe driver
685 */
686struct xe_file {
687	/** @xe: xe DEVICE **/
688	struct xe_device *xe;
689
690	/** @drm: base DRM file */
691	struct drm_file *drm;
692
693	/** @vm: VM state for file */
694	struct {
695		/** @vm.xe: xarray to store VMs */
696		struct xarray xa;
697		/**
698		 * @vm.lock: Protects VM lookup + reference and removal from
699		 * file xarray. Not an intended to be an outer lock which does
700		 * thing while being held.
701		 */
702		struct mutex lock;
703	} vm;
704
705	/** @exec_queue: Submission exec queue state for file */
706	struct {
707		/** @exec_queue.xa: xarray to store exece queues */
708		struct xarray xa;
709		/**
710		 * @exec_queue.lock: Protects exec queue lookup + reference and
711		 * removal from file xarray. Not intended to be an outer lock
712		 * which does things while being held.
713		 */
714		struct mutex lock;
715		/**
716		 * @exec_queue.pending_removal: items pending to be removed to
717		 * synchronize GPU state update with ongoing query.
718		 */
719		atomic_t pending_removal;
720	} exec_queue;
721
722	/** @run_ticks: hw engine class run time in ticks for this drm client */
723	u64 run_ticks[XE_ENGINE_CLASS_MAX];
724
725	/** @client: drm client */
726	struct xe_drm_client *client;
727
728	/**
729	 * @process_name: process name for file handle, used to safely output
730	 * during error situations where xe file can outlive process
731	 */
732	char *process_name;
733
734	/**
735	 * @pid: pid for file handle, used to safely output uring error
736	 * situations where xe file can outlive process
737	 */
738	pid_t pid;
739
740	/** @refcount: ref count of this xe file */
741	struct kref refcount;
742};
743
744#endif