xe_lrc_layout.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2023 Intel Corporation
 4 */
 5
 6#ifndef _XE_LRC_LAYOUT_H_
 7#define _XE_LRC_LAYOUT_H_
 8
 9#define CTX_CONTEXT_CONTROL		(0x02 + 1)
10#define CTX_RING_HEAD			(0x04 + 1)
11#define CTX_RING_TAIL			(0x06 + 1)
12#define CTX_RING_START			(0x08 + 1)
13#define CTX_RING_CTL			(0x0a + 1)
14#define CTX_BB_PER_CTX_PTR		(0x12 + 1)
15#define CTX_CS_INDIRECT_CTX		(0x14 + 1)
16#define CTX_CS_INDIRECT_CTX_OFFSET	(0x16 + 1)
17#define CTX_TIMESTAMP			(0x22 + 1)
18#define CTX_TIMESTAMP_UDW		(0x24 + 1)
19#define CTX_INDIRECT_RING_STATE		(0x26 + 1)
20#define CTX_ACC_CTR_THOLD		(0x2a + 1)
21#define CTX_ASID			(0x2e + 1)
22#define CTX_PDP0_UDW			(0x30 + 1)
23#define CTX_PDP0_LDW			(0x32 + 1)
24
25#define CTX_LRM_INT_MASK_ENABLE		0x50
26#define CTX_INT_MASK_ENABLE_REG		(CTX_LRM_INT_MASK_ENABLE + 1)
27#define CTX_INT_MASK_ENABLE_PTR		(CTX_LRM_INT_MASK_ENABLE + 2)
28#define CTX_LRI_INT_REPORT_PTR		0x55
29#define CTX_INT_STATUS_REPORT_REG	(CTX_LRI_INT_REPORT_PTR + 1)
30#define CTX_INT_STATUS_REPORT_PTR	(CTX_LRI_INT_REPORT_PTR + 2)
31#define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)
32#define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)
33
34#define CTX_CS_INT_VEC_REG		0x5a
35#define CTX_CS_INT_VEC_DATA		(CTX_CS_INT_VEC_REG + 1)
36
37#define INDIRECT_CTX_RING_HEAD		(0x02 + 1)
38#define INDIRECT_CTX_RING_TAIL		(0x04 + 1)
39#define INDIRECT_CTX_RING_START		(0x06 + 1)
40#define INDIRECT_CTX_RING_START_UDW	(0x08 + 1)
41#define INDIRECT_CTX_RING_CTL		(0x0a + 1)
42
43#endif