xe_gt_regs.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#ifndef _XE_GT_REGS_H_
  7#define _XE_GT_REGS_H_
  8
  9#include "regs/xe_reg_defs.h"
 10
 11/*
 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
 13 * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
 15 */
 16#define MEDIA_GT_GSI_OFFSET				0x380000
 17#define MEDIA_GT_GSI_LENGTH				0x40000
 18
 19/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
 20#define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
 21#define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
 22#define   MTL_CC_MASK					REG_GENMASK(12, 9)
 23
 24/* RPM unit config (Gen8+) */
 25#define RPM_CONFIG0					XE_REG(0xd00)
 26#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
 27#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
 28#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
 29#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
 30#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
 31#define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
 32
 33#define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
 34#define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
 35#define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)
 36
 37#define GMD_ID					XE_REG(0xd8c)
 38#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
 39#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
 40/*
 41 * Spec defines these bits as "Reserved", but then make them assume some
 42 * meaning that depends on the ARCH. To avoid any confusion, call them
 43 * SUBIP_FLAG_MASK.
 44 */
 45#define   GMD_ID_SUBIP_FLAG_MASK		REG_GENMASK(13, 6)
 46#define   GMD_ID_REVID				REG_GENMASK(5, 0)
 47
 48#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
 49#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)
 50
 51#define STEER_SEMAPHORE				XE_REG(0xfd0)
 52#define MTL_MCR_SELECTOR			XE_REG(0xfd4)
 53#define SF_MCR_SELECTOR				XE_REG(0xfd8)
 54#define MCR_SELECTOR				XE_REG(0xfdc)
 55#define GAM_MCR_SELECTOR			XE_REG(0xfe0)
 56#define   MCR_MULTICAST				REG_BIT(31)
 57#define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
 58#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
 59#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
 60#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
 61#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
 62#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
 63
 64#define PS_INVOCATION_COUNT			XE_REG(0x2348)
 65
 66#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
 67#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
 68#define   LE_SSE_MASK				REG_GENMASK(18, 17)
 69#define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
 70#define   LE_COS_MASK				REG_GENMASK(16, 15)
 71#define   LE_SCF_MASK				REG_BIT(14)
 72#define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
 73#define   LE_PFM_MASK				REG_GENMASK(13, 11)
 74#define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
 75#define   LE_SCC_MASK				REG_GENMASK(10, 8)
 76#define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
 77#define   LE_RSC_MASK				REG_BIT(7)
 78#define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
 79#define   LE_AOM_MASK				REG_BIT(6)
 80#define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
 81#define   LE_LRUM_MASK				REG_GENMASK(5, 4)
 82#define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
 83#define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
 84#define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
 85#define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
 86#define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
 87
 88#define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)
 89#define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
 90
 91#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
 92#define   CG_DIS_CNTLBUS			REG_BIT(6)
 93
 94#define CCS_AUX_INV				XE_REG(0x4208)
 95
 96#define VD0_AUX_INV				XE_REG(0x4218)
 97#define VE0_AUX_INV				XE_REG(0x4238)
 98
 99#define VE1_AUX_INV				XE_REG(0x42b8)
100#define   AUX_INV				REG_BIT(0)
101
102#define XE2_LMEM_CFG				XE_REG(0x48b0)
103
104#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
105#define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
106
107#define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
108#define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
109
110#define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
111#define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
112#define   DIS_CLIP_NEGATIVE_BOUNDING_BOX	REG_BIT(6)
113
114#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
115#define   TBIMR_FAST_CLIP			REG_BIT(5)
116
117#define FF_MODE					XE_REG_MCR(0x6210)
118#define   DIS_TE_AUTOSTRIP			REG_BIT(31)
119#define   VS_HIT_MAX_VALUE_MASK			REG_GENMASK(25, 20)
120#define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)
121#define   DIS_MESH_AUTOSTRIP			REG_BIT(15)
122
123#define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
124#define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)
125#define   DIS_AUTOSTRIP				REG_BIT(6)
126#define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
127#define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
128
129#define FF_MODE2				XE_REG(0x6604)
130#define XEHP_FF_MODE2				XE_REG_MCR(0x6604)
131#define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
132#define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
133#define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
134#define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
135
136#define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)
137
138#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)
139#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
140
141#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)
142#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
143
144#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)
145#define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
146#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)
147
148#define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
149#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)
150
151#define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
152#define   FLSH_IGNORES_PSD			REG_BIT(10)
153#define   FD_END_COLLECT			REG_BIT(5)
154
155#define SC_INSTDONE				XE_REG(0x7100)
156#define SC_INSTDONE_EXTRA			XE_REG(0x7104)
157#define SC_INSTDONE_EXTRA2			XE_REG(0x7108)
158
159#define XEHPG_SC_INSTDONE			XE_REG_MCR(0x7100)
160#define XEHPG_SC_INSTDONE_EXTRA			XE_REG_MCR(0x7104)
161#define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)
162
163#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)
164#define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE	REG_BIT(12)
165#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
166
167#define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)
168#define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
169#define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
170#define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
171#define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)
172#define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)
173
174#define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
175#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
176#define   FAST_CLEAR_VALIGN_FIX			REG_BIT(13)
177
178#define XE2LPM_CCCHKNREG1			XE_REG(0x82a8)
179
180#define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)
181#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
182
183#define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)
184#define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)
185
186#define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)
187#define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
188
189#define SQCNT1					XE_REG_MCR(0x8718)
190#define XELPMP_SQCNT1				XE_REG(0x8718)
191#define   SQCNT1_PMON_ENABLE			REG_BIT(30)
192#define   SQCNT1_OABPC				REG_BIT(29)
193#define   ENFORCE_RAR				REG_BIT(23)
194
195#define XEHP_SQCM				XE_REG_MCR(0x8724)
196#define   EN_32B_ACCESS				REG_BIT(30)
197
198#define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)
199#define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)
200#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK	REG_GENMASK(31, 6)
201
202#define XE2_FLAT_CCS_BASE_RANGE_UPPER		XE_REG_MCR(0x8804)
203#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK	REG_GENMASK(7, 0)
204
205#define GSCPSMI_BASE				XE_REG(0x880c)
206
207#define CCCHKNREG1				XE_REG_MCR(0x8828)
208#define   L3CMPCTRL				REG_BIT(23)
209#define   ENCOMPPERFFIX				REG_BIT(18)
210
211/* Fuse readout registers for GT */
212#define XEHP_FUSE4				XE_REG(0x9114)
213#define   CFEG_WMTP_DISABLE			REG_BIT(20)
214#define   CCS_EN_MASK				REG_GENMASK(19, 16)
215#define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
216
217#define	MIRROR_FUSE3				XE_REG(0x9118)
218#define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)
219#define   L3BANK_PAIR_COUNT			4
220#define   XEHPC_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
221#define   XE2_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
222#define   L3BANK_MASK				REG_GENMASK(3, 0)
223#define   XELP_GT_L3_MODE_MASK			REG_GENMASK(7, 0)
224/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
225#define   MAX_MSLICES				4
226#define   MEML3_EN_MASK				REG_GENMASK(3, 0)
227
228#define MIRROR_FUSE1				XE_REG(0x911c)
229
230#define MIRROR_L3BANK_ENABLE			XE_REG(0x9130)
231#define   XE3_L3BANK_ENABLE			REG_GENMASK(31, 0)
232
233#define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
234#define   XELP_EU_MASK				REG_GENMASK(7, 0)
235#define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
236#define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
237
238#define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
239#define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)
240#define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)
241
242#define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
243#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
244#define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
245#define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
246#define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
247
248#define SERVICE_COPY_ENABLE			XE_REG(0x9170)
249#define   FUSE_SERVICE_COPY_ENABLE_MASK		REG_GENMASK(7, 0)
250
251#define GDRST					XE_REG(0x941c)
252#define   GRDOM_GUC				REG_BIT(3)
253#define   GRDOM_FULL				REG_BIT(0)
254
255#define MISCCPCTL				XE_REG(0x9424)
256#define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)
257
258#define UNSLCGCTL9430				XE_REG(0x9430)
259#define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
260
261#define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)
262#define   VFUNIT_CLKGATE_DIS			REG_BIT(20)
263#define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */
264#define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */
265#define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)
266#define   HSUNIT_CLKGATE_DIS			REG_BIT(8)
267#define   VSUNIT_CLKGATE_DIS			REG_BIT(3)
268
269#define UNSLCGCTL9440				XE_REG(0x9440)
270#define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)
271#define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)
272#define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)
273#define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)
274#define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)
275#define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)
276#define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)
277#define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)
278#define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)
279#define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)
280#define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)
281#define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)
282
283#define UNSLCGCTL9444				XE_REG(0x9444)
284#define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)
285#define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)
286#define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)
287#define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)
288#define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)
289#define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)
290#define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)
291#define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)
292#define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)
293#define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)
294#define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)
295#define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)
296#define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)
297#define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)
298#define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
299#define   LTCDD_CLKGATE_DIS			REG_BIT(10)
300
301#define UNSLCGCTL9454				XE_REG(0x9454)
302#define   LSCFE_CLKGATE_DIS			REG_BIT(4)
303
304#define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
305#define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
306#define   L3_CLKGATE_DIS			REG_BIT(16)
307#define   NODEDSS_CLKGATE_DIS			REG_BIT(12)
308#define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)
309#define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)
310#define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)
311#define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)
312
313#define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)
314#define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)
315
316#define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)
317#define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)
318#define   GWUNIT_CLKGATE_DIS			REG_BIT(16)
319
320#define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)
321#define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)
322
323#define SSMCGCTL9530				XE_REG_MCR(0x9530)
324#define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)
325
326#define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)
327#define   DFR_DISABLE				REG_BIT(9)
328
329#define RPNSWREQ				XE_REG(0xa008)
330#define   REQ_RATIO_MASK			REG_GENMASK(31, 23)
331
332#define RP_CONTROL				XE_REG(0xa024)
333#define   RPSWCTL_MASK				REG_GENMASK(10, 9)
334#define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)
335#define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)
336#define RC_CONTROL				XE_REG(0xa090)
337#define   RC_CTL_HW_ENABLE			REG_BIT(31)
338#define   RC_CTL_TO_MODE			REG_BIT(28)
339#define   RC_CTL_RC6_ENABLE			REG_BIT(18)
340#define RC_STATE				XE_REG(0xa094)
341#define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)
342#define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)
343#define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)
344
345#define PMINTRMSK				XE_REG(0xa168)
346#define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
347#define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)
348
349#define FORCEWAKE_GT				XE_REG(0xa188)
350
351#define POWERGATE_ENABLE			XE_REG(0xa210)
352#define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
353#define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
354#define   MEDIA_SAMPLERS_POWERGATE_ENABLE	REG_BIT(2)
355#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
356#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
357
358#define FORCEWAKE_RENDER			XE_REG(0xa278)
359
360#define POWERGATE_DOMAIN_STATUS			XE_REG(0xa2a0)
361#define   MEDIA_SLICE3_AWAKE_STATUS		REG_BIT(4)
362#define   MEDIA_SLICE2_AWAKE_STATUS		REG_BIT(3)
363#define   MEDIA_SLICE1_AWAKE_STATUS		REG_BIT(2)
364#define   RENDER_AWAKE_STATUS			REG_BIT(1)
365#define   MEDIA_SLICE0_AWAKE_STATUS		REG_BIT(0)
366
367#define MISC_STATUS_0				XE_REG(0xa500)
368
369#define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)
370#define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
371#define FORCEWAKE_GSC				XE_REG(0xa618)
372
373#define XELP_GARBCNTL				XE_REG(0xb004)
374#define   XELP_BUS_HASH_CTL_BIT_EXC		REG_BIT(7)
375
376#define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
377#define   XEHPC_OVRLSCCC			REG_BIT(0)
378
379#define LNCFCMOCS_REG_COUNT			32
380#define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
381#define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
382#define   L3_UPPER_LKUP_MASK			REG_BIT(23)
383#define   L3_UPPER_GLBGO_MASK			REG_BIT(22)
384#define   L3_UPPER_IDX_CACHEABILITY_MASK	REG_GENMASK(21, 20)
385#define   L3_UPPER_IDX_SCC_MASK			REG_GENMASK(19, 17)
386#define   L3_UPPER_IDX_ESC_MASK			REG_BIT(16)
387#define   L3_LKUP_MASK				REG_BIT(7)
388#define   L3_LKUP(value)			REG_FIELD_PREP(L3_LKUP_MASK, value)
389#define   L3_GLBGO_MASK				REG_BIT(6)
390#define   L3_GLBGO(value)			REG_FIELD_PREP(L3_GLBGO_MASK, value)
391#define   L3_CACHEABILITY_MASK			REG_GENMASK(5, 4)
392#define   L3_CACHEABILITY(value)		REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
393#define   L3_SCC_MASK				REG_GENMASK(3, 1)
394#define   L3_SCC(value)				REG_FIELD_PREP(L3_SCC_MASK, value)
395#define   L3_ESC_MASK				REG_BIT(0)
396#define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
397
398#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
399#define   XEHP_LNESPARE				REG_BIT(19)
400
401#define LSN_VC_REG2				XE_REG_MCR(0xb0c8)
402#define   LSN_LNI_WGT_MASK			REG_GENMASK(31, 28)
403#define   LSN_LNI_WGT(value)			REG_FIELD_PREP(LSN_LNI_WGT_MASK, value)
404#define   LSN_LNE_WGT_MASK			REG_GENMASK(27, 24)
405#define   LSN_LNE_WGT(value)			REG_FIELD_PREP(LSN_LNE_WGT_MASK, value)
406#define   LSN_DIM_X_WGT_MASK			REG_GENMASK(23, 20)
407#define   LSN_DIM_X_WGT(value)			REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value)
408#define   LSN_DIM_Y_WGT_MASK			REG_GENMASK(19, 16)
409#define   LSN_DIM_Y_WGT(value)			REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value)
410#define   LSN_DIM_Z_WGT_MASK			REG_GENMASK(15, 12)
411#define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
412
413#define L3SQCREG2				XE_REG_MCR(0xb104)
414#define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
415
416#define L3SQCREG3				XE_REG_MCR(0xb108)
417#define   COMPPWOVERFETCHEN			REG_BIT(28)
418
419#define SCRATCH3_LBCF				XE_REG_MCR(0xb154)
420#define   RWFLUSHALLEN				REG_BIT(17)
421
422#define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
423#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
424
425#define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)
426#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
427
428#define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
429
430#define XE2_GLOBAL_INVAL			XE_REG(0xb404)
431
432#define XE2LPM_L3SQCREG2			XE_REG_MCR(0xb604)
433
434#define XE2LPM_L3SQCREG3			XE_REG_MCR(0xb608)
435
436#define XE2LPM_SCRATCH3_LBCF			XE_REG_MCR(0xb654)
437
438#define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
439
440#define XE2_TDF_CTRL				XE_REG(0xb418)
441#define   TRANSIENT_FLUSH_REQUEST		REG_BIT(0)
442
443#define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
444#define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
445#define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
446#define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
447#define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
448#define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
449#define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
450#define   FORCE_MISS_FTLB			REG_BIT(3)
451
452#define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
453#define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
454#define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
455#define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
456
457#define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)
458#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
459#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
460
461#define LMEM_CFG				XE_REG(0xcf58)
462#define   LMEM_EN				REG_BIT(31)
463#define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */
464
465#define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
466#define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
467
468#define SAMPLER_INSTDONE			XE_REG_MCR(0xe160)
469#define ROW_INSTDONE				XE_REG_MCR(0xe164)
470
471#define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
472#define   ENABLE_SMALLPL			REG_BIT(15)
473#define   SMP_WAIT_FETCH_MERGING_COUNTER	REG_GENMASK(11, 10)
474#define   SMP_FORCE_128B_OVERFETCH		REG_FIELD_PREP(SMP_WAIT_FETCH_MERGING_COUNTER, 1)
475#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
476#define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
477#define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
478
479#define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
480#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
481#define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
482
483#define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
484#define   DISABLE_ECC				REG_BIT(5)
485#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
486
487#define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
488#define   DISABLE_GRF_CLEAR			REG_BIT(13)
489#define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)
490#define   DISABLE_TDL_PUSH			REG_BIT(9)
491#define   DIS_PICK_2ND_EU			REG_BIT(7)
492#define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
493#define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
494#define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
495
496#define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
497#define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
498#define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
499
500#define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
501#define   STK_ID_RESTRICT			REG_BIT(12)
502#define   SLM_WMTP_RESTORE			REG_BIT(11)
503#define   RES_CHK_SPR_DIS			REG_BIT(6)
504
505#define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
506#define   UGM_BACKUP_MODE			REG_BIT(13)
507#define   MDQ_ARBITRATION_MODE			REG_BIT(12)
508#define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
509#define   EARLY_EOT_DIS				REG_BIT(1)
510
511#define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
512#define   DISABLE_READ_SUPPRESSION		REG_BIT(15)
513#define   DISABLE_EARLY_READ			REG_BIT(14)
514#define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)
515#define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)
516#define   DISABLE_TDL_SVHS_GATING		REG_BIT(1)
517#define   DISABLE_DOP_GATING			REG_BIT(0)
518
519#define RT_CTRL					XE_REG_MCR(0xe530)
520#define   DIS_NULL_QUERY			REG_BIT(10)
521
522#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
523#define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
524
525#define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
526#define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
527#define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
528
529#define TDL_CHICKEN				XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
530#define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE	REG_BIT(12)
531#define   EUSTALL_PERF_SAMPLING_DISABLE		REG_BIT(5)
532
533#define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
534#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
535#define   WR_REQ_CHAINING_DIS			REG_BIT(26)
536#define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
537#define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
538#define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)
539
540#define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)
541#define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
542#define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
543#define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
544#define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
545#define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
546#define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
547#define   L3_128B_256B_WRT_DIS			REG_BIT(40 - 32)
548#define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
549#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
550
551#define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
552#define   COMP_CKN_IN				REG_GENMASK(30, 29)
553
554#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
555#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
556
557#define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
558#define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
559#define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
560
561/*
562 * Total of 4 cslices, where each cslice is in the form:
563 *   [0-3]     CCS ID
564 *   [4-6]     RSVD
565 *   [7]       Disabled
566 */
567#define CCS_MODE				XE_REG(0x14804, XE_REG_OPTION_MASKED)
568#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
569#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
570#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
571#define   CCS_MODE_CSLICE(cslice, ccs) \
572	((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
573
574#define FORCEWAKE_ACK_GT			XE_REG(0x130044)
575
576/* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
577#define   FORCEWAKE_KERNEL			0
578#define   FORCEWAKE_MT(bit)			BIT(bit)
579#define   FORCEWAKE_MT_MASK(bit)		BIT((bit) + 16)
580
581#define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
582#define MTL_MEDIA_MC6				XE_REG(0x138048)
583
584#define GT_CORE_STATUS				XE_REG(0x138060)
585#define   RCN_MASK				REG_GENMASK(2, 0)
586#define   GT_C0					0
587#define   GT_C6					3
588
589#define GT_GFX_RC6_LOCKED			XE_REG(0x138104)
590#define GT_GFX_RC6				XE_REG(0x138108)
591
592#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
593/* Common performance limit reason bits - available on all platforms */
594#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
595#define   PROCHOT_MASK				REG_BIT(0)
596#define   THERMAL_LIMIT_MASK			REG_BIT(1)
597#define   RATL_MASK				REG_BIT(5)
598#define   VR_THERMALERT_MASK			REG_BIT(6)
599#define   VR_TDC_MASK				REG_BIT(7)
600#define   POWER_LIMIT_4_MASK			REG_BIT(8)
601#define   POWER_LIMIT_1_MASK			REG_BIT(10)
602#define   POWER_LIMIT_2_MASK			REG_BIT(11)
603/* Platform-specific performance limit reason bits - for Crescent Island */
604#define   CRI_PERF_LIMIT_REASONS_MASK		0xfdff
605#define   SOC_THERMAL_LIMIT_MASK		REG_BIT(1)
606#define   MEM_THERMAL_MASK			REG_BIT(2)
607#define   VR_THERMAL_MASK			REG_BIT(3)
608#define   ICCMAX_MASK				REG_BIT(4)
609#define   SOC_AVG_THERMAL_MASK			REG_BIT(6)
610#define   FASTVMODE_MASK			REG_BIT(7)
611#define   PSYS_PL1_MASK				REG_BIT(12)
612#define   PSYS_PL2_MASK				REG_BIT(13)
613#define   P0_FREQ_MASK				REG_BIT(14)
614#define   PSYS_CRIT_MASK			REG_BIT(15)
615
616#define GT_PERF_STATUS				XE_REG(0x1381b4)
617#define   VOLTAGE_MASK				REG_GENMASK(10, 0)
618
619#define SFC_DONE(n)				XE_REG(0x1cc000 + (n) * 0x1000)
620
621#endif