xe_gsc_regs.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2023 Intel Corporation
 4 */
 5
 6#ifndef _XE_GSC_REGS_H_
 7#define _XE_GSC_REGS_H_
 8
 9#include <linux/compiler.h>
10#include <linux/types.h>
11
12#include "regs/xe_reg_defs.h"
13
14/* Definitions of GSC H/W registers, bits, etc */
15
16#define BMG_GSC_HECI1_BASE	0x373000
17
18#define MTL_GSC_HECI1_BASE	0x00116000
19#define MTL_GSC_HECI2_BASE	0x00117000
20
21#define DG1_GSC_HECI2_BASE	0x00259000
22#define PVC_GSC_HECI2_BASE	0x00285000
23#define DG2_GSC_HECI2_BASE	0x00374000
24
25#define HECI_H_CSR(base)	XE_REG((base) + 0x4)
26#define   HECI_H_CSR_IE		REG_BIT(0)
27#define   HECI_H_CSR_IS		REG_BIT(1)
28#define   HECI_H_CSR_IG		REG_BIT(2)
29#define   HECI_H_CSR_RDY	REG_BIT(3)
30#define   HECI_H_CSR_RST	REG_BIT(4)
31
32/*
33 * The FWSTS register values are FW defined and can be different between
34 * HECI1 and HECI2
35 */
36#define HECI_FWSTS1(base)				XE_REG((base) + 0xc40)
37#define   HECI1_FWSTS1_CURRENT_STATE			REG_GENMASK(3, 0)
38#define   HECI1_FWSTS1_CURRENT_STATE_RESET		0
39#define   HECI1_FWSTS1_PROXY_STATE_NORMAL		5
40#define   HECI1_FWSTS1_INIT_COMPLETE			REG_BIT(9)
41#define HECI_FWSTS2(base)				XE_REG((base) + 0xc48)
42#define HECI_FWSTS3(base)				XE_REG((base) + 0xc60)
43#define HECI_FWSTS4(base)				XE_REG((base) + 0xc64)
44#define HECI_FWSTS5(base)				XE_REG((base) + 0xc68)
45#define   HECI1_FWSTS5_HUC_AUTH_DONE			REG_BIT(19)
46#define HECI_FWSTS6(base)				XE_REG((base) + 0xc6c)
47
48#define HECI_H_GS1(base)	XE_REG((base) + 0xc4c)
49#define   HECI_H_GS1_ER_PREP	REG_BIT(0)
50
51#define GSCI_TIMER_STATUS				XE_REG(0x11ca28)
52#define   GSCI_TIMER_STATUS_VALUE			REG_GENMASK(1, 0)
53#define   GSCI_TIMER_STATUS_RESET_IN_PROGRESS		0
54#define   GSCI_TIMER_STATUS_TIMER_EXPIRED		1
55#define   GSCI_TIMER_STATUS_RESET_COMPLETE		2
56#define   GSCI_TIMER_STATUS_OUT_OF_RESET		3
57
58#endif