xe_alu_commands.h

 1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2025 Intel Corporation
 4 */
 5
 6#ifndef _XE_ALU_COMMANDS_H_
 7#define _XE_ALU_COMMANDS_H_
 8
 9#include "instructions/xe_instr_defs.h"
10
11/* Instruction Opcodes */
12#define CS_ALU_OPCODE_NOOP			0x000
13#define CS_ALU_OPCODE_FENCE_RD			0x001
14#define CS_ALU_OPCODE_FENCE_WR			0x002
15#define CS_ALU_OPCODE_LOAD			0x080
16#define CS_ALU_OPCODE_LOADINV			0x480
17#define CS_ALU_OPCODE_LOAD0			0x081
18#define CS_ALU_OPCODE_LOAD1			0x481
19#define CS_ALU_OPCODE_LOADIND			0x082
20#define CS_ALU_OPCODE_ADD			0x100
21#define CS_ALU_OPCODE_SUB			0x101
22#define CS_ALU_OPCODE_AND			0x102
23#define CS_ALU_OPCODE_OR			0x103
24#define CS_ALU_OPCODE_XOR			0x104
25#define CS_ALU_OPCODE_SHL			0x105
26#define CS_ALU_OPCODE_SHR			0x106
27#define CS_ALU_OPCODE_SAR			0x107
28#define CS_ALU_OPCODE_STORE			0x180
29#define CS_ALU_OPCODE_STOREINV			0x580
30#define CS_ALU_OPCODE_STOREIND			0x181
31
32/* Instruction Operands */
33#define CS_ALU_OPERAND_REG(n)			REG_FIELD_PREP(GENMASK(3, 0), (n))
34#define CS_ALU_OPERAND_REG0			0x0
35#define CS_ALU_OPERAND_REG1			0x1
36#define CS_ALU_OPERAND_REG2			0x2
37#define CS_ALU_OPERAND_REG3			0x3
38#define CS_ALU_OPERAND_REG4			0x4
39#define CS_ALU_OPERAND_REG5			0x5
40#define CS_ALU_OPERAND_REG6			0x6
41#define CS_ALU_OPERAND_REG7			0x7
42#define CS_ALU_OPERAND_REG8			0x8
43#define CS_ALU_OPERAND_REG9			0x9
44#define CS_ALU_OPERAND_REG10			0xa
45#define CS_ALU_OPERAND_REG11			0xb
46#define CS_ALU_OPERAND_REG12			0xc
47#define CS_ALU_OPERAND_REG13			0xd
48#define CS_ALU_OPERAND_REG14			0xe
49#define CS_ALU_OPERAND_REG15			0xf
50#define CS_ALU_OPERAND_SRCA			0x20
51#define CS_ALU_OPERAND_SRCB			0x21
52#define CS_ALU_OPERAND_ACCU			0x31
53#define CS_ALU_OPERAND_ZF			0x32
54#define CS_ALU_OPERAND_CF			0x33
55#define CS_ALU_OPERAND_NA			0 /* N/A operand */
56
57/* Command Streamer ALU Instructions */
58#define CS_ALU_INSTR(opcode, op1, op2)		(REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \
59						 REG_FIELD_PREP(GENMASK(19, 10), (op1)) | \
60						 REG_FIELD_PREP(GENMASK(9, 0), (op2)))
61
62#define __CS_ALU_INSTR(opcode, op1, op2)	CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \
63							     CS_ALU_OPERAND_##op1, \
64							     CS_ALU_OPERAND_##op2)
65
66#define CS_ALU_INSTR_NOOP			__CS_ALU_INSTR(NOOP, NA, NA)
67#define CS_ALU_INSTR_LOAD(op1, op2)		__CS_ALU_INSTR(LOAD, op1, op2)
68#define CS_ALU_INSTR_LOADINV(op1, op2)		__CS_ALU_INSTR(LOADINV, op1, op2)
69#define CS_ALU_INSTR_LOAD0(op1)			__CS_ALU_INSTR(LOAD0, op1, NA)
70#define CS_ALU_INSTR_LOAD1(op1)			__CS_ALU_INSTR(LOAD1, op1, NA)
71#define CS_ALU_INSTR_ADD			__CS_ALU_INSTR(ADD, NA, NA)
72#define CS_ALU_INSTR_SUB			__CS_ALU_INSTR(SUB, NA, NA)
73#define CS_ALU_INSTR_AND			__CS_ALU_INSTR(AND, NA, NA)
74#define CS_ALU_INSTR_OR				__CS_ALU_INSTR(OR, NA, NA)
75#define CS_ALU_INSTR_XOR			__CS_ALU_INSTR(XOR, NA, NA)
76#define CS_ALU_INSTR_STORE(op1, op2)		__CS_ALU_INSTR(STORE, op1, op2)
77#define CS_ALU_INSTR_STOREINV(op1, op2)		__CS_ALU_INSTR(STOREINV, op1, op2)
78
79#endif