intel_uncore.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_UNCORE_H__
  7#define __INTEL_UNCORE_H__
  8
  9#include "xe_device.h"
 10#include "xe_device_types.h"
 11#include "xe_mmio.h"
 12
 13#define FORCEWAKE_ALL XE_FORCEWAKE_ALL
 14
 15static inline struct intel_uncore *to_intel_uncore(struct drm_device *drm)
 16{
 17	return &to_xe_device(drm)->uncore;
 18}
 19
 20static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncore)
 21{
 22	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
 23
 24	return xe_root_tile_mmio(xe);
 25}
 26
 27static inline u32 intel_uncore_read(struct intel_uncore *uncore,
 28				    i915_reg_t i915_reg)
 29{
 30	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 31
 32	return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
 33}
 34
 35static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
 36				    i915_reg_t i915_reg)
 37{
 38	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 39
 40	return xe_mmio_read8(__compat_uncore_to_mmio(uncore), reg);
 41}
 42
 43static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
 44				      i915_reg_t i915_reg)
 45{
 46	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 47
 48	return xe_mmio_read16(__compat_uncore_to_mmio(uncore), reg);
 49}
 50
 51static inline u64
 52intel_uncore_read64_2x32(struct intel_uncore *uncore,
 53			 i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
 54{
 55	struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
 56	struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
 57	u32 upper, lower, old_upper;
 58	int loop = 0;
 59
 60	upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
 61	do {
 62		old_upper = upper;
 63		lower = xe_mmio_read32(__compat_uncore_to_mmio(uncore), lower_reg);
 64		upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
 65	} while (upper != old_upper && loop++ < 2);
 66
 67	return (u64)upper << 32 | lower;
 68}
 69
 70static inline void intel_uncore_posting_read(struct intel_uncore *uncore,
 71					     i915_reg_t i915_reg)
 72{
 73	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 74
 75	xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
 76}
 77
 78static inline void intel_uncore_write(struct intel_uncore *uncore,
 79				      i915_reg_t i915_reg, u32 val)
 80{
 81	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 82
 83	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
 84}
 85
 86static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
 87				   i915_reg_t i915_reg, u32 clear, u32 set)
 88{
 89	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
 90
 91	return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);
 92}
 93
 94static inline int
 95__intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
 96			  u32 mask, u32 value, unsigned int fast_timeout_us,
 97			  unsigned int slow_timeout_ms, u32 *out_value)
 98{
 99	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
100	bool atomic;
101
102	/*
103	 * Replicate the behavior from i915 here, in which sleep is not
104	 * performed if slow_timeout_ms == 0. This is necessary because
105	 * of some paths in display code where waits are done in atomic
106	 * context.
107	 */
108	atomic = !slow_timeout_ms && fast_timeout_us > 0;
109
110	return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
111			      fast_timeout_us + 1000 * slow_timeout_ms,
112			      out_value, atomic);
113}
114
115static inline int
116__intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t i915_reg,
117			     u32 mask, u32 value, unsigned int fast_timeout_us,
118			     unsigned int slow_timeout_ms, u32 *out_value)
119{
120	return __intel_wait_for_register(uncore, i915_reg, mask, value,
121					 fast_timeout_us, slow_timeout_ms,
122					 out_value);
123}
124
125static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
126				       i915_reg_t i915_reg)
127{
128	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
129
130	return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
131}
132
133static inline void intel_uncore_write_fw(struct intel_uncore *uncore,
134					 i915_reg_t i915_reg, u32 val)
135{
136	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
137
138	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
139}
140
141static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,
142					    i915_reg_t i915_reg)
143{
144	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
145
146	return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
147}
148
149static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,
150					      i915_reg_t i915_reg, u32 val)
151{
152	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
153
154	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
155}
156
157#define intel_uncore_forcewake_get(x, y) do { } while (0)
158#define intel_uncore_forcewake_put(x, y) do { } while (0)
159
160#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0)
161
162#endif /* __INTEL_UNCORE_H__ */