vc4_v3d.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  4 * Copyright (C) 2013 Red Hat
  5 * Author: Rob Clark <robdclark@gmail.com>
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/component.h>
 10#include <linux/platform_device.h>
 11#include <linux/pm_runtime.h>
 12
 13#include <drm/drm_print.h>
 14
 15#include "vc4_drv.h"
 16#include "vc4_regs.h"
 17
 18static const struct debugfs_reg32 v3d_regs[] = {
 19	VC4_REG32(V3D_IDENT0),
 20	VC4_REG32(V3D_IDENT1),
 21	VC4_REG32(V3D_IDENT2),
 22	VC4_REG32(V3D_SCRATCH),
 23	VC4_REG32(V3D_L2CACTL),
 24	VC4_REG32(V3D_SLCACTL),
 25	VC4_REG32(V3D_INTCTL),
 26	VC4_REG32(V3D_INTENA),
 27	VC4_REG32(V3D_INTDIS),
 28	VC4_REG32(V3D_CT0CS),
 29	VC4_REG32(V3D_CT1CS),
 30	VC4_REG32(V3D_CT0EA),
 31	VC4_REG32(V3D_CT1EA),
 32	VC4_REG32(V3D_CT0CA),
 33	VC4_REG32(V3D_CT1CA),
 34	VC4_REG32(V3D_CT00RA0),
 35	VC4_REG32(V3D_CT01RA0),
 36	VC4_REG32(V3D_CT0LC),
 37	VC4_REG32(V3D_CT1LC),
 38	VC4_REG32(V3D_CT0PC),
 39	VC4_REG32(V3D_CT1PC),
 40	VC4_REG32(V3D_PCS),
 41	VC4_REG32(V3D_BFC),
 42	VC4_REG32(V3D_RFC),
 43	VC4_REG32(V3D_BPCA),
 44	VC4_REG32(V3D_BPCS),
 45	VC4_REG32(V3D_BPOA),
 46	VC4_REG32(V3D_BPOS),
 47	VC4_REG32(V3D_BXCF),
 48	VC4_REG32(V3D_SQRSV0),
 49	VC4_REG32(V3D_SQRSV1),
 50	VC4_REG32(V3D_SQCNTL),
 51	VC4_REG32(V3D_SRQPC),
 52	VC4_REG32(V3D_SRQUA),
 53	VC4_REG32(V3D_SRQUL),
 54	VC4_REG32(V3D_SRQCS),
 55	VC4_REG32(V3D_VPACNTL),
 56	VC4_REG32(V3D_VPMBASE),
 57	VC4_REG32(V3D_PCTRC),
 58	VC4_REG32(V3D_PCTRE),
 59	VC4_REG32(V3D_PCTR(0)),
 60	VC4_REG32(V3D_PCTRS(0)),
 61	VC4_REG32(V3D_PCTR(1)),
 62	VC4_REG32(V3D_PCTRS(1)),
 63	VC4_REG32(V3D_PCTR(2)),
 64	VC4_REG32(V3D_PCTRS(2)),
 65	VC4_REG32(V3D_PCTR(3)),
 66	VC4_REG32(V3D_PCTRS(3)),
 67	VC4_REG32(V3D_PCTR(4)),
 68	VC4_REG32(V3D_PCTRS(4)),
 69	VC4_REG32(V3D_PCTR(5)),
 70	VC4_REG32(V3D_PCTRS(5)),
 71	VC4_REG32(V3D_PCTR(6)),
 72	VC4_REG32(V3D_PCTRS(6)),
 73	VC4_REG32(V3D_PCTR(7)),
 74	VC4_REG32(V3D_PCTRS(7)),
 75	VC4_REG32(V3D_PCTR(8)),
 76	VC4_REG32(V3D_PCTRS(8)),
 77	VC4_REG32(V3D_PCTR(9)),
 78	VC4_REG32(V3D_PCTRS(9)),
 79	VC4_REG32(V3D_PCTR(10)),
 80	VC4_REG32(V3D_PCTRS(10)),
 81	VC4_REG32(V3D_PCTR(11)),
 82	VC4_REG32(V3D_PCTRS(11)),
 83	VC4_REG32(V3D_PCTR(12)),
 84	VC4_REG32(V3D_PCTRS(12)),
 85	VC4_REG32(V3D_PCTR(13)),
 86	VC4_REG32(V3D_PCTRS(13)),
 87	VC4_REG32(V3D_PCTR(14)),
 88	VC4_REG32(V3D_PCTRS(14)),
 89	VC4_REG32(V3D_PCTR(15)),
 90	VC4_REG32(V3D_PCTRS(15)),
 91	VC4_REG32(V3D_DBGE),
 92	VC4_REG32(V3D_FDBGO),
 93	VC4_REG32(V3D_FDBGB),
 94	VC4_REG32(V3D_FDBGR),
 95	VC4_REG32(V3D_FDBGS),
 96	VC4_REG32(V3D_ERRSTAT),
 97};
 98
 99static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
100{
101	struct drm_debugfs_entry *entry = m->private;
102	struct drm_device *dev = entry->dev;
103	struct vc4_dev *vc4 = to_vc4_dev(dev);
104	int ret = vc4_v3d_pm_get(vc4);
105
106	if (ret == 0) {
107		uint32_t ident1 = V3D_READ(V3D_IDENT1);
108		uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
109		uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
110		uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
111
112		seq_printf(m, "Revision:   %d\n",
113			   VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
114		seq_printf(m, "Slices:     %d\n", nslc);
115		seq_printf(m, "TMUs:       %d\n", nslc * tups);
116		seq_printf(m, "QPUs:       %d\n", nslc * qups);
117		seq_printf(m, "Semaphores: %d\n",
118			   VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
119		vc4_v3d_pm_put(vc4);
120	}
121
122	return 0;
123}
124
125/*
126 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably
127 * get the pm_runtime refcount to 0 in vc4_reset().
128 */
129int
130vc4_v3d_pm_get(struct vc4_dev *vc4)
131{
132	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
133		return -ENODEV;
134
135	mutex_lock(&vc4->power_lock);
136	if (vc4->power_refcount++ == 0) {
137		int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
138
139		if (ret < 0) {
140			vc4->power_refcount--;
141			mutex_unlock(&vc4->power_lock);
142			return ret;
143		}
144	}
145	mutex_unlock(&vc4->power_lock);
146
147	return 0;
148}
149
150void
151vc4_v3d_pm_put(struct vc4_dev *vc4)
152{
153	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
154		return;
155
156	mutex_lock(&vc4->power_lock);
157	if (--vc4->power_refcount == 0) {
158		pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
159		pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
160	}
161	mutex_unlock(&vc4->power_lock);
162}
163
164static void vc4_v3d_init_hw(struct drm_device *dev)
165{
166	struct vc4_dev *vc4 = to_vc4_dev(dev);
167
168	/* Take all the memory that would have been reserved for user
169	 * QPU programs, since we don't have an interface for running
170	 * them, anyway.
171	 */
172	V3D_WRITE(V3D_VPMBASE, 0);
173}
174
175int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
176{
177	struct drm_device *dev = &vc4->base;
178	unsigned long irqflags;
179	int slot;
180	uint64_t seqno = 0;
181	struct vc4_exec_info *exec;
182
183	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
184		return -ENODEV;
185
186try_again:
187	spin_lock_irqsave(&vc4->job_lock, irqflags);
188	slot = ffs(~vc4->bin_alloc_used);
189	if (slot != 0) {
190		/* Switch from ffs() bit index to a 0-based index. */
191		slot--;
192		vc4->bin_alloc_used |= BIT(slot);
193		spin_unlock_irqrestore(&vc4->job_lock, irqflags);
194		return slot;
195	}
196
197	/* Couldn't find an open slot.  Wait for render to complete
198	 * and try again.
199	 */
200	exec = vc4_last_render_job(vc4);
201	if (exec)
202		seqno = exec->seqno;
203	spin_unlock_irqrestore(&vc4->job_lock, irqflags);
204
205	if (seqno) {
206		int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true);
207
208		if (ret == 0)
209			goto try_again;
210
211		return ret;
212	}
213
214	return -ENOMEM;
215}
216
217/*
218 * bin_bo_alloc() - allocates the memory that will be used for
219 * tile binning.
220 *
221 * The binner has a limitation that the addresses in the tile state
222 * buffer that point into the tile alloc buffer or binner overflow
223 * memory only have 28 bits (256MB), and the top 4 on the bus for
224 * tile alloc references end up coming from the tile state buffer's
225 * address.
226 *
227 * To work around this, we allocate a single large buffer while V3D is
228 * in use, make sure that it has the top 4 bits constant across its
229 * entire extent, and then put the tile state, tile alloc, and binner
230 * overflow memory inside that buffer.
231 *
232 * This creates a limitation where we may not be able to execute a job
233 * if it doesn't fit within the buffer that we allocated up front.
234 * However, it turns out that 16MB is "enough for anybody", and
235 * real-world applications run into allocation failures from the
236 * overall DMA pool before they make scenes complicated enough to run
237 * out of bin space.
238 */
239static int bin_bo_alloc(struct vc4_dev *vc4)
240{
241	struct vc4_v3d *v3d = vc4->v3d;
242	uint32_t size = 16 * 1024 * 1024;
243	int ret = 0;
244	struct list_head list;
245
246	if (!v3d)
247		return -ENODEV;
248
249	/* We may need to try allocating more than once to get a BO
250	 * that doesn't cross 256MB.  Track the ones we've allocated
251	 * that failed so far, so that we can free them when we've got
252	 * one that succeeded (if we freed them right away, our next
253	 * allocation would probably be the same chunk of memory).
254	 */
255	INIT_LIST_HEAD(&list);
256
257	while (true) {
258		struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true,
259						  VC4_BO_TYPE_BIN);
260
261		if (IS_ERR(bo)) {
262			ret = PTR_ERR(bo);
263
264			dev_err(&v3d->pdev->dev,
265				"Failed to allocate memory for tile binning: "
266				"%d. You may need to enable DMA or give it "
267				"more memory.",
268				ret);
269			break;
270		}
271
272		/* Check if this BO won't trigger the addressing bug. */
273		if ((bo->base.dma_addr & 0xf0000000) ==
274		    ((bo->base.dma_addr + bo->base.base.size - 1) & 0xf0000000)) {
275			vc4->bin_bo = bo;
276
277			/* Set up for allocating 512KB chunks of
278			 * binner memory.  The biggest allocation we
279			 * need to do is for the initial tile alloc +
280			 * tile state buffer.  We can render to a
281			 * maximum of ((2048*2048) / (32*32) = 4096
282			 * tiles in a frame (until we do floating
283			 * point rendering, at which point it would be
284			 * 8192).  Tile state is 48b/tile (rounded to
285			 * a page), and tile alloc is 32b/tile
286			 * (rounded to a page), plus a page of extra,
287			 * for a total of 320kb for our worst-case.
288			 * We choose 512kb so that it divides evenly
289			 * into our 16MB, and the rest of the 512kb
290			 * will be used as storage for the overflow
291			 * from the initial 32b CL per bin.
292			 */
293			vc4->bin_alloc_size = 512 * 1024;
294			vc4->bin_alloc_used = 0;
295			vc4->bin_alloc_overflow = 0;
296			WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
297				     bo->base.base.size / vc4->bin_alloc_size);
298
299			kref_init(&vc4->bin_bo_kref);
300
301			/* Enable the out-of-memory interrupt to set our
302			 * newly-allocated binner BO, potentially from an
303			 * already-pending-but-masked interrupt.
304			 */
305			V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
306
307			break;
308		}
309
310		/* Put it on the list to free later, and try again. */
311		list_add(&bo->unref_head, &list);
312	}
313
314	/* Free all the BOs we allocated but didn't choose. */
315	while (!list_empty(&list)) {
316		struct vc4_bo *bo = list_last_entry(&list,
317						    struct vc4_bo, unref_head);
318
319		list_del(&bo->unref_head);
320		drm_gem_object_put(&bo->base.base);
321	}
322
323	return ret;
324}
325
326int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used)
327{
328	int ret = 0;
329
330	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
331		return -ENODEV;
332
333	mutex_lock(&vc4->bin_bo_lock);
334
335	if (used && *used)
336		goto complete;
337
338	if (vc4->bin_bo)
339		kref_get(&vc4->bin_bo_kref);
340	else
341		ret = bin_bo_alloc(vc4);
342
343	if (ret == 0 && used)
344		*used = true;
345
346complete:
347	mutex_unlock(&vc4->bin_bo_lock);
348
349	return ret;
350}
351
352static void bin_bo_release(struct kref *ref)
353{
354	struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref);
355
356	if (WARN_ON_ONCE(!vc4->bin_bo))
357		return;
358
359	drm_gem_object_put(&vc4->bin_bo->base.base);
360	vc4->bin_bo = NULL;
361}
362
363void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
364{
365	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
366		return;
367
368	mutex_lock(&vc4->bin_bo_lock);
369	kref_put(&vc4->bin_bo_kref, bin_bo_release);
370	mutex_unlock(&vc4->bin_bo_lock);
371}
372
373#ifdef CONFIG_PM
374static int vc4_v3d_runtime_suspend(struct device *dev)
375{
376	struct vc4_v3d *v3d = dev_get_drvdata(dev);
377	struct vc4_dev *vc4 = v3d->vc4;
378
379	vc4_irq_disable(&vc4->base);
380
381	clk_disable_unprepare(v3d->clk);
382
383	return 0;
384}
385
386static int vc4_v3d_runtime_resume(struct device *dev)
387{
388	struct vc4_v3d *v3d = dev_get_drvdata(dev);
389	struct vc4_dev *vc4 = v3d->vc4;
390	int ret;
391
392	ret = clk_prepare_enable(v3d->clk);
393	if (ret != 0)
394		return ret;
395
396	vc4_v3d_init_hw(&vc4->base);
397
398	vc4_irq_enable(&vc4->base);
399
400	return 0;
401}
402#endif
403
404int vc4_v3d_debugfs_init(struct drm_minor *minor)
405{
406	struct drm_device *drm = minor->dev;
407	struct vc4_dev *vc4 = to_vc4_dev(drm);
408	struct vc4_v3d *v3d = vc4->v3d;
409
410	if (!vc4->v3d)
411		return -ENODEV;
412
413	drm_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL);
414
415	vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset);
416
417	return 0;
418}
419
420static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
421{
422	struct platform_device *pdev = to_platform_device(dev);
423	struct drm_device *drm = dev_get_drvdata(master);
424	struct vc4_dev *vc4 = to_vc4_dev(drm);
425	struct vc4_v3d *v3d = NULL;
426	int ret;
427
428	v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
429	if (!v3d)
430		return -ENOMEM;
431
432	dev_set_drvdata(dev, v3d);
433
434	v3d->pdev = pdev;
435
436	v3d->regs = vc4_ioremap_regs(pdev, 0);
437	if (IS_ERR(v3d->regs))
438		return PTR_ERR(v3d->regs);
439	v3d->regset.base = v3d->regs;
440	v3d->regset.regs = v3d_regs;
441	v3d->regset.nregs = ARRAY_SIZE(v3d_regs);
442
443	vc4->v3d = v3d;
444	v3d->vc4 = vc4;
445
446	v3d->clk = devm_clk_get_optional(dev, NULL);
447	if (IS_ERR(v3d->clk))
448		return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
449
450	ret = platform_get_irq(pdev, 0);
451	if (ret < 0)
452		return ret;
453	vc4->irq = ret;
454
455	ret = devm_pm_runtime_enable(dev);
456	if (ret)
457		return ret;
458
459	ret = pm_runtime_resume_and_get(dev);
460	if (ret)
461		return ret;
462
463	if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
464		drm_err(drm, "V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
465			V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
466		ret = -EINVAL;
467		goto err_put_runtime_pm;
468	}
469
470	/* Reset the binner overflow address/size at setup, to be sure
471	 * we don't reuse an old one.
472	 */
473	V3D_WRITE(V3D_BPOA, 0);
474	V3D_WRITE(V3D_BPOS, 0);
475
476	ret = vc4_irq_install(drm, vc4->irq);
477	if (ret) {
478		drm_err(drm, "Failed to install IRQ handler\n");
479		goto err_put_runtime_pm;
480	}
481
482	pm_runtime_use_autosuspend(dev);
483	pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
484	pm_runtime_put_autosuspend(dev);
485
486	return 0;
487
488err_put_runtime_pm:
489	pm_runtime_put(dev);
490
491	return ret;
492}
493
494static void vc4_v3d_unbind(struct device *dev, struct device *master,
495			   void *data)
496{
497	struct drm_device *drm = dev_get_drvdata(master);
498	struct vc4_dev *vc4 = to_vc4_dev(drm);
499
500	vc4_irq_uninstall(drm);
501
502	/* Disable the binner's overflow memory address, so the next
503	 * driver probe (if any) doesn't try to reuse our old
504	 * allocation.
505	 */
506	V3D_WRITE(V3D_BPOA, 0);
507	V3D_WRITE(V3D_BPOS, 0);
508
509	vc4->v3d = NULL;
510}
511
512static const struct dev_pm_ops vc4_v3d_pm_ops = {
513	SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
514};
515
516static const struct component_ops vc4_v3d_ops = {
517	.bind   = vc4_v3d_bind,
518	.unbind = vc4_v3d_unbind,
519};
520
521static int vc4_v3d_dev_probe(struct platform_device *pdev)
522{
523	return component_add(&pdev->dev, &vc4_v3d_ops);
524}
525
526static void vc4_v3d_dev_remove(struct platform_device *pdev)
527{
528	component_del(&pdev->dev, &vc4_v3d_ops);
529}
530
531const struct of_device_id vc4_v3d_dt_match[] = {
532	{ .compatible = "brcm,bcm2835-v3d" },
533	{ .compatible = "brcm,cygnus-v3d" },
534	{ .compatible = "brcm,vc4-v3d" },
535	{}
536};
537
538struct platform_driver vc4_v3d_driver = {
539	.probe = vc4_v3d_dev_probe,
540	.remove = vc4_v3d_dev_remove,
541	.driver = {
542		.name = "vc4_v3d",
543		.of_match_table = vc4_v3d_dt_match,
544		.pm = &vc4_v3d_pm_ops,
545	},
546};