FILE
vc4_regs.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/vc4/vc4_regs.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright © 2014-2015 Broadcom 4 */ 5 6#ifndef VC4_REGS_H 7#define VC4_REGS_H 8 9#include <linux/bitfield.h> 10#include <linux/bitops.h> 11 12#define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 13/* Using the GNU statement expression extension */ 14#define VC4_SET_FIELD(value, field) \ 15 ({ \ 16 WARN_ON(!FIELD_FIT(field##_MASK, value)); \ 17 FIELD_PREP(field##_MASK, value); \ 18 }) 19 20#define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) 21 22#define VC6_SET_FIELD(value, field) \ 23 ({ \ 24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \ 25 SCALER6_ ## field ## _MASK : \ 26 SCALER6D_ ## field ## _MASK, value));\ 27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \ 28 SCALER6_ ## field ## _MASK : \ 29 SCALER6D_ ## field ## _MASK, value); \ 30 }) 31 32#define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \ 33 SCALER6_ ## field ## _MASK : \ 34 SCALER6D_ ## field ## _MASK, word) 35 36#define V3D_IDENT0 0x00000 37# define V3D_EXPECTED_IDENT0 \ 38 ((2 << 24) | \ 39 ('V' << 0) | \ 40 ('3' << 8) | \ 41 ('D' << 16)) 42 43#define V3D_IDENT1 0x00004 44/* Multiples of 1kb */ 45# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 46# define V3D_IDENT1_VPM_SIZE_SHIFT 28 47# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 48# define V3D_IDENT1_NSEM_SHIFT 16 49# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 50# define V3D_IDENT1_TUPS_SHIFT 12 51# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 52# define V3D_IDENT1_QUPS_SHIFT 8 53# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 54# define V3D_IDENT1_NSLC_SHIFT 4 55# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 56# define V3D_IDENT1_REV_SHIFT 0 57 58#define V3D_IDENT2 0x00008 59#define V3D_SCRATCH 0x00010 60#define V3D_L2CACTL 0x00020 61# define V3D_L2CACTL_L2CCLR BIT(2) 62# define V3D_L2CACTL_L2CDIS BIT(1) 63# define V3D_L2CACTL_L2CENA BIT(0) 64 65#define V3D_SLCACTL 0x00024 66# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 67# define V3D_SLCACTL_T1CC_SHIFT 24 68# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 69# define V3D_SLCACTL_T0CC_SHIFT 16 70# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 71# define V3D_SLCACTL_UCC_SHIFT 8 72# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 73# define V3D_SLCACTL_ICC_SHIFT 0 74 75#define V3D_INTCTL 0x00030 76#define V3D_INTENA 0x00034 77#define V3D_INTDIS 0x00038 78# define V3D_INT_SPILLUSE BIT(3) 79# define V3D_INT_OUTOMEM BIT(2) 80# define V3D_INT_FLDONE BIT(1) 81# define V3D_INT_FRDONE BIT(0) 82 83#define V3D_CT0CS 0x00100 84#define V3D_CT1CS 0x00104 85#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 86# define V3D_CTRSTA BIT(15) 87# define V3D_CTSEMA BIT(12) 88# define V3D_CTRTSD BIT(8) 89# define V3D_CTRUN BIT(5) 90# define V3D_CTSUBS BIT(4) 91# define V3D_CTERR BIT(3) 92# define V3D_CTMODE BIT(0) 93 94#define V3D_CT0EA 0x00108 95#define V3D_CT1EA 0x0010c 96#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 97#define V3D_CT0CA 0x00110 98#define V3D_CT1CA 0x00114 99#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 100#define V3D_CT00RA0 0x00118 101#define V3D_CT01RA0 0x0011c 102#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 103#define V3D_CT0LC 0x00120 104#define V3D_CT1LC 0x00124 105#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 106#define V3D_CT0PC 0x00128 107#define V3D_CT1PC 0x0012c 108#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 109 110#define V3D_PCS 0x00130 111# define V3D_BMOOM BIT(8) 112# define V3D_RMBUSY BIT(3) 113# define V3D_RMACTIVE BIT(2) 114# define V3D_BMBUSY BIT(1) 115# define V3D_BMACTIVE BIT(0) 116 117#define V3D_BFC 0x00134 118#define V3D_RFC 0x00138 119#define V3D_BPCA 0x00300 120#define V3D_BPCS 0x00304 121#define V3D_BPOA 0x00308 122#define V3D_BPOS 0x0030c 123#define V3D_BXCF 0x00310 124#define V3D_SQRSV0 0x00410 125#define V3D_SQRSV1 0x00414 126#define V3D_SQCNTL 0x00418 127#define V3D_SRQPC 0x00430 128#define V3D_SRQUA 0x00434 129#define V3D_SRQUL 0x00438 130#define V3D_SRQCS 0x0043c 131#define V3D_VPACNTL 0x00500 132#define V3D_VPMBASE 0x00504 133#define V3D_PCTRC 0x00670 134#define V3D_PCTRE 0x00674 135# define V3D_PCTRE_EN BIT(31) 136#define V3D_PCTR(x) (0x00680 + ((x) * 8)) 137#define V3D_PCTRS(x) (0x00684 + ((x) * 8)) 138#define V3D_DBGE 0x00f00 139#define V3D_FDBGO 0x00f04 140#define V3D_FDBGB 0x00f08 141#define V3D_FDBGR 0x00f0c 142#define V3D_FDBGS 0x00f10 143#define V3D_ERRSTAT 0x00f20 144 145#define PV_CONTROL 0x00 146# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25) 147# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25 148# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 149# define PV_CONTROL_FORMAT_SHIFT 21 150# define PV_CONTROL_FORMAT_24 0 151# define PV_CONTROL_FORMAT_DSIV_16 1 152# define PV_CONTROL_FORMAT_DSIC_16 2 153# define PV_CONTROL_FORMAT_DSIV_18 3 154# define PV_CONTROL_FORMAT_DSIV_24 4 155 156# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 157# define PV_CONTROL_FIFO_LEVEL_SHIFT 15 158# define PV_CONTROL_CLR_AT_START BIT(14) 159# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 160# define PV_CONTROL_WAIT_HSTART BIT(12) 161# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 162# define PV_CONTROL_PIXEL_REP_SHIFT 4 163# define PV_CONTROL_CLK_SELECT_DSI 0 164# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 165# define PV_CONTROL_CLK_SELECT_VEC 2 166# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 167# define PV_CONTROL_CLK_SELECT_SHIFT 2 168# define PV_CONTROL_FIFO_CLR BIT(1) 169# define PV_CONTROL_EN BIT(0) 170 171#define PV_V_CONTROL 0x04 172# define PV_VCONTROL_ODD_TIMING BIT(29) 173# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 174# define PV_VCONTROL_ODD_DELAY_SHIFT 6 175# define PV_VCONTROL_ODD_FIRST BIT(5) 176# define PV_VCONTROL_INTERLACE BIT(4) 177# define PV_VCONTROL_DSI BIT(3) 178# define PV_VCONTROL_COMMAND BIT(2) 179# define PV_VCONTROL_CONTINUOUS BIT(1) 180# define PV_VCONTROL_VIDEN BIT(0) 181 182#define PV_VSYNCD_EVEN 0x08 183 184#define PV_HORZA 0x0c 185# define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 186# define PV_HORZA_HBP_SHIFT 16 187# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 188# define PV_HORZA_HSYNC_SHIFT 0 189 190#define PV_HORZB 0x10 191# define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 192# define PV_HORZB_HFP_SHIFT 16 193# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 194# define PV_HORZB_HACTIVE_SHIFT 0 195 196#define PV_VERTA 0x14 197# define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 198# define PV_VERTA_VBP_SHIFT 16 199# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 200# define PV_VERTA_VSYNC_SHIFT 0 201 202#define PV_VERTB 0x18 203# define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 204# define PV_VERTB_VFP_SHIFT 16 205# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 206# define PV_VERTB_VACTIVE_SHIFT 0 207 208#define PV_VERTA_EVEN 0x1c 209#define PV_VERTB_EVEN 0x20 210 211#define PV_INTEN 0x24 212#define PV_INTSTAT 0x28 213# define PV_INT_VID_IDLE BIT(9) 214# define PV_INT_VFP_END BIT(8) 215# define PV_INT_VFP_START BIT(7) 216# define PV_INT_VACT_START BIT(6) 217# define PV_INT_VBP_START BIT(5) 218# define PV_INT_VSYNC_START BIT(4) 219# define PV_INT_HFP_START BIT(3) 220# define PV_INT_HACT_START BIT(2) 221# define PV_INT_HBP_START BIT(1) 222# define PV_INT_HSYNC_START BIT(0) 223 224#define PV_STAT 0x2c 225 226#define PV_HACT_ACT 0x30 227 228#define PV_MUX_CFG 0x34 229# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2) 230# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2 231# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8 232 233#define PV_PIPE_INIT_CTRL 0x94 234# define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8) 235# define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK VC4_MASK(7, 4) 236# define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0) 237 238#define SCALER_CHANNELS_COUNT 3 239 240#define SCALER_DISPCTRL 0x00000000 241/* Global register for clock gating the HVS */ 242# define SCALER_DISPCTRL_ENABLE BIT(31) 243# define SCALER_DISPCTRL_PANIC0_MASK VC4_MASK(25, 24) 244# define SCALER_DISPCTRL_PANIC0_SHIFT 24 245# define SCALER_DISPCTRL_PANIC1_MASK VC4_MASK(27, 26) 246# define SCALER_DISPCTRL_PANIC1_SHIFT 26 247# define SCALER_DISPCTRL_PANIC2_MASK VC4_MASK(29, 28) 248# define SCALER_DISPCTRL_PANIC2_SHIFT 28 249# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) 250# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 251 252/* Enables Display 0 short line and underrun contribution to 253 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 254 * always enabled. 255 */ 256# define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x)) 257# define SCALER5_DISPCTRL_DSPEISLUR(x) BIT(9 + ((x) * 4)) 258/* Enables Display 0 end-of-line-N contribution to 259 * SCALER_DISPSTAT_IRQDISP0 260 */ 261# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2)) 262# define SCALER5_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 4)) 263/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 264# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2)) 265# define SCALER5_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 4)) 266 267# define SCALER5_DISPCTRL_DSPEIVST(x) BIT(6 + ((x) * 4)) 268 269# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) /* HVS4 only */ 270# define SCALER_DISPCTRL_SLVWREIRQ BIT(5) /* HVS4 only */ 271# define SCALER5_DISPCTRL_SLVEIRQ BIT(5) 272# define SCALER_DISPCTRL_DMAEIRQ BIT(4) 273/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 274 * bits and short frames.. 275 */ 276# define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x)) 277/* Enables interrupt generation on scaler profiler interrupt. */ 278# define SCALER_DISPCTRL_SCLEIRQ BIT(0) 279 280#define SCALER_DISPSTAT 0x00000004 281# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 282# define SCALER_DISPSTAT_RESP_SHIFT 14 283# define SCALER_DISPSTAT_RESP_OKAY 0 284# define SCALER_DISPSTAT_RESP_EXOKAY 1 285# define SCALER_DISPSTAT_RESP_SLVERR 2 286# define SCALER_DISPSTAT_RESP_DECERR 3 287 288# define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8)) 289/* Set when the DISPEOLN line is done compositing. */ 290# define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8)) 291/* Set when VSTART is seen but there are still pixels in the current 292 * output line. 293 */ 294# define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8)) 295/* Set when HSTART is seen but there are still pixels in the current 296 * output line. 297 */ 298# define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8)) 299/* Set when the downstream tries to read from the display FIFO 300 * while it's empty. 301 */ 302# define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8)) 303/* Set when the display mode changes from RUN to EOF */ 304# define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8)) 305 306# define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \ 307 8 + ((x) * 8)) 308 309/* Set on AXI invalid DMA ID error. */ 310# define SCALER_DISPSTAT_DMA_ERROR BIT(7) 311/* Set on AXI slave read decode error */ 312# define SCALER_DISPSTAT_IRQSLVRD BIT(6) 313/* Set on AXI slave write decode error */ 314# define SCALER_DISPSTAT_IRQSLVWR BIT(5) 315/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 316 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 317 */ 318# define SCALER_DISPSTAT_IRQDMA BIT(4) 319/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 320 * corresponding interrupt bit is enabled in DISPCTRL. 321 */ 322# define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x)) 323/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 324# define SCALER_DISPSTAT_IRQSCL BIT(0) 325 326#define SCALER_DISPID 0x00000008 327#define SCALER_DISPECTRL 0x0000000c 328# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31 329# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31) 330 331#define SCALER_DISPPROF 0x00000010 332 333#define SCALER_DISPDITHER 0x00000014 334# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30 335# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30) 336 337#define SCALER_DISPEOLN 0x00000018 338# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30 339# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30) 340 341#define SCALER_DISPLIST0 0x00000020 342#define SCALER_DISPLIST1 0x00000024 343#define SCALER_DISPLIST2 0x00000028 344#define SCALER_DISPLSTAT 0x0000002c 345#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 346 (x) * (SCALER_DISPLIST1 - \ 347 SCALER_DISPLIST0)) 348 349#define SCALER_DISPLACT0 0x00000030 350#define SCALER_DISPLACT1 0x00000034 351#define SCALER_DISPLACT2 0x00000038 352#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 353 (x) * (SCALER_DISPLACT1 - \ 354 SCALER_DISPLACT0)) 355 356#define SCALER_DISPCTRL0 0x00000040 357# define SCALER_DISPCTRLX_ENABLE BIT(31) 358# define SCALER_DISPCTRLX_RESET BIT(30) 359/* Generates a single frame when VSTART is seen and stops at the last 360 * pixel read from the FIFO. 361 */ 362# define SCALER_DISPCTRLX_ONESHOT BIT(29) 363/* Processes a single context in the dlist and then task switch, 364 * instead of an entire line. 365 */ 366# define SCALER_DISPCTRLX_ONECTX BIT(28) 367/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */ 368# define SCALER_DISPCTRLX_FIFO32 BIT(27) 369/* Turns on output to the DISPSLAVE register instead of the normal 370 * FIFO. 371 */ 372# define SCALER_DISPCTRLX_FIFOREG BIT(26) 373 374# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 375# define SCALER_DISPCTRLX_WIDTH_SHIFT 12 376# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 377# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 378 379# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16) 380# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16 381/* Generates a single frame when VSTART is seen and stops at the last 382 * pixel read from the FIFO. 383 */ 384# define SCALER5_DISPCTRLX_ONESHOT BIT(15) 385/* Processes a single context in the dlist and then task switch, 386 * instead of an entire line. 387 */ 388# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13) 389# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13 390# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0) 391# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0 392 393#define SCALER_DISPBKGND0 0x00000044 394# define SCALER_DISPBKGND_AUTOHS BIT(31) 395# define SCALER5_DISPBKGND_BCK2BCK BIT(31) 396# define SCALER_DISPBKGND_INTERLACE BIT(30) 397# define SCALER_DISPBKGND_GAMMA BIT(29) 398# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 399# define SCALER_DISPBKGND_TESTMODE_SHIFT 25 400/* Enables filling the scaler line with the RGB value in the low 24 401 * bits before compositing. Costs cycles, so should be skipped if 402 * opaque display planes will cover everything. 403 */ 404# define SCALER_DISPBKGND_FILL BIT(24) 405 406#define SCALER_DISPSTAT0 0x00000048 407# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 408# define SCALER_DISPSTATX_MODE_SHIFT 30 409# define SCALER_DISPSTATX_MODE_DISABLED 0 410# define SCALER_DISPSTATX_MODE_INIT 1 411# define SCALER_DISPSTATX_MODE_RUN 2 412# define SCALER_DISPSTATX_MODE_EOF 3 413# define SCALER_DISPSTATX_FULL BIT(29) 414# define SCALER_DISPSTATX_EMPTY BIT(28) 415# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 416# define SCALER_DISPSTATX_LINE_SHIFT 0 417 418#define SCALER_DISPBASE0 0x0000004c 419/* Last pixel in the COB (display FIFO memory) allocated to this HVS 420 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 421 * next COB base). 422 */ 423# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 424# define SCALER_DISPBASEX_TOP_SHIFT 16 425/* First pixel in the COB (display FIFO memory) allocated to this HVS 426 * channel. Must be 4-pixel aligned. 427 */ 428# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 429# define SCALER_DISPBASEX_BASE_SHIFT 0 430 431#define SCALER_DISPCTRL1 0x00000050 432#define SCALER_DISPBKGND1 0x00000054 433#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 434 (x) * (SCALER_DISPBKGND1 - \ 435 SCALER_DISPBKGND0)) 436#define SCALER_DISPSTAT1 0x00000058 437# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18) 438# define SCALER_DISPSTAT1_FRCNT0_SHIFT 18 439# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12) 440# define SCALER_DISPSTAT1_FRCNT1_SHIFT 12 441# define SCALER5_DISPSTAT1_FRCNT0_MASK VC4_MASK(25, 20) 442# define SCALER5_DISPSTAT1_FRCNT0_SHIFT 20 443# define SCALER5_DISPSTAT1_FRCNT1_MASK VC4_MASK(19, 14) 444# define SCALER5_DISPSTAT1_FRCNT1_SHIFT 14 445 446#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 447 (x) * (SCALER_DISPSTAT1 - \ 448 SCALER_DISPSTAT0)) 449 450#define SCALER_DISPBASE1 0x0000005c 451#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 452 (x) * (SCALER_DISPBASE1 - \ 453 SCALER_DISPBASE0)) 454#define SCALER_DISPCTRL2 0x00000060 455#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 456 (x) * (SCALER_DISPCTRL1 - \ 457 SCALER_DISPCTRL0)) 458#define SCALER_DISPBKGND2 0x00000064 459 460#define SCALER_DISPSTAT2 0x00000068 461# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12) 462# define SCALER_DISPSTAT2_FRCNT2_SHIFT 12 463# define SCALER5_DISPSTAT2_FRCNT2_MASK VC4_MASK(19, 14) 464# define SCALER5_DISPSTAT2_FRCNT2_SHIFT 14 465 466#define SCALER_DISPBASE2 0x0000006c 467#define SCALER_DISPALPHA2 0x00000070 468#define SCALER_GAMADDR 0x00000078 469# define SCALER_GAMADDR_AUTOINC BIT(31) 470/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 471 * enabled. 472 */ 473# define SCALER_GAMADDR_SRAMENB BIT(30) 474 475#define SCALER_OLEDOFFS 0x00000080 476/* Clamps R to [16,235] and G/B to [16,240]. */ 477# define SCALER_OLEDOFFS_YUVCLAMP BIT(31) 478 479/* Chooses which display FIFO the matrix applies to. */ 480# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24) 481# define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24 482# define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0 483# define SCALER_OLEDOFFS_DISPFIFO_0 1 484# define SCALER_OLEDOFFS_DISPFIFO_1 2 485# define SCALER_OLEDOFFS_DISPFIFO_2 3 486 487/* Offsets are 8-bit 2s-complement. */ 488# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16) 489# define SCALER_OLEDOFFS_RED_SHIFT 16 490# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8) 491# define SCALER_OLEDOFFS_GREEN_SHIFT 8 492# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0) 493# define SCALER_OLEDOFFS_BLUE_SHIFT 0 494 495/* The coefficients are S0.9 fractions. */ 496#define SCALER_OLEDCOEF0 0x00000084 497# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20) 498# define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20 499# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10) 500# define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10 501# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0) 502# define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0 503 504#define SCALER_OLEDCOEF1 0x00000088 505# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20) 506# define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20 507# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10) 508# define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10 509# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0) 510# define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0 511 512#define SCALER_OLEDCOEF2 0x0000008c 513# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20) 514# define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20 515# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10) 516# define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10 517# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0) 518# define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0 519 520/* Slave addresses for DMAing from HVS composition output to other 521 * devices. The top bits are valid only in !FIFO32 mode. 522 */ 523#define SCALER_DISPSLAVE0 0x000000c0 524#define SCALER_DISPSLAVE1 0x000000c9 525#define SCALER_DISPSLAVE2 0x000000d0 526# define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31) 527# define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30) 528/* Set when the current line has been read and an HSTART is required. */ 529# define SCALER_DISPSLAVE_EOL BIT(26) 530/* Set when the display FIFO is empty. */ 531# define SCALER_DISPSLAVE_EMPTY BIT(25) 532/* Set when there is RGB data ready to read. */ 533# define SCALER_DISPSLAVE_VALID BIT(24) 534# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0) 535# define SCALER_DISPSLAVE_RGB_SHIFT 0 536 537#define SCALER_GAMDATA 0x000000e0 538#define SCALER_DLIST_START 0x00002000 539#define SCALER_DLIST_SIZE 0x00004000 540 541#define SCALER5_DLIST_START 0x00004000 542 543#define SCALER6_VERSION 0x00000000 544# define SCALER6_VERSION_MASK VC4_MASK(7, 0) 545# define SCALER6_VERSION_C0 0x00000053 546# define SCALER6_VERSION_D0 0x00000054 547#define SCALER6_CXM_SIZE 0x00000004 548#define SCALER6_LBM_SIZE 0x00000008 549#define SCALER6_UBM_SIZE 0x0000000c 550#define SCALER6_COBA_SIZE 0x00000010 551#define SCALER6_COB_SIZE 0x00000014 552 553#define SCALER6_CONTROL 0x00000020 554# define SCALER6_CONTROL_HVS_EN BIT(31) 555# define SCALER6_CONTROL_PF_LINES_MASK VC4_MASK(22, 18) 556# define SCALER6_CONTROL_ABORT_ON_EMPTY BIT(16) 557# define SCALER6_CONTROL_DSP1_TARGET_MASK VC4_MASK(13, 12) 558# define SCALER6_CONTROL_MAX_REQS_MASK VC4_MASK(7, 4) 559 560#define SCALER6_FETCHER_STATUS 0x00000024 561#define SCALER6_FETCH_STATUS 0x00000028 562#define SCALER6_HANDLE_ERROR 0x0000002c 563 564#define SCALER6_DISP0_CTRL0 0x00000030 565#define SCALER6_DISPX_CTRL0(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 566 (SCALER6_DISP0_CTRL0 + ((x) * (SCALER6_DISP1_CTRL0 - SCALER6_DISP0_CTRL0))) : \ 567 (SCALER6D_DISP0_CTRL0 + ((x) * (SCALER6D_DISP1_CTRL0 - SCALER6D_DISP0_CTRL0)))) 568# define SCALER6_DISPX_CTRL0_ENB BIT(31) 569# define SCALER6_DISPX_CTRL0_RESET BIT(30) 570# define SCALER6_DISPX_CTRL0_FWIDTH_MASK VC4_MASK(28, 16) 571# define SCALER6_DISPX_CTRL0_ONESHOT BIT(15) 572# define SCALER6_DISPX_CTRL0_ONECTX_MASK VC4_MASK(14, 13) 573# define SCALER6_DISPX_CTRL0_LINES_MASK VC4_MASK(12, 0) 574 575#define SCALER6_DISP0_CTRL1 0x00000034 576#define SCALER6_DISPX_CTRL1(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 577 (SCALER6_DISP0_CTRL1 + ((x) * (SCALER6_DISP1_CTRL1 - SCALER6_DISP0_CTRL1))) : \ 578 (SCALER6D_DISP0_CTRL1 + ((x) * (SCALER6D_DISP1_CTRL1 - SCALER6D_DISP0_CTRL1)))) 579# define SCALER6_DISPX_CTRL1_BGENB BIT(8) 580# define SCALER6_DISPX_CTRL1_INTLACE BIT(0) 581 582#define SCALER6_DISP0_BGND 0x00000038 583#define SCALER6_DISPX_BGND(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 584 (SCALER6_DISP0_BGND + ((x) * (SCALER6_DISP1_BGND - SCALER6_DISP0_BGND))) : \ 585 (SCALER6D_DISP0_BGND + ((x) * (SCALER6D_DISP1_BGND - SCALER6D_DISP0_BGND)))) 586 587#define SCALER6_DISP0_LPTRS 0x0000003c 588#define SCALER6_DISPX_LPTRS(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 589 (SCALER6_DISP0_LPTRS + ((x) * (SCALER6_DISP1_LPTRS - SCALER6_DISP0_LPTRS))) : \ 590 (SCALER6D_DISP0_LPTRS + ((x) * (SCALER6D_DISP1_LPTRS - SCALER6D_DISP0_LPTRS)))) 591# define SCALER6_DISPX_LPTRS_HEADE_MASK VC4_MASK(11, 0) 592 593#define SCALER6_DISP0_COB 0x00000040 594#define SCALER6_DISPX_COB(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 595 (SCALER6_DISP0_COB + ((x) * (SCALER6_DISP1_COB - SCALER6_DISP0_COB))) : \ 596 (SCALER6D_DISP0_COB + ((x) * (SCALER6D_DISP1_COB - SCALER6D_DISP0_COB)))) 597# define SCALER6_DISPX_COB_TOP_MASK VC4_MASK(31, 16) 598# define SCALER6_DISPX_COB_BASE_MASK VC4_MASK(15, 0) 599 600#define SCALER6_DISP0_STATUS 0x00000044 601#define SCALER6_DISPX_STATUS(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 602 (SCALER6_DISP0_STATUS + ((x) * (SCALER6_DISP1_STATUS - SCALER6_DISP0_STATUS))) : \ 603 (SCALER6D_DISP0_STATUS + ((x) * (SCALER6D_DISP1_STATUS - SCALER6D_DISP0_STATUS)))) 604# define SCALER6_DISPX_STATUS_EMPTY BIT(22) 605# define SCALER6_DISPX_STATUS_FRCNT_MASK VC4_MASK(21, 16) 606# define SCALER6_DISPX_STATUS_OFIELD BIT(15) 607# define SCALER6_DISPX_STATUS_MODE_MASK VC4_MASK(14, 13) 608# define SCALER6_DISPX_STATUS_MODE_DISABLED 0 609# define SCALER6_DISPX_STATUS_MODE_INIT 1 610# define SCALER6_DISPX_STATUS_MODE_RUN 2 611# define SCALER6_DISPX_STATUS_MODE_EOF 3 612# define SCALER6_DISPX_STATUS_YLINE_MASK VC4_MASK(12, 0) 613 614#define SCALER6_DISP0_DL 0x00000048 615 616#define SCALER6_DISPX_DL(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? \ 617 (SCALER6_DISP0_DL + ((x) * (SCALER6_DISP1_DL - SCALER6_DISP0_DL))) : \ 618 (SCALER6D_DISP0_DL + ((x) * (SCALER6D_DISP1_DL - SCALER6D_DISP0_DL)))) 619# define SCALER6_DISPX_DL_LACT_MASK VC4_MASK(11, 0) 620 621#define SCALER6_DISP0_RUN 0x0000004c 622#define SCALER6_DISP1_CTRL0 0x00000050 623#define SCALER6_DISP1_CTRL1 0x00000054 624#define SCALER6_DISP1_BGND 0x00000058 625#define SCALER6_DISP1_LPTRS 0x0000005c 626#define SCALER6_DISP1_COB 0x00000060 627#define SCALER6_DISP1_STATUS 0x00000064 628#define SCALER6_DISP1_DL 0x00000068 629#define SCALER6_DISP1_RUN 0x0000006c 630#define SCALER6_DISP2_CTRL0 0x00000070 631#define SCALER6_DISP2_CTRL1 0x00000074 632#define SCALER6_DISP2_BGND 0x00000078 633#define SCALER6_DISP2_LPTRS 0x0000007c 634#define SCALER6_DISP2_COB 0x00000080 635#define SCALER6_DISP2_STATUS 0x00000084 636#define SCALER6_DISP2_DL 0x00000088 637#define SCALER6_DISP2_RUN 0x0000008c 638#define SCALER6_EOLN 0x00000090 639#define SCALER6_DL_STATUS 0x00000094 640#define SCALER6_BFG_MISC 0x0000009c 641#define SCALER6_QOS0 0x000000a0 642#define SCALER6_PROF0 0x000000a4 643#define SCALER6_QOS1 0x000000a8 644#define SCALER6_PROF1 0x000000ac 645#define SCALER6_QOS2 0x000000b0 646#define SCALER6_PROF2 0x000000b4 647#define SCALER6_PRI_MAP0 0x000000b8 648#define SCALER6_PRI_MAP1 0x000000bc 649#define SCALER6_HISTCTRL 0x000000c0 650#define SCALER6_HISTBIN0 0x000000c4 651#define SCALER6_HISTBIN1 0x000000c8 652#define SCALER6_HISTBIN2 0x000000cc 653#define SCALER6_HISTBIN3 0x000000d0 654#define SCALER6_HISTBIN4 0x000000d4 655#define SCALER6_HISTBIN5 0x000000d8 656#define SCALER6_HISTBIN6 0x000000dc 657#define SCALER6_HISTBIN7 0x000000e0 658#define SCALER6_HDR_CFG_REMAP 0x000000f4 659#define SCALER6_COL_SPACE 0x000000f8 660#define SCALER6_HVS_ID 0x000000fc 661#define SCALER6_CFC1 0x00000100 662#define SCALER6_DISP_UPM_ISO0 0x00000200 663#define SCALER6_DISP_UPM_ISO1 0x00000204 664#define SCALER6_DISP_UPM_ISO2 0x00000208 665#define SCALER6_DISP_LBM_ISO0 0x0000020c 666#define SCALER6_DISP_LBM_ISO1 0x00000210 667#define SCALER6_DISP_LBM_ISO2 0x00000214 668#define SCALER6_DISP_COB_ISO0 0x00000218 669#define SCALER6_DISP_COB_ISO1 0x0000021c 670#define SCALER6_DISP_COB_ISO2 0x00000220 671#define SCALER6_BAD_COB 0x00000224 672#define SCALER6_BAD_LBM 0x00000228 673#define SCALER6_BAD_UPM 0x0000022c 674#define SCALER6_BAD_AXI 0x00000230 675 676#define SCALER6D_VERSION 0x00000000 677#define SCALER6D_CXM_SIZE 0x00000004 678#define SCALER6D_LBM_SIZE 0x00000008 679#define SCALER6D_UBM_SIZE 0x0000000c 680#define SCALER6D_COBA_SIZE 0x00000010 681#define SCALER6D_COB_SIZE 0x00000014 682#define SCALER6D_CONTROL 0x00000020 683#define SCALER6D_FETCHER_STATUS 0x00000024 684#define SCALER6D_FETCH_STATUS 0x00000028 685#define SCALER6D_HANDLE_ERROR 0x0000002c 686#define SCALER6D_EOLN 0x00000030 687#define SCALER6D_DL_STATUS 0x00000034 688#define SCALER6D_PRI_MAP0 0x00000038 689#define SCALER6D_PRI_MAP1 0x0000003c 690#define SCALER6D_HISTCTRL 0x000000d0 691#define SCALER6D_HISTBIN0 0x000000d4 692#define SCALER6D_HISTBIN1 0x000000d8 693#define SCALER6D_HISTBIN2 0x000000dc 694#define SCALER6D_HISTBIN3 0x000000e0 695#define SCALER6D_HISTBIN4 0x000000e4 696#define SCALER6D_HISTBIN5 0x000000e8 697#define SCALER6D_HISTBIN6 0x000000ec 698#define SCALER6D_HISTBIN7 0x000000f0 699#define SCALER6D_HVS_ID 0x000000fc 700 701#define SCALER6D_DISP0_CTRL0 0x00000100 702#define SCALER6D_DISP0_CTRL1 0x00000104 703#define SCALER6D_DISP0_BGND 0x00000108 704#define SCALER6D_DISP0_LPTRS 0x00000110 705#define SCALER6D_DISP0_COB 0x00000114 706#define SCALER6D_DISP0_STATUS 0x00000118 707#define SCALER6D_DISP0_CTRL0 0x00000100 708#define SCALER6D_DISP0_CTRL1 0x00000104 709#define SCALER6D_DISP0_BGND0 0x00000108 710#define SCALER6D_DISP0_BGND1 0x0000010c 711#define SCALER6D_DISP0_LPTRS 0x00000110 712#define SCALER6D_DISP0_COB 0x00000114 713#define SCALER6D_DISP0_STATUS 0x00000118 714#define SCALER6D_DISP0_DL 0x0000011c 715#define SCALER6D_DISP0_RUN 0x00000120 716#define SCALER6D_QOS0 0x00000124 717#define SCALER6D_PROF0 0x00000128 718#define SCALER6D_DISP1_CTRL0 0x00000140 719#define SCALER6D_DISP1_CTRL1 0x00000144 720#define SCALER6D_DISP1_BGND0 0x00000148 721#define SCALER6D_DISP1_BGND1 0x0000014c 722#define SCALER6D_DISP1_LPTRS 0x00000150 723#define SCALER6D_DISP1_COB 0x00000154 724#define SCALER6D_DISP1_STATUS 0x00000158 725#define SCALER6D_DISP1_DL 0x0000015c 726#define SCALER6D_DISP1_RUN 0x00000160 727#define SCALER6D_QOS1 0x00000164 728#define SCALER6D_PROF1 0x00000168 729#define SCALER6D_DISP2_CTRL0 0x00000180 730#define SCALER6D_DISP2_CTRL1 0x00000184 731#define SCALER6D_DISP2_BGND0 0x00000188 732#define SCALER6D_DISP2_BGND1 0x0000018c 733#define SCALER6D_DISP2_LPTRS 0x00000190 734#define SCALER6D_DISP2_COB 0x00000194 735#define SCALER6D_DISP2_STATUS 0x00000198 736#define SCALER6D_DISP2_DL 0x0000019c 737#define SCALER6D_DISP2_RUN 0x000001a0 738#define SCALER6D_QOS2 0x000001a4 739#define SCALER6D_PROF2 0x000001a8 740 741#define SCALER6(x) ((hvs->vc4->gen == VC4_GEN_6_C) ? SCALER6_ ## x : SCALER6D_ ## x) 742 743# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 744# define VC4_HDMI_SW_RESET_HDMI BIT(0) 745 746# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 747 748# define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) 749# define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) 750# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) 751# define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 752 753# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) 754# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) 755# define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) 756# define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) 757# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10) 758# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10 759/* If set, then multichannel, otherwise 2 channel. */ 760# define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) 761/* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ 762# define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) 763# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) 764# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 765 766# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16) 767# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16 768 769enum { 770 VC4_HDMI_MAI_FORMAT_PCM = 2, 771 VC4_HDMI_MAI_FORMAT_HBR = 200, 772}; 773 774# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8) 775# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8 776 777enum { 778 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0, 779 VC4_HDMI_MAI_SAMPLE_RATE_8000 = 1, 780 VC4_HDMI_MAI_SAMPLE_RATE_11025 = 2, 781 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3, 782 VC4_HDMI_MAI_SAMPLE_RATE_16000 = 4, 783 VC4_HDMI_MAI_SAMPLE_RATE_22050 = 5, 784 VC4_HDMI_MAI_SAMPLE_RATE_24000 = 6, 785 VC4_HDMI_MAI_SAMPLE_RATE_32000 = 7, 786 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8, 787 VC4_HDMI_MAI_SAMPLE_RATE_48000 = 9, 788 VC4_HDMI_MAI_SAMPLE_RATE_64000 = 10, 789 VC4_HDMI_MAI_SAMPLE_RATE_88200 = 11, 790 VC4_HDMI_MAI_SAMPLE_RATE_96000 = 12, 791 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13, 792 VC4_HDMI_MAI_SAMPLE_RATE_176400 = 14, 793 VC4_HDMI_MAI_SAMPLE_RATE_192000 = 15, 794}; 795 796# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 797 798/* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead 799 * of pixel clock. 800 */ 801# define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) 802/* When set, no CRP packets will be sent. */ 803# define VC4_HDMI_CRP_CFG_DISABLE BIT(25) 804/* If set, generates CTS values based on N, audio clock, and video 805 * clock. N must be divisible by 128. 806 */ 807# define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) 808# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) 809# define VC4_HDMI_CRP_CFG_N_SHIFT 0 810 811# define VC4_HDMI_HORZA_VPOS BIT(14) 812# define VC4_HDMI_HORZA_HPOS BIT(13) 813/* Horizontal active pixels (hdisplay). */ 814# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 815# define VC4_HDMI_HORZA_HAP_SHIFT 0 816 817/* Horizontal back porch (htotal - hsync_end). */ 818# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 819# define VC4_HDMI_HORZB_HBP_SHIFT 20 820/* Horizontal sync pulse (hsync_end - hsync_start). */ 821# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 822# define VC4_HDMI_HORZB_HSP_SHIFT 10 823/* Horizontal front porch (hsync_start - hdisplay). */ 824# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 825# define VC4_HDMI_HORZB_HFP_SHIFT 0 826 827# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 828# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 829# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 830# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 831# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 832# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 833# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 834# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 835# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 836# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 837# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 838 839# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 840# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 841# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 842# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 843# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 844 845/* Vertical sync pulse (vsync_end - vsync_start). */ 846# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 847# define VC4_HDMI_VERTA_VSP_SHIFT 20 848/* Vertical front porch (vsync_start - vdisplay). */ 849# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 850# define VC4_HDMI_VERTA_VFP_SHIFT 13 851/* Vertical active lines (vdisplay). */ 852# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 853# define VC4_HDMI_VERTA_VAL_SHIFT 0 854 855/* Vertical sync pulse offset (for interlaced) */ 856# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 857# define VC4_HDMI_VERTB_VSPO_SHIFT 9 858/* Vertical pack porch (vtotal - vsync_end). */ 859# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 860# define VC4_HDMI_VERTB_VBP_SHIFT 0 861 862/* Set when the transmission has ended. */ 863# define VC4_HDMI_CEC_TX_EOM BIT(31) 864/* If set, transmission was acked on the 1st or 2nd attempt (only one 865 * retry is attempted). If in continuous mode, this means TX needs to 866 * be filled if !TX_EOM. 867 */ 868# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30) 869# define VC4_HDMI_CEC_RX_EOM BIT(29) 870# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28) 871/* Number of bytes received for the message. */ 872# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24) 873# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24 874/* Sets continuous receive mode. Generates interrupt after each 8 875 * bytes to signal that RX_DATA should be consumed, and at RX_EOM. 876 * 877 * If disabled, maximum 16 bytes will be received (including header), 878 * and interrupt at RX_EOM. Later bytes will be acked but not put 879 * into the RX_DATA. 880 */ 881# define VC4_HDMI_CEC_RX_CONTINUE BIT(23) 882# define VC4_HDMI_CEC_TX_CONTINUE BIT(22) 883/* Set this after a CEC interrupt. */ 884# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21) 885/* Starts a TX. Will wait for appropriate idel time before CEC 886 * activity. Must be cleared in between transmits. 887 */ 888# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20) 889# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16) 890# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16 891/* Device's CEC address */ 892# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12) 893# define VC4_HDMI_CEC_ADDR_SHIFT 12 894/* Divides off of HSM clock to generate CEC bit clock. */ 895/* With the current defaults the CEC bit clock is 40 kHz = 25 usec */ 896# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0) 897# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0 898 899/* Set these fields to how many bit clock cycles get to that many 900 * microseconds. 901 */ 902# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24) 903# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24 904# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17) 905# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17 906# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11) 907# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11 908# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5) 909# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5 910# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0) 911# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0 912 913# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24) 914# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24 915# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16) 916# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16 917# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8) 918# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8 919# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0) 920# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0 921 922# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24) 923# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24 924# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16) 925# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16 926# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8) 927# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8 928# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0) 929# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0 930 931# define VC4_HDMI_CEC_TX_SW_RESET BIT(27) 932# define VC4_HDMI_CEC_RX_SW_RESET BIT(26) 933# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) 934# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24) 935# define VC4_HDMI_CEC_RX_CEC_INT BIT(23) 936# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16) 937# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16 938# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8) 939# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8 940# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0) 941# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0 942 943# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) 944 945# define VC4_HDMI_CPU_CEC BIT(6) 946# define VC4_HDMI_CPU_HOTPLUG BIT(0) 947 948/* Debug: Current receive value on the CEC pad. */ 949# define VC4_HD_CECRXD BIT(9) 950/* Debug: Override CEC output to 0. */ 951# define VC4_HD_CECOVR BIT(8) 952# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 953# define VC4_HD_M_RAM_STANDBY (3 << 4) 954# define VC4_HD_M_SW_RST BIT(2) 955# define VC4_HD_M_ENABLE BIT(0) 956 957/* Set when audio stream is received at a slower rate than the 958 * sampling period, so MAI fifo goes empty. Write 1 to clear. 959 */ 960# define VC4_HD_MAI_CTL_DLATE BIT(15) 961# define VC4_HD_MAI_CTL_BUSY BIT(14) 962# define VC4_HD_MAI_CTL_CHALIGN BIT(13) 963# define VC4_HD_MAI_CTL_WHOLSMP BIT(12) 964# define VC4_HD_MAI_CTL_FULL BIT(11) 965# define VC4_HD_MAI_CTL_EMPTY BIT(10) 966# define VC4_HD_MAI_CTL_FLUSH BIT(9) 967/* If set, MAI bus generates SPDIF (bit 31) parity instead of passing 968 * through. 969 */ 970# define VC4_HD_MAI_CTL_PAREN BIT(8) 971# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4) 972# define VC4_HD_MAI_CTL_CHNUM_SHIFT 4 973# define VC4_HD_MAI_CTL_ENABLE BIT(3) 974/* Underflow error status bit, write 1 to clear. */ 975# define VC4_HD_MAI_CTL_ERRORE BIT(2) 976/* Overflow error status bit, write 1 to clear. */ 977# define VC4_HD_MAI_CTL_ERRORF BIT(1) 978/* Single-shot reset bit. Read value is undefined. */ 979# define VC4_HD_MAI_CTL_RESET BIT(0) 980 981# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) 982# define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 983# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) 984# define VC4_HD_MAI_THR_PANICLOW_SHIFT 16 985# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8) 986# define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8 987# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) 988# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 989 990# define VC6_D_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 23) 991# define VC6_D_HD_MAI_THR_PANICHIGH_SHIFT 23 992# define VC6_D_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 15) 993# define VC6_D_HD_MAI_THR_PANICLOW_SHIFT 15 994# define VC6_D_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 7) 995# define VC6_D_HD_MAI_THR_DREQHIGH_SHIFT 7 996# define VC6_D_HD_MAI_THR_DREQLOW_MASK VC4_MASK(6, 0) 997# define VC6_D_HD_MAI_THR_DREQLOW_SHIFT 0 998 999/* Divider from HDMI HSM clock to MAI serial clock. Sampling period 1000 * converges to N / (M + 1) cycles. 1001 */ 1002# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) 1003# define VC4_HD_MAI_SMP_N_SHIFT 8 1004# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) 1005# define VC4_HD_MAI_SMP_M_SHIFT 0 1006 1007# define VC4_HD_VID_CTL_ENABLE BIT(31) 1008# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 1009# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 1010# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 1011# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 1012# define VC4_HD_VID_CTL_CLRSYNC BIT(24) 1013# define VC4_HD_VID_CTL_CLRRGB BIT(23) 1014# define VC4_HD_VID_CTL_BLANKPIX BIT(18) 1015# define VC4_HD_VID_CTL_BLANK_INSERT_EN BIT(16) 1016 1017# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 1018# define VC4_HD_CSC_CTL_ORDER_SHIFT 5 1019# define VC4_HD_CSC_CTL_ORDER_RGB 0 1020# define VC4_HD_CSC_CTL_ORDER_BGR 1 1021# define VC4_HD_CSC_CTL_ORDER_BRG 2 1022# define VC4_HD_CSC_CTL_ORDER_GRB 3 1023# define VC4_HD_CSC_CTL_ORDER_GBR 4 1024# define VC4_HD_CSC_CTL_ORDER_RBG 5 1025# define VC4_HD_CSC_CTL_PADMSB BIT(4) 1026# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 1027# define VC4_HD_CSC_CTL_MODE_SHIFT 2 1028# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 1029# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 1030# define VC4_HD_CSC_CTL_MODE_CUSTOM 3 1031# define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 1032# define VC4_HD_CSC_CTL_ENABLE BIT(0) 1033 1034# define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6) 1035# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \ 1036 VC4_MASK(5, 4) 1037# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \ 1038 3 1039# define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3) 1040# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2) 1041# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0) 1042 1043# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \ 1044 VC4_MASK(7, 6) 1045# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \ 1046 2 1047 1048# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1) 1049 1050# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \ 1051 VC4_MASK(3, 2) 1052# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \ 1053 2 1054 1055/* HVS display list information. */ 1056#define HVS_BOOTLOADER_DLIST_END 32 1057 1058enum hvs_pixel_format { 1059 /* 8bpp */ 1060 HVS_PIXEL_FORMAT_RGB332 = 0, 1061 /* 16bpp */ 1062 HVS_PIXEL_FORMAT_RGBA4444 = 1, 1063 HVS_PIXEL_FORMAT_RGB555 = 2, 1064 HVS_PIXEL_FORMAT_RGBA5551 = 3, 1065 HVS_PIXEL_FORMAT_RGB565 = 4, 1066 /* 24bpp */ 1067 HVS_PIXEL_FORMAT_RGB888 = 5, 1068 HVS_PIXEL_FORMAT_RGBA6666 = 6, 1069 /* 32bpp */ 1070 HVS_PIXEL_FORMAT_RGBA8888 = 7, 1071 1072 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 1073 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 1074 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 1075 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 1076 HVS_PIXEL_FORMAT_H264 = 12, 1077 HVS_PIXEL_FORMAT_PALETTE = 13, 1078 HVS_PIXEL_FORMAT_YUV444_RGB = 14, 1079 HVS_PIXEL_FORMAT_AYUV444_RGB = 15, 1080 HVS_PIXEL_FORMAT_RGBA1010102 = 16, 1081 HVS_PIXEL_FORMAT_YCBCR_10BIT = 17, 1082}; 1083 1084/* Note: the LSB is the rightmost character shown. Only valid for 1085 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 1086 */ 1087/* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */ 1088#define HVS_PIXEL_ORDER_RGBA 0 1089#define HVS_PIXEL_ORDER_BGRA 1 1090#define HVS_PIXEL_ORDER_ARGB 2 1091#define HVS_PIXEL_ORDER_ABGR 3 1092 1093/* For modes 666 and 888 (4 & 5) */ 1094#define HVS_PIXEL_ORDER_XBRG 0 1095#define HVS_PIXEL_ORDER_XRBG 1 1096#define HVS_PIXEL_ORDER_XRGB 2 1097#define HVS_PIXEL_ORDER_XBGR 3 1098 1099/* For YCbCr modes (8-12, and 17) */ 1100#define HVS_PIXEL_ORDER_XYCBCR 0 1101#define HVS_PIXEL_ORDER_XYCRCB 1 1102#define HVS_PIXEL_ORDER_YXCBCR 2 1103#define HVS_PIXEL_ORDER_YXCRCB 3 1104 1105#define SCALER_CTL0_END BIT(31) 1106#define SCALER_CTL0_VALID BIT(30) 1107 1108#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 1109#define SCALER_CTL0_SIZE_SHIFT 24 1110 1111#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20) 1112#define SCALER_CTL0_TILING_SHIFT 20 1113#define SCALER_CTL0_TILING_LINEAR 0 1114#define SCALER_CTL0_TILING_64B 1 1115#define SCALER_CTL0_TILING_128B 2 1116#define SCALER_CTL0_TILING_256B_OR_T 3 1117 1118#define SCALER_CTL0_ALPHA_MASK BIT(19) 1119#define SCALER_CTL0_HFLIP BIT(16) 1120#define SCALER_CTL0_VFLIP BIT(15) 1121 1122#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17) 1123#define SCALER_CTL0_KEY_MODE_SHIFT 17 1124#define SCALER_CTL0_KEY_DISABLED 0 1125#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1 1126#define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */ 1127#define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */ 1128 1129#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 1130#define SCALER_CTL0_ORDER_SHIFT 13 1131 1132#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11) 1133#define SCALER_CTL0_RGBA_EXPAND_SHIFT 11 1134#define SCALER_CTL0_RGBA_EXPAND_ZERO 0 1135#define SCALER_CTL0_RGBA_EXPAND_LSB 1 1136#define SCALER_CTL0_RGBA_EXPAND_MSB 2 1137#define SCALER_CTL0_RGBA_EXPAND_ROUND 3 1138 1139#define SCALER5_CTL0_ALPHA_EXPAND BIT(12) 1140 1141#define SCALER5_CTL0_RGB_EXPAND BIT(11) 1142 1143#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 1144#define SCALER_CTL0_SCL1_SHIFT 8 1145 1146#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 1147#define SCALER_CTL0_SCL0_SHIFT 5 1148 1149#define SCALER_CTL0_SCL_H_PPF_V_PPF 0 1150#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 1151#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 1152#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 1153#define SCALER_CTL0_SCL_H_PPF_V_NONE 4 1154#define SCALER_CTL0_SCL_H_NONE_V_PPF 5 1155#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 1156#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 1157 1158/* Set to indicate no scaling. */ 1159#define SCALER_CTL0_UNITY BIT(4) 1160#define SCALER5_CTL0_UNITY BIT(15) 1161 1162#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 1163#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 1164 1165#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0) 1166 1167#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 1168#define SCALER_POS0_FIXED_ALPHA_SHIFT 24 1169 1170#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 1171#define SCALER_POS0_START_Y_SHIFT 12 1172 1173#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 1174#define SCALER_POS0_START_X_SHIFT 0 1175 1176#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16) 1177#define SCALER5_POS0_START_Y_SHIFT 16 1178 1179#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0) 1180#define SCALER5_POS0_START_X_SHIFT 0 1181 1182#define SCALER5_POS0_VFLIP BIT(31) 1183#define SCALER5_POS0_HFLIP BIT(15) 1184 1185#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30) 1186#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30 1187#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0 1188#define SCALER5_CTL2_ALPHA_MODE_FIXED 1 1189#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2 1190#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3 1191 1192#define SCALER5_CTL2_ALPHA_PREMULT BIT(29) 1193 1194#define SCALER5_CTL2_ALPHA_MIX BIT(28) 1195 1196#define SCALER5_CTL2_ALPHA_LOC BIT(25) 1197 1198#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17) 1199#define SCALER5_CTL2_MAP_SEL_SHIFT 17 1200 1201#define SCALER5_CTL2_GAMMA BIT(16) 1202 1203#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4) 1204#define SCALER5_CTL2_ALPHA_SHIFT 4 1205 1206#define SCALER6D_CTL2_CSC_ENABLE BIT(19) 1207#define SCALER6D_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(22, 20) 1208 1209#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 1210#define SCALER_POS1_SCL_HEIGHT_SHIFT 16 1211 1212#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 1213#define SCALER_POS1_SCL_WIDTH_SHIFT 0 1214 1215#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16) 1216#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16 1217 1218#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0) 1219#define SCALER5_POS1_SCL_WIDTH_SHIFT 0 1220 1221#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 1222#define SCALER_POS2_ALPHA_MODE_SHIFT 30 1223#define SCALER_POS2_ALPHA_MODE_PIPELINE 0 1224#define SCALER_POS2_ALPHA_MODE_FIXED 1 1225#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 1226#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 1227#define SCALER_POS2_ALPHA_PREMULT BIT(29) 1228#define SCALER_POS2_ALPHA_MIX BIT(28) 1229 1230#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 1231#define SCALER_POS2_HEIGHT_SHIFT 16 1232 1233#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 1234#define SCALER_POS2_WIDTH_SHIFT 0 1235 1236#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16) 1237#define SCALER5_POS2_HEIGHT_SHIFT 16 1238 1239#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0) 1240#define SCALER5_POS2_WIDTH_SHIFT 0 1241 1242/* Color Space Conversion words. Some values are S2.8 signed 1243 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 1244 * 0x2: 2, 0x3: -1} 1245 */ 1246/* bottom 8 bits of S2.8 contribution of Cr to Blue */ 1247#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 1248#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 1249/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 1250#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 1251#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 1252/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 1253#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 1254#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 1255/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 1256#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 1257#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 1258#define SCALER_CSC0_ITR_R_601_5 0x00f00000 1259#define SCALER_CSC0_ITR_R_709_3 0x00f00000 1260#define SCALER_CSC0_ITR_R_2020 0x00f00000 1261#define SCALER_CSC0_JPEG_JFIF 0x00000000 1262#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000 1263#define SCALER_CSC0_ITR_R_2020_FR 0x00000000 1264 1265/* S2.8 contribution of Cb to Green */ 1266#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 1267#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 1268/* S2.8 contribution of Cr to Green */ 1269#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 1270#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 1271/* S2.8 contribution of Y to all of RGB */ 1272#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 1273#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 1274/* top 2 bits of S2.8 contribution of Cr to Blue */ 1275#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 1276#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 1277#define SCALER_CSC1_ITR_R_601_5 0xe73304a8 1278#define SCALER_CSC1_ITR_R_709_3 0xf27784a8 1279#define SCALER_CSC1_ITR_R_2020 0xf43594a8 1280#define SCALER_CSC1_JPEG_JFIF 0xea349400 1281#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400 1282#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400 1283 1284/* S2.8 contribution of Cb to Red */ 1285#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 1286#define SCALER_CSC2_COEF_CB_RED_SHIFT 20 1287/* S2.8 contribution of Cr to Red */ 1288#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 1289#define SCALER_CSC2_COEF_CR_RED_SHIFT 10 1290/* S2.8 contribution of Cb to Blue */ 1291#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 1292#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 1293#define SCALER_CSC2_ITR_R_601_5 0x00066604 1294#define SCALER_CSC2_ITR_R_709_3 0x00072e1d 1295#define SCALER_CSC2_ITR_R_2020 0x0006b624 1296#define SCALER_CSC2_JPEG_JFIF 0x00059dc6 1297#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb 1298#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2 1299 1300#define SCALER_TPZ0_VERT_RECALC BIT(31) 1301#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 1302#define SCALER_TPZ0_SCALE_SHIFT 8 1303#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 1304#define SCALER_TPZ0_IPHASE_SHIFT 0 1305#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 1306#define SCALER_TPZ1_RECIP_SHIFT 0 1307 1308/* Skips interpolating coefficients to 64 phases, so just 8 are used. 1309 * Required for nearest neighbor. 1310 */ 1311#define SCALER_PPF_NOINTERP BIT(31) 1312/* Replaes the highest valued coefficient with one that makes all 4 1313 * sum to unity. 1314 */ 1315#define SCALER_PPF_AGC BIT(30) 1316#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 1317#define SCALER_PPF_SCALE_SHIFT 8 1318#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 1319#define SCALER_PPF_IPHASE_SHIFT 0 1320 1321#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 1322#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 1323#define SCALER_PPF_KERNEL_UNCACHED BIT(31) 1324 1325/* PITCH0/1/2 fields for raster. */ 1326#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 1327#define SCALER_SRC_PITCH_SHIFT 0 1328 1329/* PITCH0/1/2 fields for tiled (SAND). */ 1330#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16) 1331#define SCALER_TILE_SKIP_0_SHIFT 16 1332#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0) 1333#define SCALER_TILE_HEIGHT_SHIFT 0 1334 1335/* Common PITCH0 fields */ 1336#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26) 1337#define SCALER_PITCH0_SINK_PIX_SHIFT 26 1338 1339/* PITCH0 fields for T-tiled. */ 1340#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16) 1341#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16 1342#define SCALER_PITCH0_TILE_LINE_DIR BIT(15) 1343#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14) 1344/* Y offset within a tile. */ 1345#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8) 1346#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8 1347#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0) 1348#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0 1349 1350#define SCALER6_CTL0_END BIT(31) 1351#define SCALER6_CTL0_VALID BIT(30) 1352#define SCALER6_CTL0_NEXT_MASK VC4_MASK(29, 24) 1353#define SCALER6_CTL0_RGB_TRANS BIT(23) 1354#define SCALER6_CTL0_ADDR_MODE_MASK VC4_MASK(22, 20) 1355#define SCALER6_CTL0_ADDR_MODE_LINEAR 0 1356#define SCALER6_CTL0_ADDR_MODE_128B 1 1357#define SCALER6_CTL0_ADDR_MODE_256B 2 1358#define SCALER6_CTL0_ADDR_MODE_MAP8 3 1359#define SCALER6_CTL0_ADDR_MODE_UIF 4 1360 1361#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18) 1362#define SCALER6_CTL0_ALPHA_MASK_NONE 0 1363#define SCALER6D_CTL0_ALPHA_MASK_FIXED 3 1364#define SCALER6_CTL0_UNITY BIT(15) 1365#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13) 1366#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8) 1367#define SCALER6_CTL0_SCL0_MODE_MASK VC4_MASK(7, 5) 1368#define SCALER6_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0) 1369 1370#define SCALER6_POS0_START_Y_MASK VC4_MASK(28, 16) 1371#define SCALER6_POS0_HFLIP BIT(15) 1372#define SCALER6_POS0_START_X_MASK VC4_MASK(12, 0) 1373 1374#define SCALER6_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30) 1375#define SCALER6_CTL2_ALPHA_PREMULT BIT(29) 1376#define SCALER6_CTL2_ALPHA_MIX BIT(28) 1377#define SCALER6_CTL2_BFG BIT(26) 1378#define SCALER6C_CTL2_CSC_ENABLE BIT(25) 1379#define SCALER6C_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16) 1380#define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4) 1381 1382#define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16) 1383#define SCALER6_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0) 1384 1385#define SCALER6_POS2_SRC_LINES_MASK VC4_MASK(28, 16) 1386#define SCALER6_POS2_SRC_WIDTH_MASK VC4_MASK(12, 0) 1387 1388#define SCALER6_PTR0_VFLIP BIT(31) 1389#define SCALER6_PTR0_UPM_BASE_MASK VC4_MASK(28, 16) 1390#define SCALER6_PTR0_UPM_HANDLE_MASK VC4_MASK(14, 10) 1391#define SCALER6_PTR0_UPM_BUFF_SIZE_MASK VC4_MASK(9, 8) 1392#define SCALER6_PTR0_UPM_BUFF_SIZE_16_LINES 3 1393#define SCALER6_PTR0_UPM_BUFF_SIZE_8_LINES 2 1394#define SCALER6_PTR0_UPM_BUFF_SIZE_4_LINES 1 1395#define SCALER6_PTR0_UPM_BUFF_SIZE_2_LINES 0 1396#define SCALER6_PTR0_UPPER_ADDR_MASK VC4_MASK(7, 0) 1397 1398#define SCALER6_PTR2_ALPHA_BPP_MASK VC4_MASK(31, 31) 1399#define SCALER6_PTR2_ALPHA_BPP_1BPP 1 1400#define SCALER6_PTR2_ALPHA_BPP_8BPP 0 1401#define SCALER6_PTR2_ALPHA_ORDER_MASK VC4_MASK(30, 30) 1402#define SCALER6_PTR2_ALPHA_ORDER_MSB_TO_LSB 1 1403#define SCALER6_PTR2_ALPHA_ORDER_LSB_TO_MSB 0 1404#define SCALER6_PTR2_ALPHA_OFFS_MASK VC4_MASK(29, 27) 1405#define SCALER6_PTR2_LSKIP_MASK VC4_MASK(26, 24) 1406#define SCALER6_PTR2_PITCH_MASK VC4_MASK(16, 0) 1407#define SCALER6_PTR2_FETCH_COUNT_MASK VC4_MASK(26, 16) 1408 1409#endif /* VC4_REGS_H */
~/
Read-only file preview.