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vc4_hdmi_regs.h

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linux-6.19.14/drivers/gpu/drm/vc4/vc4_hdmi_regs.h C 
  1#ifndef _VC4_HDMI_REGS_H_
  2#define _VC4_HDMI_REGS_H_
  3
  4#include <linux/pm_runtime.h>
  5
  6#include "vc4_hdmi.h"
  7
  8#define VC4_HDMI_PACKET_STRIDE			0x24
  9
 10enum vc4_hdmi_regs {
 11	VC4_INVALID = 0,
 12	VC4_HDMI,
 13	VC4_HD,
 14	VC5_CEC,
 15	VC5_CSC,
 16	VC5_DVP,
 17	VC5_PHY,
 18	VC5_RAM,
 19	VC5_RM,
 20};
 21
 22enum vc4_hdmi_field {
 23	HDMI_AUDIO_PACKET_CONFIG,
 24	HDMI_CEC_CNTRL_1,
 25	HDMI_CEC_CNTRL_2,
 26	HDMI_CEC_CNTRL_3,
 27	HDMI_CEC_CNTRL_4,
 28	HDMI_CEC_CNTRL_5,
 29	HDMI_CEC_CPU_CLEAR,
 30	HDMI_CEC_CPU_MASK_CLEAR,
 31	HDMI_CEC_CPU_MASK_SET,
 32	HDMI_CEC_CPU_MASK_STATUS,
 33	HDMI_CEC_CPU_STATUS,
 34	HDMI_CEC_CPU_SET,
 35
 36	/*
 37	 * Transmit data, first byte is low byte of the 32-bit reg.
 38	 * MSB of each byte transmitted first.
 39	 */
 40	HDMI_CEC_RX_DATA_1,
 41	HDMI_CEC_RX_DATA_2,
 42	HDMI_CEC_RX_DATA_3,
 43	HDMI_CEC_RX_DATA_4,
 44	HDMI_CEC_TX_DATA_1,
 45	HDMI_CEC_TX_DATA_2,
 46	HDMI_CEC_TX_DATA_3,
 47	HDMI_CEC_TX_DATA_4,
 48	HDMI_CLOCK_STOP,
 49	HDMI_CORE_REV,
 50	HDMI_CRP_CFG,
 51	HDMI_CSC_12_11,
 52	HDMI_CSC_14_13,
 53	HDMI_CSC_22_21,
 54	HDMI_CSC_24_23,
 55	HDMI_CSC_32_31,
 56	HDMI_CSC_34_33,
 57	HDMI_CSC_CHANNEL_CTL,
 58	HDMI_CSC_CTL,
 59
 60	/*
 61	 * 20-bit fields containing CTS values to be transmitted if
 62	 * !EXTERNAL_CTS_EN
 63	 */
 64	HDMI_CTS_0,
 65	HDMI_CTS_1,
 66	HDMI_DEEP_COLOR_CONFIG_1,
 67	HDMI_DVP_CTL,
 68	HDMI_FIFO_CTL,
 69	HDMI_FRAME_COUNT,
 70	HDMI_GCP_CONFIG,
 71	HDMI_GCP_WORD_1,
 72	HDMI_HORZA,
 73	HDMI_HORZB,
 74	HDMI_HOTPLUG,
 75	HDMI_HOTPLUG_INT,
 76
 77	/*
 78	 * 3 bits per field, where each field maps from that
 79	 * corresponding MAI bus channel to the given HDMI channel.
 80	 */
 81	HDMI_MAI_CHANNEL_MAP,
 82	HDMI_MAI_CONFIG,
 83	HDMI_MAI_CTL,
 84
 85	/*
 86	 * Register for DMAing in audio data to be transported over
 87	 * the MAI bus to the Falcon core.
 88	 */
 89	HDMI_MAI_DATA,
 90
 91	/* Format header to be placed on the MAI data. Unused. */
 92	HDMI_MAI_FMT,
 93
 94	/* Last received format word on the MAI bus. */
 95	HDMI_MAI_FORMAT,
 96	HDMI_MAI_SMP,
 97	HDMI_MAI_THR,
 98	HDMI_M_CTL,
 99	HDMI_RAM_PACKET_CONFIG,
100	HDMI_RAM_PACKET_START,
101	HDMI_RAM_PACKET_STATUS,
102	HDMI_RM_CONTROL,
103	HDMI_RM_FORMAT,
104	HDMI_RM_OFFSET,
105	HDMI_SCHEDULER_CONTROL,
106	HDMI_SCRAMBLER_CTL,
107	HDMI_SW_RESET_CONTROL,
108	HDMI_TX_PHY_CHANNEL_SWAP,
109	HDMI_TX_PHY_CLK_DIV,
110	HDMI_TX_PHY_CTL_0,
111	HDMI_TX_PHY_CTL_1,
112	HDMI_TX_PHY_CTL_2,
113	HDMI_TX_PHY_CTL_3,
114	HDMI_TX_PHY_CTL_CK,
115	HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
116	HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
117	HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
118	HDMI_TX_PHY_PLL_CFG,
119	HDMI_TX_PHY_PLL_CFG_PDIV,
120	HDMI_TX_PHY_PLL_CTL_0,
121	HDMI_TX_PHY_PLL_CTL_1,
122	HDMI_TX_PHY_PLL_MISC_0,
123	HDMI_TX_PHY_PLL_MISC_1,
124	HDMI_TX_PHY_PLL_MISC_2,
125	HDMI_TX_PHY_PLL_MISC_3,
126	HDMI_TX_PHY_PLL_MISC_4,
127	HDMI_TX_PHY_PLL_MISC_5,
128	HDMI_TX_PHY_PLL_MISC_6,
129	HDMI_TX_PHY_PLL_MISC_7,
130	HDMI_TX_PHY_PLL_MISC_8,
131	HDMI_TX_PHY_PLL_POST_KDIV,
132	HDMI_TX_PHY_PLL_POWERUP_CTL,
133	HDMI_TX_PHY_PLL_REFCLK,
134	HDMI_TX_PHY_PLL_RESET_CTL,
135	HDMI_TX_PHY_PLL_VCOCLK_DIV,
136	HDMI_TX_PHY_POWERDOWN_CTL,
137	HDMI_TX_PHY_POWERUP_CTL,
138	HDMI_TX_PHY_RESET_CTL,
139	HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
140	HDMI_VEC_INTERFACE_CFG,
141	HDMI_VEC_INTERFACE_XBAR,
142	HDMI_VERTA0,
143	HDMI_VERTA1,
144	HDMI_VERTB0,
145	HDMI_VERTB1,
146	HDMI_VID_CTL,
147	HDMI_MISC_CONTROL,
148	HDMI_FORMAT_DET_1,
149	HDMI_FORMAT_DET_2,
150	HDMI_FORMAT_DET_3,
151	HDMI_FORMAT_DET_4,
152	HDMI_FORMAT_DET_5,
153	HDMI_FORMAT_DET_6,
154	HDMI_FORMAT_DET_7,
155	HDMI_FORMAT_DET_8,
156	HDMI_FORMAT_DET_9,
157	HDMI_FORMAT_DET_10,
158};
159
160struct vc4_hdmi_register {
161	char *name;
162	enum vc4_hdmi_regs reg;
163	unsigned int offset;
164};
165
166#define _VC4_REG(_base, _reg, _offset)	\
167	[_reg] = {				\
168		.name = #_reg,			\
169		.reg = _base,			\
170		.offset = _offset,		\
171	}
172
173#define VC4_HD_REG(reg, offset)		_VC4_REG(VC4_HD, reg, offset)
174#define VC4_HDMI_REG(reg, offset)	_VC4_REG(VC4_HDMI, reg, offset)
175#define VC5_CEC_REG(reg, offset)	_VC4_REG(VC5_CEC, reg, offset)
176#define VC5_CSC_REG(reg, offset)	_VC4_REG(VC5_CSC, reg, offset)
177#define VC5_DVP_REG(reg, offset)	_VC4_REG(VC5_DVP, reg, offset)
178#define VC5_PHY_REG(reg, offset)	_VC4_REG(VC5_PHY, reg, offset)
179#define VC5_RAM_REG(reg, offset)	_VC4_REG(VC5_RAM, reg, offset)
180#define VC5_RM_REG(reg, offset)		_VC4_REG(VC5_RM, reg, offset)
181
182static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
183	VC4_HD_REG(HDMI_M_CTL, 0x000c),
184	VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
185	VC4_HD_REG(HDMI_MAI_THR, 0x0018),
186	VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
187	VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
188	VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
189	VC4_HD_REG(HDMI_VID_CTL, 0x0038),
190	VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
191	VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
192	VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
193	VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
194	VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
195	VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
196	VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
197	VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
198
199	VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
200	VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
201	VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
202	VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
203	VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
204	VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
205	VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
206	VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
207	VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
208	VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
209	VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
210	VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
211	VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
212	VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
213	VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
214	VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
215	VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
216	VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
217	VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
218	VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
219	VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
220	VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x00e4),
221	VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
222	VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
223	VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
224	VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
225	VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
226	VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
227	VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
228	VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
229	VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
230	VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
231	VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
232	VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
233	VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
234	VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
235	VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
236	VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
237	VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
238	VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
239	VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
240	VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
241	VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
242	VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
243};
244
245static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
246	VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
247	VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
248	VC4_HD_REG(HDMI_MAI_THR, 0x0014),
249	VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
250	VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
251	VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
252	VC4_HD_REG(HDMI_VID_CTL, 0x0044),
253	VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
254
255	VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
256	VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
257	VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
258	VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
259	VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
260	VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
261	VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
262	VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
263	VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
264	VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
265	VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
266	VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
267	VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
268	VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
269	VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
270	VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
271	VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
272	VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
273	VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
274	VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
275	VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
276	VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
277	VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
278	VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
279	VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
280	VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
281	VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
282	VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
283	VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
284	VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
285	VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
286	VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
287
288	VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
289	VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
290	VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
291
292	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
293	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
294	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
295	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
296	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
297	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
298	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
299	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
300	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
301	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
302	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
303	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
304	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
305	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
306	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
307
308	VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
309	VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
310	VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
311
312	VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
313
314	VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
315	VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
316	VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
317	VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
318	VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
319	VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
320	VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
321	VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
322	VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
323	VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
324	VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
325	VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
326	VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
327
328	VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
329	VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
330	VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
331	VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
332	VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
333	VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
334	VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
335	VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
336};
337
338static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
339	VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
340	VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
341	VC4_HD_REG(HDMI_MAI_THR, 0x0034),
342	VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
343	VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
344	VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
345	VC4_HD_REG(HDMI_VID_CTL, 0x0048),
346	VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
347
348	VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
349	VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
350	VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
351	VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
352	VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
353	VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
354	VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
355	VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
356	VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
357	VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
358	VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
359	VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
360	VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
361	VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
362	VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
363	VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
364	VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
365	VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
366	VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
367	VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
368	VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
369	VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
370	VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
371	VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
372	VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
373	VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
374	VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
375	VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
376	VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
377	VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
378	VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
379	VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
380
381	VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
382	VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
383	VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
384
385	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
386	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
387	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
388	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
389	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
390	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
391	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
392	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
393	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
394	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
395	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
396	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
397	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
398	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
399	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
400
401	VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
402	VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
403	VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
404
405	VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
406
407	VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
408	VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
409	VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
410	VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
411	VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
412	VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
413	VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
414	VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
415	VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
416	VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
417	VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
418	VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
419	VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
420
421	VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
422	VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
423	VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
424	VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
425	VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
426	VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
427	VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
428	VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
429};
430
431static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi0_fields[] = {
432	VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
433	VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
434	VC4_HD_REG(HDMI_MAI_THR, 0x0014),
435	VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
436	VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
437	VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
438	VC4_HD_REG(HDMI_VID_CTL, 0x0044),
439	VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
440
441	VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
442	VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
443	VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
444	VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
445	VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
446	VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
447	VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
448	VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
449	VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
450	VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
451	VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
452	VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
453	VC4_HDMI_REG(HDMI_VERTA1, 0x100),
454	VC4_HDMI_REG(HDMI_VERTB1, 0x104),
455	VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
456	VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
457	VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
458	VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
459	VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
460	VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
461	VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
462	VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
463	VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
464	VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
465	VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
466	VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
467	VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
468	VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
469	VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
470	VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
471	VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
472	VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
473
474	VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
475	VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
476	VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
477
478	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
479	VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
480	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
481	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
482	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
483	VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
484	VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
485	VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
486	VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
487	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
488	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
489	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
490	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
491	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
492	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
493	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
494	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
495	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
496	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
497	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
498	VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
499	VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
500
501	VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
502	VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
503	VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
504
505	VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
506
507	VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
508	VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
509	VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
510	VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
511	VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
512	VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
513	VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
514	VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
515	VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
516	VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
517	VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
518	VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
519	VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
520
521	VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
522	VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
523	VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
524	VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
525	VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
526	VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
527	VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
528	VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
529};
530
531static const struct vc4_hdmi_register __maybe_unused vc6_hdmi_hdmi1_fields[] = {
532	VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
533	VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
534	VC4_HD_REG(HDMI_MAI_THR, 0x0034),
535	VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
536	VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
537	VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
538	VC4_HD_REG(HDMI_VID_CTL, 0x0048),
539	VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
540
541	VC4_HDMI_REG(HDMI_FIFO_CTL, 0x07c),
542	VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0c0),
543	VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0c4),
544	VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0cc),
545	VC4_HDMI_REG(HDMI_CRP_CFG, 0x0d0),
546	VC4_HDMI_REG(HDMI_CTS_0, 0x0d4),
547	VC4_HDMI_REG(HDMI_CTS_1, 0x0d8),
548	VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e8),
549	VC4_HDMI_REG(HDMI_HORZA, 0x0ec),
550	VC4_HDMI_REG(HDMI_HORZB, 0x0f0),
551	VC4_HDMI_REG(HDMI_VERTA0, 0x0f4),
552	VC4_HDMI_REG(HDMI_VERTB0, 0x0f8),
553	VC4_HDMI_REG(HDMI_VERTA1, 0x100),
554	VC4_HDMI_REG(HDMI_VERTB1, 0x104),
555	VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x114),
556	VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0a4),
557	VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a8),
558	VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x148),
559	VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x14c),
560	VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x150),
561	VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x158),
562	VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x15c),
563	VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x160),
564	VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x164),
565	VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x168),
566	VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x16c),
567	VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x170),
568	VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x18c),
569	VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x194),
570	VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x198),
571	VC4_HDMI_REG(HDMI_HOTPLUG, 0x1c8),
572	VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1e4),
573
574	VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
575	VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0f0),
576	VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f4),
577
578	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
579	VC5_PHY_REG(HDMI_TX_PHY_POWERUP_CTL, 0x004),
580	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
581	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
582	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
583	VC5_PHY_REG(HDMI_TX_PHY_CTL_CK, 0x014),
584	VC5_PHY_REG(HDMI_TX_PHY_PLL_REFCLK, 0x01c),
585	VC5_PHY_REG(HDMI_TX_PHY_PLL_POST_KDIV, 0x028),
586	VC5_PHY_REG(HDMI_TX_PHY_PLL_VCOCLK_DIV, 0x02c),
587	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x044),
588	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x054),
589	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_0, 0x060),
590	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_1, 0x064),
591	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_2, 0x068),
592	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_3, 0x06c),
593	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_4, 0x070),
594	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_5, 0x074),
595	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_6, 0x078),
596	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_7, 0x07c),
597	VC5_PHY_REG(HDMI_TX_PHY_PLL_MISC_8, 0x080),
598	VC5_PHY_REG(HDMI_TX_PHY_PLL_RESET_CTL, 0x190),
599	VC5_PHY_REG(HDMI_TX_PHY_PLL_POWERUP_CTL, 0x194),
600
601	VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
602	VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
603	VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
604
605	VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
606
607	VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
608	VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
609	VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
610	VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
611	VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
612	VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
613	VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
614	VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
615	VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
616	VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
617	VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
618	VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
619	VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
620
621	VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
622	VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
623	VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
624	VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
625	VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
626	VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
627	VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
628	VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
629};
630
631static inline
632void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
633					enum vc4_hdmi_regs reg)
634{
635	switch (reg) {
636	case VC4_HD:
637		return hdmi->hd_regs;
638
639	case VC4_HDMI:
640		return hdmi->hdmicore_regs;
641
642	case VC5_CSC:
643		return hdmi->csc_regs;
644
645	case VC5_CEC:
646		return hdmi->cec_regs;
647
648	case VC5_DVP:
649		return hdmi->dvp_regs;
650
651	case VC5_PHY:
652		return hdmi->phy_regs;
653
654	case VC5_RAM:
655		return hdmi->ram_regs;
656
657	case VC5_RM:
658		return hdmi->rm_regs;
659
660	default:
661		return NULL;
662	}
663
664	return NULL;
665}
666
667static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
668				enum vc4_hdmi_field reg)
669{
670	const struct vc4_hdmi_register *field;
671	const struct vc4_hdmi_variant *variant = hdmi->variant;
672	void __iomem *base;
673
674	WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
675
676	kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
677
678	if (reg >= variant->num_registers) {
679		dev_warn(&hdmi->pdev->dev,
680			 "Invalid register ID %u\n", reg);
681		return 0;
682	}
683
684	field = &variant->registers[reg];
685	base = __vc4_hdmi_get_field_base(hdmi, field->reg);
686	if (!base) {
687		dev_warn(&hdmi->pdev->dev,
688			 "Unknown register ID %u\n", reg);
689		return 0;
690	}
691
692	return readl(base + field->offset);
693}
694#define HDMI_READ(reg)		vc4_hdmi_read(vc4_hdmi, reg)
695
696static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
697				  enum vc4_hdmi_field reg,
698				  u32 value)
699{
700	const struct vc4_hdmi_register *field;
701	const struct vc4_hdmi_variant *variant = hdmi->variant;
702	void __iomem *base;
703
704	lockdep_assert_held(&hdmi->hw_lock);
705
706	WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
707
708	kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
709
710	if (reg >= variant->num_registers) {
711		dev_warn(&hdmi->pdev->dev,
712			 "Invalid register ID %u\n", reg);
713		return;
714	}
715
716	field = &variant->registers[reg];
717	base = __vc4_hdmi_get_field_base(hdmi, field->reg);
718	if (!base) {
719		dev_warn(&hdmi->pdev->dev,
720			 "Unknown register ID %u\n", reg);
721		return;
722	}
723
724	writel(value, base + field->offset);
725}
726#define HDMI_WRITE(reg, val)	vc4_hdmi_write(vc4_hdmi, reg, val)
727
728#endif /* _VC4_HDMI_REGS_H_ */
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