tidss_plane.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
  4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  5 */
  6
  7#include <drm/drm_atomic.h>
  8#include <drm/drm_atomic_helper.h>
  9#include <drm/drm_blend.h>
 10#include <drm/drm_crtc.h>
 11#include <drm/drm_fb_dma_helper.h>
 12#include <drm/drm_fourcc.h>
 13#include <drm/drm_framebuffer.h>
 14#include <drm/drm_gem_atomic_helper.h>
 15
 16#include "tidss_crtc.h"
 17#include "tidss_dispc.h"
 18#include "tidss_drv.h"
 19#include "tidss_plane.h"
 20
 21void tidss_plane_error_irq(struct drm_plane *plane, u64 irqstatus)
 22{
 23	struct tidss_plane *tplane = to_tidss_plane(plane);
 24
 25	dev_err_ratelimited(plane->dev->dev, "Plane%u underflow (irq %llx)\n",
 26			    tplane->hw_plane_id, irqstatus);
 27}
 28
 29/* drm_plane_helper_funcs */
 30
 31static int tidss_plane_atomic_check(struct drm_plane *plane,
 32				    struct drm_atomic_state *state)
 33{
 34	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 35										 plane);
 36	struct drm_device *ddev = plane->dev;
 37	struct tidss_device *tidss = to_tidss(ddev);
 38	struct tidss_plane *tplane = to_tidss_plane(plane);
 39	const struct drm_format_info *finfo;
 40	struct drm_crtc_state *crtc_state;
 41	u32 hw_plane = tplane->hw_plane_id;
 42	u32 hw_videoport;
 43	int ret;
 44
 45	if (!new_plane_state->crtc) {
 46		/*
 47		 * The visible field is not reset by the DRM core but only
 48		 * updated by drm_atomic_helper_check_plane_state(), set it
 49		 * manually.
 50		 */
 51		new_plane_state->visible = false;
 52		return 0;
 53	}
 54
 55	crtc_state = drm_atomic_get_crtc_state(state,
 56					       new_plane_state->crtc);
 57	if (IS_ERR(crtc_state))
 58		return PTR_ERR(crtc_state);
 59
 60	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 61						  0,
 62						  INT_MAX, true, true);
 63	if (ret < 0)
 64		return ret;
 65
 66	/*
 67	 * The HW is only able to start drawing at subpixel boundary
 68	 * (the two first checks below). At the end of a row the HW
 69	 * can only jump integer number of subpixels forward to the
 70	 * beginning of the next row. So we can only show picture with
 71	 * integer subpixel width (the third check). However, after
 72	 * reaching the end of the drawn picture the drawing starts
 73	 * again at the absolute memory address where top left corner
 74	 * position of the drawn picture is (so there is no need to
 75	 * check for odd height).
 76	 */
 77
 78	finfo = drm_format_info(new_plane_state->fb->format->format);
 79
 80	if ((new_plane_state->src_x >> 16) % finfo->hsub != 0) {
 81		dev_dbg(ddev->dev,
 82			"%s: x-position %u not divisible subpixel size %u\n",
 83			__func__, (new_plane_state->src_x >> 16), finfo->hsub);
 84		return -EINVAL;
 85	}
 86
 87	if ((new_plane_state->src_y >> 16) % finfo->vsub != 0) {
 88		dev_dbg(ddev->dev,
 89			"%s: y-position %u not divisible subpixel size %u\n",
 90			__func__, (new_plane_state->src_y >> 16), finfo->vsub);
 91		return -EINVAL;
 92	}
 93
 94	if ((new_plane_state->src_w >> 16) % finfo->hsub != 0) {
 95		dev_dbg(ddev->dev,
 96			"%s: src width %u not divisible by subpixel size %u\n",
 97			 __func__, (new_plane_state->src_w >> 16),
 98			 finfo->hsub);
 99		return -EINVAL;
100	}
101
102	if (!new_plane_state->visible)
103		return 0;
104
105	hw_videoport = to_tidss_crtc(new_plane_state->crtc)->hw_videoport;
106
107	ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state,
108				hw_videoport);
109	if (ret)
110		return ret;
111
112	return 0;
113}
114
115static void tidss_plane_atomic_update(struct drm_plane *plane,
116				      struct drm_atomic_state *state)
117{
118	struct drm_device *ddev = plane->dev;
119	struct tidss_device *tidss = to_tidss(ddev);
120	struct tidss_plane *tplane = to_tidss_plane(plane);
121	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
122									   plane);
123	u32 hw_videoport;
124
125	if (!new_state->visible) {
126		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
127		return;
128	}
129
130	hw_videoport = to_tidss_crtc(new_state->crtc)->hw_videoport;
131
132	dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport);
133}
134
135static void tidss_plane_atomic_enable(struct drm_plane *plane,
136				      struct drm_atomic_state *state)
137{
138	struct drm_device *ddev = plane->dev;
139	struct tidss_device *tidss = to_tidss(ddev);
140	struct tidss_plane *tplane = to_tidss_plane(plane);
141
142	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
143}
144
145static void tidss_plane_atomic_disable(struct drm_plane *plane,
146				       struct drm_atomic_state *state)
147{
148	struct drm_device *ddev = plane->dev;
149	struct tidss_device *tidss = to_tidss(ddev);
150	struct tidss_plane *tplane = to_tidss_plane(plane);
151
152	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
153}
154
155static void drm_plane_destroy(struct drm_plane *plane)
156{
157	struct tidss_plane *tplane = to_tidss_plane(plane);
158
159	drm_plane_cleanup(plane);
160	kfree(tplane);
161}
162
163static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
164	.atomic_check = tidss_plane_atomic_check,
165	.atomic_update = tidss_plane_atomic_update,
166	.atomic_enable = tidss_plane_atomic_enable,
167	.atomic_disable = tidss_plane_atomic_disable,
168};
169
170static const struct drm_plane_helper_funcs tidss_primary_plane_helper_funcs = {
171	.atomic_check = tidss_plane_atomic_check,
172	.atomic_update = tidss_plane_atomic_update,
173	.atomic_enable = tidss_plane_atomic_enable,
174	.atomic_disable = tidss_plane_atomic_disable,
175	.get_scanout_buffer = drm_fb_dma_get_scanout_buffer,
176};
177
178static const struct drm_plane_funcs tidss_plane_funcs = {
179	.update_plane = drm_atomic_helper_update_plane,
180	.disable_plane = drm_atomic_helper_disable_plane,
181	.reset = drm_atomic_helper_plane_reset,
182	.destroy = drm_plane_destroy,
183	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
184	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
185};
186
187struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
188				       u32 hw_plane_id, u32 plane_type,
189				       u32 crtc_mask, const u32 *formats,
190				       u32 num_formats)
191{
192	struct tidss_plane *tplane;
193	enum drm_plane_type type;
194	u32 possible_crtcs;
195	u32 num_planes = tidss->feat->num_vids;
196	u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
197			       BIT(DRM_COLOR_YCBCR_BT709));
198	u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
199			    BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
200	u32 default_encoding = DRM_COLOR_YCBCR_BT601;
201	u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
202	u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
203			   BIT(DRM_MODE_BLEND_COVERAGE));
204	int ret;
205
206	tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
207	if (!tplane)
208		return ERR_PTR(-ENOMEM);
209
210	tplane->hw_plane_id = hw_plane_id;
211
212	possible_crtcs = crtc_mask;
213	type = plane_type;
214
215	ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
216				       possible_crtcs,
217				       &tidss_plane_funcs,
218				       formats, num_formats,
219				       NULL, type, NULL);
220	if (ret < 0)
221		goto err;
222
223	if (type == DRM_PLANE_TYPE_PRIMARY)
224		drm_plane_helper_add(&tplane->plane, &tidss_primary_plane_helper_funcs);
225	else
226		drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
227
228	drm_plane_create_zpos_property(&tplane->plane, tidss->num_planes, 0,
229				       num_planes - 1);
230
231	ret = drm_plane_create_color_properties(&tplane->plane,
232						color_encodings,
233						color_ranges,
234						default_encoding,
235						default_range);
236	if (ret)
237		goto err;
238
239	ret = drm_plane_create_alpha_property(&tplane->plane);
240	if (ret)
241		goto err;
242
243	ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
244	if (ret)
245		goto err;
246
247	return tplane;
248
249err:
250	kfree(tplane);
251	return ERR_PTR(ret);
252}