tidss_dispc_regs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
  4 * Author: Jyri Sarha <jsarha@ti.com>
  5 */
  6
  7#ifndef __TIDSS_DISPC_REGS_H
  8#define __TIDSS_DISPC_REGS_H
  9
 10enum dispc_common_regs {
 11	NOT_APPLICABLE_OFF = 0,
 12	DSS_REVISION_OFF,
 13	DSS_SYSCONFIG_OFF,
 14	DSS_SYSSTATUS_OFF,
 15	DISPC_IRQ_EOI_OFF,
 16	DISPC_IRQSTATUS_RAW_OFF,
 17	DISPC_IRQSTATUS_OFF,
 18	DISPC_IRQENABLE_SET_OFF,
 19	DISPC_IRQENABLE_CLR_OFF,
 20	DISPC_VID_IRQENABLE_OFF,
 21	DISPC_VID_IRQSTATUS_OFF,
 22	DISPC_VP_IRQENABLE_OFF,
 23	DISPC_VP_IRQSTATUS_OFF,
 24	WB_IRQENABLE_OFF,
 25	WB_IRQSTATUS_OFF,
 26	DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF,
 27	DISPC_GLOBAL_OUTPUT_ENABLE_OFF,
 28	DISPC_GLOBAL_BUFFER_OFF,
 29	DSS_CBA_CFG_OFF,
 30	DISPC_DBG_CONTROL_OFF,
 31	DISPC_DBG_STATUS_OFF,
 32	DISPC_CLKGATING_DISABLE_OFF,
 33	DISPC_SECURE_DISABLE_OFF,
 34	FBDC_REVISION_1_OFF,
 35	FBDC_REVISION_2_OFF,
 36	FBDC_REVISION_3_OFF,
 37	FBDC_REVISION_4_OFF,
 38	FBDC_REVISION_5_OFF,
 39	FBDC_REVISION_6_OFF,
 40	FBDC_COMMON_CONTROL_OFF,
 41	FBDC_CONSTANT_COLOR_0_OFF,
 42	FBDC_CONSTANT_COLOR_1_OFF,
 43	DISPC_CONNECTIONS_OFF,
 44	DISPC_MSS_VP1_OFF,
 45	DISPC_MSS_VP3_OFF,
 46	DISPC_COMMON_REG_TABLE_LEN,
 47};
 48
 49/*
 50 * dispc_common_regmap should be defined as const u16 * and pointing
 51 * to a valid dss common register map for the platform, before the
 52 * macros below can be used.
 53 */
 54
 55#define REG(r) (dispc_common_regmap[r ## _OFF])
 56
 57#define DSS_REVISION			REG(DSS_REVISION)
 58#define DSS_SYSCONFIG			REG(DSS_SYSCONFIG)
 59#define DSS_SYSCONFIG_SOFTRESET_MASK		GENMASK(1, 1)
 60
 61#define DSS_SYSSTATUS			REG(DSS_SYSSTATUS)
 62#define DSS_SYSSTATUS_DISPC_IDLE_STATUS		GENMASK(9, 9)
 63#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE	GENMASK(0, 0)
 64
 65#define DISPC_IRQ_EOI			REG(DISPC_IRQ_EOI)
 66#define DISPC_IRQSTATUS_RAW		REG(DISPC_IRQSTATUS_RAW)
 67#define DISPC_IRQSTATUS			REG(DISPC_IRQSTATUS)
 68#define DISPC_IRQENABLE_SET		REG(DISPC_IRQENABLE_SET)
 69#define DISPC_IRQENABLE_CLR		REG(DISPC_IRQENABLE_CLR)
 70#define DISPC_VID_IRQENABLE(n)		(REG(DISPC_VID_IRQENABLE) + (n) * 4)
 71#define DISPC_VID_IRQSTATUS(n)		(REG(DISPC_VID_IRQSTATUS) + (n) * 4)
 72#define DISPC_VP_IRQENABLE(n)		(REG(DISPC_VP_IRQENABLE) + (n) * 4)
 73#define DISPC_VP_IRQSTATUS(n)		(REG(DISPC_VP_IRQSTATUS) + (n) * 4)
 74#define WB_IRQENABLE			REG(WB_IRQENABLE)
 75#define WB_IRQSTATUS			REG(WB_IRQSTATUS)
 76
 77#define DISPC_GLOBAL_MFLAG_ATTRIBUTE	REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE)
 78#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK	GENMASK(6, 6)
 79#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK	GENMASK(1, 0)
 80
 81#define DISPC_GLOBAL_OUTPUT_ENABLE	REG(DISPC_GLOBAL_OUTPUT_ENABLE)
 82#define DISPC_GLOBAL_BUFFER		REG(DISPC_GLOBAL_BUFFER)
 83#define DSS_CBA_CFG			REG(DSS_CBA_CFG)
 84#define DSS_CBA_CFG_PRI_HI_MASK			GENMASK(5, 3)
 85#define DSS_CBA_CFG_PRI_LO_MASK			GENMASK(2, 0)
 86
 87#define DISPC_DBG_CONTROL		REG(DISPC_DBG_CONTROL)
 88#define DISPC_DBG_STATUS		REG(DISPC_DBG_STATUS)
 89#define DISPC_CLKGATING_DISABLE		REG(DISPC_CLKGATING_DISABLE)
 90#define DISPC_SECURE_DISABLE		REG(DISPC_SECURE_DISABLE)
 91
 92#define FBDC_REVISION_1			REG(FBDC_REVISION_1)
 93#define FBDC_REVISION_2			REG(FBDC_REVISION_2)
 94#define FBDC_REVISION_3			REG(FBDC_REVISION_3)
 95#define FBDC_REVISION_4			REG(FBDC_REVISION_4)
 96#define FBDC_REVISION_5			REG(FBDC_REVISION_5)
 97#define FBDC_REVISION_6			REG(FBDC_REVISION_6)
 98#define FBDC_COMMON_CONTROL		REG(FBDC_COMMON_CONTROL)
 99#define FBDC_CONSTANT_COLOR_0		REG(FBDC_CONSTANT_COLOR_0)
100#define FBDC_CONSTANT_COLOR_1		REG(FBDC_CONSTANT_COLOR_1)
101#define DISPC_CONNECTIONS		REG(DISPC_CONNECTIONS)
102#define DISPC_CONNECTIONS_DPI_1_CONN_MASK	GENMASK(7, 4)
103#define DISPC_CONNECTIONS_DPI_0_CONN_MASK	GENMASK(3, 0)
104
105#define DISPC_MSS_VP1			REG(DISPC_MSS_VP1)
106#define DISPC_MSS_VP3			REG(DISPC_MSS_VP3)
107
108/* VID */
109
110#define DISPC_VID_ACCUH_0		0x0
111#define DISPC_VID_ACCUH_1		0x4
112#define DISPC_VID_ACCUH2_0		0x8
113#define DISPC_VID_ACCUH2_1		0xc
114#define DISPC_VID_ACCUV_0		0x10
115#define DISPC_VID_ACCUV_1		0x14
116#define DISPC_VID_ACCUV2_0		0x18
117#define DISPC_VID_ACCUV2_1		0x1c
118#define DISPC_VID_ATTRIBUTES		0x20
119#define DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK	GENMASK(28, 28)
120#define DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK		GENMASK(21, 21)
121#define DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK		GENMASK(19, 19)
122#define DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK	GENMASK(9, 9)
123#define DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK		GENMASK(8, 8)
124#define DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK		GENMASK(7, 7)
125#define DISPC_VID_ATTRIBUTES_FORMAT_MASK		GENMASK(6, 1)
126#define DISPC_VID_ATTRIBUTES_ENABLE_MASK		GENMASK(0, 0)
127
128#define DISPC_VID_ATTRIBUTES2		0x24
129#define DISPC_VID_BA_0			0x28
130#define DISPC_VID_BA_1			0x2c
131#define DISPC_VID_BA_UV_0		0x30
132#define DISPC_VID_BA_UV_1		0x34
133#define DISPC_VID_BUF_SIZE_STATUS	0x38
134#define DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK	GENMASK(15, 0)
135
136#define DISPC_VID_BUF_THRESHOLD		0x3c
137#define DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK	GENMASK(31, 16)
138#define DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK	GENMASK(15, 0)
139
140#define DISPC_VID_CSC_COEF(n)		(0x40 + (n) * 4)
141
142#define DISPC_VID_FIRH			0x5c
143#define DISPC_VID_FIRH2			0x60
144#define DISPC_VID_FIRV			0x64
145#define DISPC_VID_FIRV2			0x68
146
147#define DISPC_VID_FIR_COEFS_H0		0x6c
148#define DISPC_VID_FIR_COEF_H0(phase)	(0x6c + (phase) * 4)
149#define DISPC_VID_FIR_COEFS_H0_C	0x90
150#define DISPC_VID_FIR_COEF_H0_C(phase)	(0x90 + (phase) * 4)
151
152#define DISPC_VID_FIR_COEFS_H12		0xb4
153#define DISPC_VID_FIR_COEF_H12(phase)	(0xb4 + (phase) * 4)
154#define DISPC_VID_FIR_COEFS_H12_C	0xf4
155#define DISPC_VID_FIR_COEF_H12_C(phase)	(0xf4 + (phase) * 4)
156
157#define DISPC_VID_FIR_COEFS_V0		0x134
158#define DISPC_VID_FIR_COEF_V0(phase)	(0x134 + (phase) * 4)
159#define DISPC_VID_FIR_COEFS_V0_C	0x158
160#define DISPC_VID_FIR_COEF_V0_C(phase)	(0x158 + (phase) * 4)
161
162#define DISPC_VID_FIR_COEFS_V12		0x17c
163#define DISPC_VID_FIR_COEF_V12(phase)	(0x17c + (phase) * 4)
164#define DISPC_VID_FIR_COEFS_V12_C	0x1bc
165#define DISPC_VID_FIR_COEF_V12_C(phase)	(0x1bc + (phase) * 4)
166
167#define DISPC_VID_GLOBAL_ALPHA		0x1fc
168#define DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK	GENMASK(7, 0)
169
170#define DISPC_VID_K2G_IRQENABLE		0x200 /* K2G */
171#define DISPC_VID_K2G_IRQSTATUS		0x204 /* K2G */
172#define DISPC_VID_MFLAG_THRESHOLD	0x208
173#define DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK	GENMASK(31, 16)
174#define DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK	GENMASK(15, 0)
175
176#define DISPC_VID_PICTURE_SIZE		0x20c
177#define DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK	GENMASK(27, 16)
178#define DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK	GENMASK(11, 0)
179
180#define DISPC_VID_PIXEL_INC		0x210
181#define DISPC_VID_K2G_POSITION		0x214 /* K2G */
182#define DISPC_VID_PRELOAD		0x218
183#define DISPC_VID_ROW_INC		0x21c
184#define DISPC_VID_SIZE			0x220
185#define DISPC_VID_SIZE_SIZEY_MASK		GENMASK(27, 16)
186#define DISPC_VID_SIZE_SIZEX_MASK		GENMASK(11, 0)
187
188#define DISPC_VID_BA_EXT_0		0x22c
189#define DISPC_VID_BA_EXT_1		0x230
190#define DISPC_VID_BA_UV_EXT_0		0x234
191#define DISPC_VID_BA_UV_EXT_1		0x238
192#define DISPC_VID_CSC_COEF7		0x23c
193#define DISPC_VID_ROW_INC_UV		0x248
194#define DISPC_VID_CLUT			0x260
195#define DISPC_VID_SAFETY_ATTRIBUTES	0x2a0
196#define DISPC_VID_SAFETY_CAPT_SIGNATURE	0x2a4
197#define DISPC_VID_SAFETY_POSITION	0x2a8
198#define DISPC_VID_SAFETY_REF_SIGNATURE	0x2ac
199#define DISPC_VID_SAFETY_SIZE		0x2b0
200#define DISPC_VID_SAFETY_LFSR_SEED	0x2b4
201#define DISPC_VID_LUMAKEY		0x2b8
202#define DISPC_VID_DMA_BUFSIZE		0x2bc /* J721E */
203
204/* OVR */
205
206#define DISPC_OVR_CONFIG		0x0
207#define DISPC_OVR_VIRTVP		0x4 /* J721E */
208#define DISPC_OVR_DEFAULT_COLOR		0x8
209#define DISPC_OVR_DEFAULT_COLOR2	0xc
210#define DISPC_OVR_TRANS_COLOR_MAX	0x10
211#define DISPC_OVR_TRANS_COLOR_MAX2	0x14
212#define DISPC_OVR_TRANS_COLOR_MIN	0x18
213#define DISPC_OVR_TRANS_COLOR_MIN2	0x1c
214#define DISPC_OVR_ATTRIBUTES(n)		(0x20 + (n) * 4)
215#define DISPC_OVR_ATTRIBUTES_POSY_MASK		GENMASK(30, 19)
216#define DISPC_OVR_ATTRIBUTES_POSX_MASK		GENMASK(17, 6)
217#define DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK	GENMASK(4, 1)
218#define DISPC_OVR_ATTRIBUTES_ENABLE_MASK	GENMASK(0, 0)
219
220#define DISPC_OVR_ATTRIBUTES2(n)	(0x34 + (n) * 4) /* J721E */
221#define DISPC_OVR_ATTRIBUTES2_POSY_MASK		GENMASK(29, 16)
222#define DISPC_OVR_ATTRIBUTES2_POSX_MASK		GENMASK(13, 0)
223
224/* VP */
225
226#define DISPC_VP_CONFIG				0x0
227#define DISPC_VP_CONFIG_COLORCONVENABLE_MASK		GENMASK(24, 24)
228#define DISPC_VP_CONFIG_CPR_MASK			GENMASK(15, 15)
229#define DISPC_VP_CONFIG_GAMMAENABLE_MASK		GENMASK(2, 2)
230
231#define DISPC_VP_CONTROL			0x4
232#define DISPC_VP_CONTROL_DATALINES_MASK			GENMASK(10, 8)
233#define DISPC_VP_CONTROL_GOBIT_MASK			GENMASK(5, 5)
234#define DISPC_VP_CONTROL_ENABLE_MASK			GENMASK(0, 0)
235
236#define DISPC_VP_CSC_COEF0			0x8
237#define DISPC_VP_CSC_COEF1			0xc
238#define DISPC_VP_CSC_COEF2			0x10
239#define DISPC_VP_DATA_CYCLE_0			0x14
240#define DISPC_VP_DATA_CYCLE_1			0x18
241#define DISPC_VP_K2G_GAMMA_TABLE		0x20 /* K2G */
242#define DISPC_VP_K2G_IRQENABLE			0x3c /* K2G */
243#define DISPC_VP_K2G_IRQSTATUS			0x40 /* K2G */
244#define DISPC_VP_DATA_CYCLE_2			0x1c
245#define DISPC_VP_LINE_NUMBER			0x44
246#define DISPC_VP_POL_FREQ			0x4c
247#define DISPC_VP_POL_FREQ_ALIGN_MASK			GENMASK(18, 18)
248#define DISPC_VP_POL_FREQ_ONOFF_MASK			GENMASK(17, 17)
249#define DISPC_VP_POL_FREQ_RF_MASK			GENMASK(16, 16)
250#define DISPC_VP_POL_FREQ_IEO_MASK			GENMASK(15, 15)
251#define DISPC_VP_POL_FREQ_IPC_MASK			GENMASK(14, 14)
252#define DISPC_VP_POL_FREQ_IHS_MASK			GENMASK(13, 13)
253#define DISPC_VP_POL_FREQ_IVS_MASK			GENMASK(12, 12)
254
255#define DISPC_VP_SIZE_SCREEN			0x50
256#define DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK		GENMASK(11, 0)
257#define DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK		GENMASK(27, 16)
258
259#define DISPC_VP_TIMING_H			0x54
260#define DISPC_VP_TIMING_H_SYNC_PULSE_MASK		GENMASK(7, 0)
261#define DISPC_VP_TIMING_H_FRONT_PORCH_MASK		GENMASK(19, 8)
262#define DISPC_VP_TIMING_H_BACK_PORCH_MASK		GENMASK(31, 20)
263
264#define DISPC_VP_TIMING_V			0x58
265#define DISPC_VP_TIMING_V_SYNC_PULSE_MASK		GENMASK(7, 0)
266#define DISPC_VP_TIMING_V_FRONT_PORCH_MASK		GENMASK(19, 8)
267#define DISPC_VP_TIMING_V_BACK_PORCH_MASK		GENMASK(31, 20)
268
269#define DISPC_VP_CSC_COEF3			0x5c
270#define DISPC_VP_CSC_COEF4			0x60
271#define DISPC_VP_CSC_COEF5			0x64
272#define DISPC_VP_CSC_COEF6			0x68
273#define DISPC_VP_CSC_COEF7			0x6c
274#define DISPC_VP_SAFETY_ATTRIBUTES_0		0x70
275#define DISPC_VP_SAFETY_ATTRIBUTES_1		0x74
276#define DISPC_VP_SAFETY_ATTRIBUTES_2		0x78
277#define DISPC_VP_SAFETY_ATTRIBUTES_3		0x7c
278#define DISPC_VP_SAFETY_CAPT_SIGNATURE_0	0x90
279#define DISPC_VP_SAFETY_CAPT_SIGNATURE_1	0x94
280#define DISPC_VP_SAFETY_CAPT_SIGNATURE_2	0x98
281#define DISPC_VP_SAFETY_CAPT_SIGNATURE_3	0x9c
282#define DISPC_VP_SAFETY_POSITION_0		0xb0
283#define DISPC_VP_SAFETY_POSITION_1		0xb4
284#define DISPC_VP_SAFETY_POSITION_2		0xb8
285#define DISPC_VP_SAFETY_POSITION_3		0xbc
286#define DISPC_VP_SAFETY_REF_SIGNATURE_0		0xd0
287#define DISPC_VP_SAFETY_REF_SIGNATURE_1		0xd4
288#define DISPC_VP_SAFETY_REF_SIGNATURE_2		0xd8
289#define DISPC_VP_SAFETY_REF_SIGNATURE_3		0xdc
290#define DISPC_VP_SAFETY_SIZE_0			0xf0
291#define DISPC_VP_SAFETY_SIZE_1			0xf4
292#define DISPC_VP_SAFETY_SIZE_2			0xf8
293#define DISPC_VP_SAFETY_SIZE_3			0xfc
294#define DISPC_VP_SAFETY_LFSR_SEED		0x110
295#define DISPC_VP_GAMMA_TABLE			0x120
296#define DISPC_VP_DSS_OLDI_CFG			0x160
297#define DISPC_VP_DSS_OLDI_CFG_MAP_MASK			GENMASK(3, 1)
298
299#define DISPC_VP_DSS_OLDI_STATUS		0x164
300#define DISPC_VP_DSS_OLDI_LB			0x168
301#define DISPC_VP_DSS_MERGE_SPLIT		0x16c /* J721E */
302#define DISPC_VP_DSS_DMA_THREADSIZE		0x170 /* J721E */
303#define DISPC_VP_DSS_DMA_THREADSIZE_STATUS	0x174 /* J721E */
304
305/* OLDI Config Bits (DISPC_VP_DSS_OLDI_CFG) */
306#define OLDI_ENABLE		BIT(0)
307#define OLDI_MAP		(BIT(1) | BIT(2) | BIT(3))
308#define OLDI_SRC		BIT(4)
309#define OLDI_CLONE_MODE		BIT(5)
310#define OLDI_MASTERSLAVE	BIT(6)
311#define OLDI_DEPOL		BIT(7)
312#define OLDI_MSB		BIT(8)
313#define OLDI_LBEN		BIT(9)
314#define OLDI_LBDATA		BIT(10)
315#define OLDI_DUALMODESYNC	BIT(11)
316#define OLDI_SOFTRST		BIT(12)
317#define OLDI_TPATCFG		BIT(13)
318
319/* LVDS Format values for OLDI_MAP field in DISPC_VP_OLDI_CFG register */
320enum oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 };
321
322/*
323 * OLDI IO_CTRL register offsets. On AM654 the registers are found
324 * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from
325 * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL
326 * register range.
327 */
328#define AM65X_OLDI_DAT0_IO_CTRL		0x00
329#define AM65X_OLDI_DAT1_IO_CTRL		0x04
330#define AM65X_OLDI_DAT2_IO_CTRL		0x08
331#define AM65X_OLDI_DAT3_IO_CTRL		0x0C
332#define AM65X_OLDI_CLK_IO_CTRL		0x10
333
334#define AM65X_OLDI_PWRDN_TX		BIT(8)
335
336#endif /* __TIDSS_DISPC_REGS_H */