FILE
hdmi.c
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linux-6.19.14/drivers/gpu/drm/tegra/hdmi.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7#include <linux/clk.h> 8#include <linux/debugfs.h> 9#include <linux/delay.h> 10#include <linux/hdmi.h> 11#include <linux/math64.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/pm_opp.h> 16#include <linux/pm_runtime.h> 17#include <linux/regulator/consumer.h> 18#include <linux/reset.h> 19 20#include <soc/tegra/common.h> 21#include <sound/hdmi-codec.h> 22 23#include <drm/drm_bridge_connector.h> 24#include <drm/drm_atomic_helper.h> 25#include <drm/drm_crtc.h> 26#include <drm/drm_debugfs.h> 27#include <drm/drm_edid.h> 28#include <drm/drm_eld.h> 29#include <drm/drm_file.h> 30#include <drm/drm_fourcc.h> 31#include <drm/drm_print.h> 32#include <drm/drm_probe_helper.h> 33#include <drm/drm_simple_kms_helper.h> 34 35#include "hda.h" 36#include "hdmi.h" 37#include "drm.h" 38#include "dc.h" 39#include "trace.h" 40 41#define HDMI_ELD_BUFFER_SIZE 96 42 43struct tmds_config { 44 unsigned int pclk; 45 u32 pll0; 46 u32 pll1; 47 u32 pe_current; 48 u32 drive_current; 49 u32 peak_current; 50}; 51 52struct tegra_hdmi_config { 53 const struct tmds_config *tmds; 54 unsigned int num_tmds; 55 56 unsigned long fuse_override_offset; 57 u32 fuse_override_value; 58 59 bool has_sor_io_peak_current; 60 bool has_hda; 61 bool has_hbr; 62}; 63 64struct tegra_hdmi { 65 struct host1x_client client; 66 struct tegra_output output; 67 struct device *dev; 68 69 struct regulator *hdmi; 70 struct regulator *pll; 71 struct regulator *vdd; 72 73 void __iomem *regs; 74 unsigned int irq; 75 76 struct clk *clk_parent; 77 struct clk *clk; 78 struct reset_control *rst; 79 80 const struct tegra_hdmi_config *config; 81 82 unsigned int audio_source; 83 struct tegra_hda_format format; 84 85 unsigned int pixel_clock; 86 bool stereo; 87 bool dvi; 88 89 struct drm_info_list *debugfs_files; 90 91 struct platform_device *audio_pdev; 92 struct mutex audio_lock; 93}; 94 95static inline struct tegra_hdmi * 96host1x_client_to_hdmi(struct host1x_client *client) 97{ 98 return container_of(client, struct tegra_hdmi, client); 99} 100 101static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) 102{ 103 return container_of(output, struct tegra_hdmi, output); 104} 105 106#define HDMI_AUDIOCLK_FREQ 216000000 107#define HDMI_REKEY_DEFAULT 56 108 109enum { 110 AUTO = 0, 111 SPDIF, 112 HDA, 113}; 114 115static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, 116 unsigned int offset) 117{ 118 u32 value = readl(hdmi->regs + (offset << 2)); 119 120 trace_hdmi_readl(hdmi->dev, offset, value); 121 122 return value; 123} 124 125static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, 126 unsigned int offset) 127{ 128 trace_hdmi_writel(hdmi->dev, offset, value); 129 writel(value, hdmi->regs + (offset << 2)); 130} 131 132struct tegra_hdmi_audio_config { 133 unsigned int n; 134 unsigned int cts; 135 unsigned int aval; 136}; 137 138static const struct tmds_config tegra20_tmds_config[] = { 139 { /* slow pixel clock modes */ 140 .pclk = 27000000, 141 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 142 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 143 SOR_PLL_TX_REG_LOAD(3), 144 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 145 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 146 PE_CURRENT1(PE_CURRENT_0_0_mA) | 147 PE_CURRENT2(PE_CURRENT_0_0_mA) | 148 PE_CURRENT3(PE_CURRENT_0_0_mA), 149 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 150 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 151 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 152 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 153 }, 154 { /* high pixel clock modes */ 155 .pclk = UINT_MAX, 156 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 157 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 158 SOR_PLL_TX_REG_LOAD(3), 159 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 160 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | 161 PE_CURRENT1(PE_CURRENT_6_0_mA) | 162 PE_CURRENT2(PE_CURRENT_6_0_mA) | 163 PE_CURRENT3(PE_CURRENT_6_0_mA), 164 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 165 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 166 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 167 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 168 }, 169}; 170 171static const struct tmds_config tegra30_tmds_config[] = { 172 { /* 480p modes */ 173 .pclk = 27000000, 174 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 175 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 176 SOR_PLL_TX_REG_LOAD(0), 177 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 178 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 179 PE_CURRENT1(PE_CURRENT_0_0_mA) | 180 PE_CURRENT2(PE_CURRENT_0_0_mA) | 181 PE_CURRENT3(PE_CURRENT_0_0_mA), 182 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 183 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 184 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 185 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 186 }, { /* 720p modes */ 187 .pclk = 74250000, 188 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 189 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 190 SOR_PLL_TX_REG_LOAD(0), 191 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 192 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 193 PE_CURRENT1(PE_CURRENT_5_0_mA) | 194 PE_CURRENT2(PE_CURRENT_5_0_mA) | 195 PE_CURRENT3(PE_CURRENT_5_0_mA), 196 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 197 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 198 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 199 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 200 }, { /* 1080p modes */ 201 .pclk = UINT_MAX, 202 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 203 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | 204 SOR_PLL_TX_REG_LOAD(0), 205 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 206 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 207 PE_CURRENT1(PE_CURRENT_5_0_mA) | 208 PE_CURRENT2(PE_CURRENT_5_0_mA) | 209 PE_CURRENT3(PE_CURRENT_5_0_mA), 210 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 211 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 212 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 213 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 214 }, 215}; 216 217static const struct tmds_config tegra114_tmds_config[] = { 218 { /* 480p/576p / 25.2MHz/27MHz modes */ 219 .pclk = 27000000, 220 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 221 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 222 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 223 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 224 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 225 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 226 PE_CURRENT3(PE_CURRENT_0_mA_T114), 227 .drive_current = 228 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 229 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 230 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 231 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 232 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 233 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 234 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 235 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 236 }, { /* 720p / 74.25MHz modes */ 237 .pclk = 74250000, 238 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 239 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 240 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 241 SOR_PLL_TMDS_TERMADJ(0), 242 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 243 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 244 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 245 PE_CURRENT3(PE_CURRENT_15_mA_T114), 246 .drive_current = 247 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 248 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 249 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 250 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 251 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 252 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 253 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 254 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 255 }, { /* 1080p / 148.5MHz modes */ 256 .pclk = 148500000, 257 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 258 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 259 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 260 SOR_PLL_TMDS_TERMADJ(0), 261 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 262 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 263 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 264 PE_CURRENT3(PE_CURRENT_10_mA_T114), 265 .drive_current = 266 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 267 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 268 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 269 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 270 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 271 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 272 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 273 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 274 }, { /* 225/297MHz modes */ 275 .pclk = UINT_MAX, 276 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 277 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 278 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 279 | SOR_PLL_TMDS_TERM_ENABLE, 280 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 281 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 282 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 283 PE_CURRENT3(PE_CURRENT_0_mA_T114), 284 .drive_current = 285 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 286 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 287 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 288 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 289 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 290 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 291 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 292 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 293 }, 294}; 295 296static const struct tmds_config tegra124_tmds_config[] = { 297 { /* 480p/576p / 25.2MHz/27MHz modes */ 298 .pclk = 27000000, 299 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 300 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 301 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 302 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 303 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 304 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 305 PE_CURRENT3(PE_CURRENT_0_mA_T114), 306 .drive_current = 307 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 308 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 309 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 310 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 311 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 312 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 313 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 314 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 315 }, { /* 720p / 74.25MHz modes */ 316 .pclk = 74250000, 317 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 318 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 319 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 320 SOR_PLL_TMDS_TERMADJ(0), 321 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 322 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 323 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 324 PE_CURRENT3(PE_CURRENT_15_mA_T114), 325 .drive_current = 326 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 327 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 328 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 329 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 330 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 331 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 332 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 333 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 334 }, { /* 1080p / 148.5MHz modes */ 335 .pclk = 148500000, 336 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 337 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 338 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 339 SOR_PLL_TMDS_TERMADJ(0), 340 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 341 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 342 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 343 PE_CURRENT3(PE_CURRENT_10_mA_T114), 344 .drive_current = 345 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 346 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 347 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 348 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 349 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 350 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 351 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 352 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 353 }, { /* 225/297MHz modes */ 354 .pclk = UINT_MAX, 355 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 356 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 357 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 358 | SOR_PLL_TMDS_TERM_ENABLE, 359 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 360 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 361 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 362 PE_CURRENT3(PE_CURRENT_0_mA_T114), 363 .drive_current = 364 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 365 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 366 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 367 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 368 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 369 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 370 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 371 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 372 }, 373}; 374 375static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi) 376{ 377 mutex_lock(&hdmi->audio_lock); 378 disable_irq(hdmi->irq); 379} 380 381static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi) 382{ 383 enable_irq(hdmi->irq); 384 mutex_unlock(&hdmi->audio_lock); 385} 386 387static int 388tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock, 389 struct tegra_hdmi_audio_config *config) 390{ 391 const unsigned int afreq = 128 * audio_freq; 392 const unsigned int min_n = afreq / 1500; 393 const unsigned int max_n = afreq / 300; 394 const unsigned int ideal_n = afreq / 1000; 395 int64_t min_err = (uint64_t)-1 >> 1; 396 unsigned int min_delta = -1; 397 int n; 398 399 memset(config, 0, sizeof(*config)); 400 config->n = -1; 401 402 for (n = min_n; n <= max_n; n++) { 403 uint64_t cts_f, aval_f; 404 unsigned int delta; 405 int64_t cts, err; 406 407 /* compute aval in 48.16 fixed point */ 408 aval_f = ((int64_t)24000000 << 16) * n; 409 do_div(aval_f, afreq); 410 /* It should round without any rest */ 411 if (aval_f & 0xFFFF) 412 continue; 413 414 /* Compute cts in 48.16 fixed point */ 415 cts_f = ((int64_t)pix_clock << 16) * n; 416 do_div(cts_f, afreq); 417 /* Round it to the nearest integer */ 418 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1); 419 420 delta = abs(n - ideal_n); 421 422 /* Compute the absolute error */ 423 err = abs((int64_t)cts_f - cts); 424 if (err < min_err || (err == min_err && delta < min_delta)) { 425 config->n = n; 426 config->cts = cts >> 16; 427 config->aval = aval_f >> 16; 428 min_delta = delta; 429 min_err = err; 430 } 431 } 432 433 return config->n != -1 ? 0 : -EINVAL; 434} 435 436static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) 437{ 438 static const unsigned int freqs[] = { 439 32000, 44100, 48000, 88200, 96000, 176400, 192000 440 }; 441 unsigned int i; 442 443 for (i = 0; i < ARRAY_SIZE(freqs); i++) { 444 unsigned int f = freqs[i]; 445 unsigned int eight_half; 446 unsigned int delta; 447 u32 value; 448 449 if (f > 96000) 450 delta = 2; 451 else if (f > 48000) 452 delta = 6; 453 else 454 delta = 9; 455 456 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); 457 value = AUDIO_FS_LOW(eight_half - delta) | 458 AUDIO_FS_HIGH(eight_half + delta); 459 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); 460 } 461} 462 463static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value) 464{ 465 static const struct { 466 unsigned int sample_rate; 467 unsigned int offset; 468 } regs[] = { 469 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 }, 470 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 }, 471 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 }, 472 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 }, 473 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 }, 474 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 }, 475 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 }, 476 }; 477 unsigned int i; 478 479 for (i = 0; i < ARRAY_SIZE(regs); i++) { 480 if (regs[i].sample_rate == hdmi->format.sample_rate) { 481 tegra_hdmi_writel(hdmi, value, regs[i].offset); 482 break; 483 } 484 } 485} 486 487static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi) 488{ 489 struct tegra_hdmi_audio_config config; 490 u32 source, value; 491 int err; 492 493 switch (hdmi->audio_source) { 494 case HDA: 495 if (hdmi->config->has_hda) 496 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL; 497 else 498 return -EINVAL; 499 500 break; 501 502 case SPDIF: 503 if (hdmi->config->has_hda) 504 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 505 else 506 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 507 break; 508 509 default: 510 if (hdmi->config->has_hda) 511 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 512 else 513 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 514 break; 515 } 516 517 /* 518 * Tegra30 and later use a slightly modified version of the register 519 * layout to accomodate for changes related to supporting HDA as the 520 * audio input source for HDMI. The source select field has moved to 521 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames 522 * per block fields remain in the AUDIO_CNTRL0 register. 523 */ 524 if (hdmi->config->has_hda) { 525 /* 526 * Inject null samples into the audio FIFO for every frame in 527 * which the codec did not receive any samples. This applies 528 * to stereo LPCM only. 529 * 530 * XXX: This seems to be a remnant of MCP days when this was 531 * used to work around issues with monitors not being able to 532 * play back system startup sounds early. It is possibly not 533 * needed on Linux at all. 534 */ 535 if (hdmi->format.channels == 2) 536 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL; 537 else 538 value = 0; 539 540 value |= source; 541 542 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); 543 } 544 545 /* 546 * On Tegra20, HDA is not a supported audio source and the source 547 * select field is part of the AUDIO_CNTRL0 register. 548 */ 549 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) | 550 AUDIO_CNTRL0_ERROR_TOLERANCE(6); 551 552 if (!hdmi->config->has_hda) 553 value |= source; 554 555 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); 556 557 /* 558 * Advertise support for High Bit-Rate on Tegra114 and later. 559 */ 560 if (hdmi->config->has_hbr) { 561 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 562 value |= SOR_AUDIO_SPARE0_HBR_ENABLE; 563 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 564 } 565 566 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate, 567 hdmi->pixel_clock, &config); 568 if (err < 0) { 569 dev_err(hdmi->dev, 570 "cannot set audio to %u Hz at %u Hz pixel clock\n", 571 hdmi->format.sample_rate, hdmi->pixel_clock); 572 return err; 573 } 574 575 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n", 576 hdmi->pixel_clock, config.n, config.cts, config.aval); 577 578 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); 579 580 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | 581 AUDIO_N_VALUE(config.n - 1); 582 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 583 584 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE, 585 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); 586 587 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts), 588 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); 589 590 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); 591 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); 592 593 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); 594 value &= ~AUDIO_N_RESETF; 595 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 596 597 if (hdmi->config->has_hda) 598 tegra_hdmi_write_aval(hdmi, config.aval); 599 600 tegra_hdmi_setup_audio_fs_tables(hdmi); 601 602 return 0; 603} 604 605static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi) 606{ 607 u32 value; 608 609 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 610 value &= ~GENERIC_CTRL_AUDIO; 611 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 612} 613 614static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi) 615{ 616 u32 value; 617 618 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 619 value |= GENERIC_CTRL_AUDIO; 620 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 621} 622 623static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi) 624{ 625 size_t length = drm_eld_size(hdmi->output.connector.eld), i; 626 u32 value; 627 628 for (i = 0; i < length; i++) 629 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i], 630 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 631 632 /* 633 * The HDA codec will always report an ELD buffer size of 96 bytes and 634 * the HDA codec driver will check that each byte read from the buffer 635 * is valid. Therefore every byte must be written, even if no 96 bytes 636 * were parsed from EDID. 637 */ 638 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++) 639 tegra_hdmi_writel(hdmi, i << 8 | 0, 640 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 641 642 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT; 643 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 644} 645 646static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size) 647{ 648 u32 value = 0; 649 size_t i; 650 651 for (i = size; i > 0; i--) 652 value = (value << 8) | ptr[i - 1]; 653 654 return value; 655} 656 657static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, 658 size_t size) 659{ 660 const u8 *ptr = data; 661 unsigned long offset; 662 size_t i; 663 u32 value; 664 665 switch (ptr[0]) { 666 case HDMI_INFOFRAME_TYPE_AVI: 667 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; 668 break; 669 670 case HDMI_INFOFRAME_TYPE_AUDIO: 671 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; 672 break; 673 674 case HDMI_INFOFRAME_TYPE_VENDOR: 675 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; 676 break; 677 678 default: 679 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", 680 ptr[0]); 681 return; 682 } 683 684 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 685 INFOFRAME_HEADER_VERSION(ptr[1]) | 686 INFOFRAME_HEADER_LEN(ptr[2]); 687 tegra_hdmi_writel(hdmi, value, offset); 688 offset++; 689 690 /* 691 * Each subpack contains 7 bytes, divided into: 692 * - subpack_low: bytes 0 - 3 693 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 694 */ 695 for (i = 3; i < size; i += 7) { 696 size_t rem = size - i, num = min_t(size_t, rem, 4); 697 698 value = tegra_hdmi_subpack(&ptr[i], num); 699 tegra_hdmi_writel(hdmi, value, offset++); 700 701 num = min_t(size_t, rem - num, 3); 702 703 value = tegra_hdmi_subpack(&ptr[i + 4], num); 704 tegra_hdmi_writel(hdmi, value, offset++); 705 } 706} 707 708static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, 709 struct drm_display_mode *mode) 710{ 711 struct hdmi_avi_infoframe frame; 712 u8 buffer[17]; 713 ssize_t err; 714 715 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 716 &hdmi->output.connector, mode); 717 if (err < 0) { 718 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); 719 return; 720 } 721 722 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 723 if (err < 0) { 724 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); 725 return; 726 } 727 728 tegra_hdmi_write_infopack(hdmi, buffer, err); 729} 730 731static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi) 732{ 733 u32 value; 734 735 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 736 value &= ~INFOFRAME_CTRL_ENABLE; 737 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 738} 739 740static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi) 741{ 742 u32 value; 743 744 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 745 value |= INFOFRAME_CTRL_ENABLE; 746 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 747} 748 749static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) 750{ 751 struct hdmi_audio_infoframe frame; 752 u8 buffer[14]; 753 ssize_t err; 754 755 err = hdmi_audio_infoframe_init(&frame); 756 if (err < 0) { 757 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n", 758 err); 759 return; 760 } 761 762 frame.channels = hdmi->format.channels; 763 764 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 765 if (err < 0) { 766 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", 767 err); 768 return; 769 } 770 771 /* 772 * The audio infoframe has only one set of subpack registers, so the 773 * infoframe needs to be truncated. One set of subpack registers can 774 * contain 7 bytes. Including the 3 byte header only the first 10 775 * bytes can be programmed. 776 */ 777 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err)); 778} 779 780static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi) 781{ 782 u32 value; 783 784 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 785 value &= ~INFOFRAME_CTRL_ENABLE; 786 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 787} 788 789static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi) 790{ 791 u32 value; 792 793 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 794 value |= INFOFRAME_CTRL_ENABLE; 795 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 796} 797 798static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) 799{ 800 struct hdmi_vendor_infoframe frame; 801 u8 buffer[10]; 802 ssize_t err; 803 804 hdmi_vendor_infoframe_init(&frame); 805 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING; 806 807 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 808 if (err < 0) { 809 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", 810 err); 811 return; 812 } 813 814 tegra_hdmi_write_infopack(hdmi, buffer, err); 815} 816 817static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi) 818{ 819 u32 value; 820 821 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 822 value &= ~GENERIC_CTRL_ENABLE; 823 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 824} 825 826static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi) 827{ 828 u32 value; 829 830 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 831 value |= GENERIC_CTRL_ENABLE; 832 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 833} 834 835static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, 836 const struct tmds_config *tmds) 837{ 838 u32 value; 839 840 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); 841 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); 842 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); 843 844 tegra_hdmi_writel(hdmi, tmds->drive_current, 845 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); 846 847 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset); 848 value |= hdmi->config->fuse_override_value; 849 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset); 850 851 if (hdmi->config->has_sor_io_peak_current) 852 tegra_hdmi_writel(hdmi, tmds->peak_current, 853 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); 854} 855 856static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi) 857{ 858 int err; 859 860 err = tegra_hdmi_setup_audio(hdmi); 861 if (err < 0) { 862 tegra_hdmi_disable_audio_infoframe(hdmi); 863 tegra_hdmi_disable_audio(hdmi); 864 } else { 865 tegra_hdmi_setup_audio_infoframe(hdmi); 866 tegra_hdmi_enable_audio_infoframe(hdmi); 867 tegra_hdmi_enable_audio(hdmi); 868 } 869 870 return err; 871} 872 873static bool tegra_output_is_hdmi(struct tegra_output *output) 874{ 875 return output->connector.display_info.is_hdmi; 876} 877 878static enum drm_connector_status 879tegra_hdmi_connector_detect(struct drm_connector *connector, bool force) 880{ 881 struct tegra_output *output = connector_to_output(connector); 882 struct tegra_hdmi *hdmi = to_hdmi(output); 883 enum drm_connector_status status; 884 885 status = tegra_output_connector_detect(connector, force); 886 if (status == connector_status_connected) 887 return status; 888 889 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 890 return status; 891} 892 893#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 894 895static const struct debugfs_reg32 tegra_hdmi_regs[] = { 896 DEBUGFS_REG32(HDMI_CTXSW), 897 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 898 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 899 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 900 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 901 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 902 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 903 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 904 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), 905 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), 906 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), 907 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), 908 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), 909 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), 910 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), 911 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), 912 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), 913 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), 914 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), 915 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), 916 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), 917 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), 918 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), 919 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), 920 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), 921 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), 922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), 923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), 924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), 925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), 926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), 927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), 928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), 929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), 930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), 931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), 932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), 933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), 934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), 935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), 936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), 937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), 938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), 939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), 940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), 941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), 942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), 943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), 944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), 945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), 946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), 947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), 948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), 949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), 950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), 951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), 952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), 953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), 954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), 955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), 956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), 957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), 958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), 959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), 960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), 961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), 962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), 963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), 964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), 965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), 966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), 967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), 968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), 969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), 970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), 971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), 972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), 973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), 974 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), 975 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), 976 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), 977 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), 978 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), 979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), 980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), 981 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), 982 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), 983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), 984 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), 985 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), 986 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), 987 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), 988 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), 989 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), 990 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), 991 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), 992 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), 993 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), 994 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), 995 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), 996 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), 997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), 998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), 999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), 1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), 1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), 1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), 1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), 1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), 1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), 1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), 1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), 1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), 1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), 1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), 1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), 1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), 1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), 1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), 1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), 1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), 1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), 1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), 1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), 1020 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), 1021 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), 1022 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), 1023 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), 1024 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), 1025 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), 1026 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), 1027 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), 1028 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), 1029 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), 1030 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), 1031 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), 1032 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), 1033 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), 1034 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), 1035 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), 1036 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), 1037 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), 1038 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), 1039 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), 1040 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), 1041 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), 1042 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), 1043 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), 1044 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), 1045 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), 1046 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), 1047 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), 1048 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), 1049 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), 1050 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), 1051 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), 1052 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), 1053 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), 1054 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), 1055 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), 1056 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), 1057 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), 1058 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), 1059 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), 1060}; 1061 1062static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 1063{ 1064 struct drm_info_node *node = s->private; 1065 struct tegra_hdmi *hdmi = node->info_ent->data; 1066 struct drm_crtc *crtc = hdmi->output.encoder.crtc; 1067 struct drm_device *drm = node->minor->dev; 1068 unsigned int i; 1069 int err = 0; 1070 1071 drm_modeset_lock_all(drm); 1072 1073 if (!crtc || !crtc->state->active) { 1074 err = -EBUSY; 1075 goto unlock; 1076 } 1077 1078 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { 1079 unsigned int offset = tegra_hdmi_regs[i].offset; 1080 1081 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, 1082 offset, tegra_hdmi_readl(hdmi, offset)); 1083 } 1084 1085unlock: 1086 drm_modeset_unlock_all(drm); 1087 return err; 1088} 1089 1090static struct drm_info_list debugfs_files[] = { 1091 { "regs", tegra_hdmi_show_regs, 0, NULL }, 1092}; 1093 1094static int tegra_hdmi_late_register(struct drm_connector *connector) 1095{ 1096 struct tegra_output *output = connector_to_output(connector); 1097 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1098 struct drm_minor *minor = connector->dev->primary; 1099 struct dentry *root = connector->debugfs_entry; 1100 struct tegra_hdmi *hdmi = to_hdmi(output); 1101 1102 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1103 GFP_KERNEL); 1104 if (!hdmi->debugfs_files) 1105 return -ENOMEM; 1106 1107 for (i = 0; i < count; i++) 1108 hdmi->debugfs_files[i].data = hdmi; 1109 1110 drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); 1111 1112 return 0; 1113} 1114 1115static void tegra_hdmi_early_unregister(struct drm_connector *connector) 1116{ 1117 struct tegra_output *output = connector_to_output(connector); 1118 struct drm_minor *minor = connector->dev->primary; 1119 unsigned int count = ARRAY_SIZE(debugfs_files); 1120 struct tegra_hdmi *hdmi = to_hdmi(output); 1121 1122 drm_debugfs_remove_files(hdmi->debugfs_files, count, 1123 connector->debugfs_entry, minor); 1124 kfree(hdmi->debugfs_files); 1125 hdmi->debugfs_files = NULL; 1126} 1127 1128static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { 1129 .reset = drm_atomic_helper_connector_reset, 1130 .detect = tegra_hdmi_connector_detect, 1131 .fill_modes = drm_helper_probe_single_connector_modes, 1132 .destroy = tegra_output_connector_destroy, 1133 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1134 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1135 .late_register = tegra_hdmi_late_register, 1136 .early_unregister = tegra_hdmi_early_unregister, 1137}; 1138 1139static enum drm_mode_status 1140tegra_hdmi_connector_mode_valid(struct drm_connector *connector, 1141 const struct drm_display_mode *mode) 1142{ 1143 struct tegra_output *output = connector_to_output(connector); 1144 struct tegra_hdmi *hdmi = to_hdmi(output); 1145 unsigned long pclk = mode->clock * 1000; 1146 enum drm_mode_status status = MODE_OK; 1147 struct clk *parent; 1148 long err; 1149 1150 parent = clk_get_parent(hdmi->clk_parent); 1151 1152 err = clk_round_rate(parent, pclk * 4); 1153 if (err <= 0) 1154 status = MODE_NOCLOCK; 1155 1156 return status; 1157} 1158 1159static const struct drm_connector_helper_funcs 1160tegra_hdmi_connector_helper_funcs = { 1161 .get_modes = tegra_output_connector_get_modes, 1162 .mode_valid = tegra_hdmi_connector_mode_valid, 1163}; 1164 1165static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder) 1166{ 1167 struct tegra_output *output = encoder_to_output(encoder); 1168 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1169 struct tegra_hdmi *hdmi = to_hdmi(output); 1170 u32 value; 1171 int err; 1172 1173 tegra_hdmi_audio_lock(hdmi); 1174 1175 /* 1176 * The following accesses registers of the display controller, so make 1177 * sure it's only executed when the output is attached to one. 1178 */ 1179 if (dc) { 1180 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1181 value &= ~HDMI_ENABLE; 1182 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1183 1184 tegra_dc_commit(dc); 1185 } 1186 1187 if (!hdmi->dvi) { 1188 if (hdmi->stereo) 1189 tegra_hdmi_disable_stereo_infoframe(hdmi); 1190 1191 tegra_hdmi_disable_audio_infoframe(hdmi); 1192 tegra_hdmi_disable_avi_infoframe(hdmi); 1193 tegra_hdmi_disable_audio(hdmi); 1194 } 1195 1196 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE); 1197 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK); 1198 1199 hdmi->pixel_clock = 0; 1200 1201 tegra_hdmi_audio_unlock(hdmi); 1202 1203 err = host1x_client_suspend(&hdmi->client); 1204 if (err < 0) 1205 dev_err(hdmi->dev, "failed to suspend: %d\n", err); 1206} 1207 1208static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder) 1209{ 1210 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1211 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; 1212 struct tegra_output *output = encoder_to_output(encoder); 1213 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1214 struct tegra_hdmi *hdmi = to_hdmi(output); 1215 unsigned int pulse_start, div82; 1216 int retries = 1000; 1217 u32 value; 1218 int err; 1219 1220 err = host1x_client_resume(&hdmi->client); 1221 if (err < 0) { 1222 dev_err(hdmi->dev, "failed to resume: %d\n", err); 1223 return; 1224 } 1225 1226 tegra_hdmi_audio_lock(hdmi); 1227 1228 /* 1229 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1230 * is used for interoperability between the HDA codec driver and the 1231 * HDMI driver. 1232 */ 1233 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE); 1234 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK); 1235 1236 hdmi->pixel_clock = mode->clock * 1000; 1237 h_sync_width = mode->hsync_end - mode->hsync_start; 1238 h_back_porch = mode->htotal - mode->hsync_end; 1239 h_front_porch = mode->hsync_start - mode->hdisplay; 1240 1241 err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock); 1242 if (err < 0) { 1243 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", 1244 err); 1245 } 1246 1247 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); 1248 1249 /* power up sequence */ 1250 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1251 value &= ~SOR_PLL_PDBG; 1252 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1253 1254 usleep_range(10, 20); 1255 1256 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1257 value &= ~SOR_PLL_PWR; 1258 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1259 1260 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 1261 DC_DISP_DISP_TIMING_OPTIONS); 1262 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, 1263 DC_DISP_DISP_COLOR_CONTROL); 1264 1265 /* video_preamble uses h_pulse2 */ 1266 pulse_start = 1 + h_sync_width + h_back_porch - 10; 1267 1268 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); 1269 1270 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | 1271 PULSE_LAST_END_A; 1272 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 1273 1274 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); 1275 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 1276 1277 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | 1278 VSYNC_WINDOW_ENABLE; 1279 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); 1280 1281 if (dc->pipe) 1282 value = HDMI_SRC_DISPLAYB; 1283 else 1284 value = HDMI_SRC_DISPLAYA; 1285 1286 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || 1287 (mode->vdisplay == 576))) 1288 tegra_hdmi_writel(hdmi, 1289 value | ARM_VIDEO_RANGE_FULL, 1290 HDMI_NV_PDISP_INPUT_CONTROL); 1291 else 1292 tegra_hdmi_writel(hdmi, 1293 value | ARM_VIDEO_RANGE_LIMITED, 1294 HDMI_NV_PDISP_INPUT_CONTROL); 1295 1296 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; 1297 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); 1298 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); 1299 1300 hdmi->dvi = !tegra_output_is_hdmi(output); 1301 if (!hdmi->dvi) { 1302 /* 1303 * Make sure that the audio format has been configured before 1304 * enabling audio, otherwise we may try to divide by zero. 1305 */ 1306 if (hdmi->format.sample_rate > 0) { 1307 err = tegra_hdmi_setup_audio(hdmi); 1308 if (err < 0) 1309 hdmi->dvi = true; 1310 } 1311 } 1312 1313 if (hdmi->config->has_hda) 1314 tegra_hdmi_write_eld(hdmi); 1315 1316 rekey = HDMI_REKEY_DEFAULT; 1317 value = HDMI_CTRL_REKEY(rekey); 1318 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + 1319 h_front_porch - rekey - 18) / 32); 1320 1321 if (!hdmi->dvi) 1322 value |= HDMI_CTRL_ENABLE; 1323 1324 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); 1325 1326 if (!hdmi->dvi) { 1327 tegra_hdmi_setup_avi_infoframe(hdmi, mode); 1328 tegra_hdmi_setup_audio_infoframe(hdmi); 1329 1330 if (hdmi->stereo) 1331 tegra_hdmi_setup_stereo_infoframe(hdmi); 1332 } 1333 1334 /* TMDS CONFIG */ 1335 for (i = 0; i < hdmi->config->num_tmds; i++) { 1336 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) { 1337 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); 1338 break; 1339 } 1340 } 1341 1342 tegra_hdmi_writel(hdmi, 1343 SOR_SEQ_PU_PC(0) | 1344 SOR_SEQ_PU_PC_ALT(0) | 1345 SOR_SEQ_PD_PC(8) | 1346 SOR_SEQ_PD_PC_ALT(8), 1347 HDMI_NV_PDISP_SOR_SEQ_CTL); 1348 1349 value = SOR_SEQ_INST_WAIT_TIME(1) | 1350 SOR_SEQ_INST_WAIT_UNITS_VSYNC | 1351 SOR_SEQ_INST_HALT | 1352 SOR_SEQ_INST_PIN_A_LOW | 1353 SOR_SEQ_INST_PIN_B_LOW | 1354 SOR_SEQ_INST_DRIVE_PWM_OUT_LO; 1355 1356 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 1357 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 1358 1359 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM); 1360 value &= ~SOR_CSTM_ROTCLK(~0); 1361 value |= SOR_CSTM_ROTCLK(2); 1362 value |= SOR_CSTM_PLLDIV; 1363 value &= ~SOR_CSTM_LVDS_ENABLE; 1364 value &= ~SOR_CSTM_MODE_MASK; 1365 value |= SOR_CSTM_MODE_TMDS; 1366 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 1367 1368 /* start SOR */ 1369 tegra_hdmi_writel(hdmi, 1370 SOR_PWR_NORMAL_STATE_PU | 1371 SOR_PWR_NORMAL_START_NORMAL | 1372 SOR_PWR_SAFE_STATE_PD | 1373 SOR_PWR_SETTING_NEW_TRIGGER, 1374 HDMI_NV_PDISP_SOR_PWR); 1375 tegra_hdmi_writel(hdmi, 1376 SOR_PWR_NORMAL_STATE_PU | 1377 SOR_PWR_NORMAL_START_NORMAL | 1378 SOR_PWR_SAFE_STATE_PD | 1379 SOR_PWR_SETTING_NEW_DONE, 1380 HDMI_NV_PDISP_SOR_PWR); 1381 1382 do { 1383 BUG_ON(--retries < 0); 1384 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); 1385 } while (value & SOR_PWR_SETTING_NEW_PENDING); 1386 1387 value = SOR_STATE_ASY_CRCMODE_COMPLETE | 1388 SOR_STATE_ASY_OWNER_HEAD0 | 1389 SOR_STATE_ASY_SUBOWNER_BOTH | 1390 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | 1391 SOR_STATE_ASY_DEPOL_POS; 1392 1393 /* setup sync polarities */ 1394 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1395 value |= SOR_STATE_ASY_HSYNCPOL_POS; 1396 1397 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1398 value |= SOR_STATE_ASY_HSYNCPOL_NEG; 1399 1400 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1401 value |= SOR_STATE_ASY_VSYNCPOL_POS; 1402 1403 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1404 value |= SOR_STATE_ASY_VSYNCPOL_NEG; 1405 1406 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); 1407 1408 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; 1409 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); 1410 1411 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1412 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); 1413 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, 1414 HDMI_NV_PDISP_SOR_STATE1); 1415 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1416 1417 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1418 value |= HDMI_ENABLE; 1419 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1420 1421 tegra_dc_commit(dc); 1422 1423 if (!hdmi->dvi) { 1424 tegra_hdmi_enable_avi_infoframe(hdmi); 1425 tegra_hdmi_enable_audio_infoframe(hdmi); 1426 tegra_hdmi_enable_audio(hdmi); 1427 1428 if (hdmi->stereo) 1429 tegra_hdmi_enable_stereo_infoframe(hdmi); 1430 } 1431 1432 /* TODO: add HDCP support */ 1433 1434 tegra_hdmi_audio_unlock(hdmi); 1435} 1436 1437static int 1438tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1439 struct drm_crtc_state *crtc_state, 1440 struct drm_connector_state *conn_state) 1441{ 1442 struct tegra_output *output = encoder_to_output(encoder); 1443 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1444 unsigned long pclk = crtc_state->mode.clock * 1000; 1445 struct tegra_hdmi *hdmi = to_hdmi(output); 1446 int err; 1447 1448 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, 1449 pclk, 0); 1450 if (err < 0) { 1451 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1452 return err; 1453 } 1454 1455 return err; 1456} 1457 1458static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { 1459 .disable = tegra_hdmi_encoder_disable, 1460 .enable = tegra_hdmi_encoder_enable, 1461 .atomic_check = tegra_hdmi_encoder_atomic_check, 1462}; 1463 1464static int tegra_hdmi_hw_params(struct device *dev, void *data, 1465 struct hdmi_codec_daifmt *fmt, 1466 struct hdmi_codec_params *hparms) 1467{ 1468 struct tegra_hdmi *hdmi = data; 1469 int ret = 0; 1470 1471 tegra_hdmi_audio_lock(hdmi); 1472 1473 hdmi->format.sample_rate = hparms->sample_rate; 1474 hdmi->format.channels = hparms->channels; 1475 1476 if (hdmi->pixel_clock && !hdmi->dvi) 1477 ret = tegra_hdmi_reconfigure_audio(hdmi); 1478 1479 tegra_hdmi_audio_unlock(hdmi); 1480 1481 return ret; 1482} 1483 1484static int tegra_hdmi_audio_startup(struct device *dev, void *data) 1485{ 1486 struct tegra_hdmi *hdmi = data; 1487 int ret; 1488 1489 ret = host1x_client_resume(&hdmi->client); 1490 if (ret < 0) 1491 dev_err(hdmi->dev, "failed to resume: %d\n", ret); 1492 1493 return ret; 1494} 1495 1496static void tegra_hdmi_audio_shutdown(struct device *dev, void *data) 1497{ 1498 struct tegra_hdmi *hdmi = data; 1499 int ret; 1500 1501 tegra_hdmi_audio_lock(hdmi); 1502 1503 hdmi->format.sample_rate = 0; 1504 hdmi->format.channels = 0; 1505 1506 tegra_hdmi_audio_unlock(hdmi); 1507 1508 ret = host1x_client_suspend(&hdmi->client); 1509 if (ret < 0) 1510 dev_err(hdmi->dev, "failed to suspend: %d\n", ret); 1511} 1512 1513static const struct hdmi_codec_ops tegra_hdmi_codec_ops = { 1514 .hw_params = tegra_hdmi_hw_params, 1515 .audio_startup = tegra_hdmi_audio_startup, 1516 .audio_shutdown = tegra_hdmi_audio_shutdown, 1517}; 1518 1519static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi) 1520{ 1521 struct hdmi_codec_pdata codec_data = {}; 1522 1523 if (hdmi->config->has_hda) 1524 return 0; 1525 1526 codec_data.ops = &tegra_hdmi_codec_ops; 1527 codec_data.data = hdmi; 1528 codec_data.spdif = 1; 1529 1530 hdmi->audio_pdev = platform_device_register_data(hdmi->dev, 1531 HDMI_CODEC_DRV_NAME, 1532 PLATFORM_DEVID_AUTO, 1533 &codec_data, 1534 sizeof(codec_data)); 1535 if (IS_ERR(hdmi->audio_pdev)) 1536 return PTR_ERR(hdmi->audio_pdev); 1537 1538 hdmi->format.channels = 2; 1539 1540 return 0; 1541} 1542 1543static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi) 1544{ 1545 if (hdmi->audio_pdev) 1546 platform_device_unregister(hdmi->audio_pdev); 1547} 1548 1549static int tegra_hdmi_init(struct host1x_client *client) 1550{ 1551 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1552 struct drm_device *drm = dev_get_drvdata(client->host); 1553 struct drm_connector *connector; 1554 int err; 1555 1556 hdmi->output.dev = client->dev; 1557 1558 drm_simple_encoder_init(drm, &hdmi->output.encoder, 1559 DRM_MODE_ENCODER_TMDS); 1560 drm_encoder_helper_add(&hdmi->output.encoder, 1561 &tegra_hdmi_encoder_helper_funcs); 1562 1563 if (hdmi->output.bridge) { 1564 err = drm_bridge_attach(&hdmi->output.encoder, hdmi->output.bridge, 1565 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1566 if (err) { 1567 dev_err(client->dev, "failed to attach bridge: %d\n", 1568 err); 1569 return err; 1570 } 1571 1572 connector = drm_bridge_connector_init(drm, &hdmi->output.encoder); 1573 if (IS_ERR(connector)) { 1574 dev_err(client->dev, 1575 "failed to initialize bridge connector: %pe\n", 1576 connector); 1577 return PTR_ERR(connector); 1578 } 1579 1580 drm_connector_attach_encoder(connector, &hdmi->output.encoder); 1581 } else { 1582 drm_connector_init_with_ddc(drm, &hdmi->output.connector, 1583 &tegra_hdmi_connector_funcs, 1584 DRM_MODE_CONNECTOR_HDMIA, 1585 hdmi->output.ddc); 1586 drm_connector_helper_add(&hdmi->output.connector, 1587 &tegra_hdmi_connector_helper_funcs); 1588 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1589 1590 drm_connector_attach_encoder(&hdmi->output.connector, 1591 &hdmi->output.encoder); 1592 drm_connector_register(&hdmi->output.connector); 1593 } 1594 1595 err = tegra_output_init(drm, &hdmi->output); 1596 if (err < 0) { 1597 dev_err(client->dev, "failed to initialize output: %d\n", err); 1598 return err; 1599 } 1600 1601 hdmi->output.encoder.possible_crtcs = 0x3; 1602 1603 err = regulator_enable(hdmi->hdmi); 1604 if (err < 0) { 1605 dev_err(client->dev, "failed to enable HDMI regulator: %d\n", 1606 err); 1607 goto output_exit; 1608 } 1609 1610 err = regulator_enable(hdmi->pll); 1611 if (err < 0) { 1612 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); 1613 goto disable_hdmi; 1614 } 1615 1616 err = regulator_enable(hdmi->vdd); 1617 if (err < 0) { 1618 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); 1619 goto disable_pll; 1620 } 1621 1622 err = tegra_hdmi_codec_register(hdmi); 1623 if (err < 0) { 1624 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err); 1625 goto disable_vdd; 1626 } 1627 1628 return 0; 1629 1630disable_vdd: 1631 regulator_disable(hdmi->vdd); 1632disable_pll: 1633 regulator_disable(hdmi->pll); 1634disable_hdmi: 1635 regulator_disable(hdmi->hdmi); 1636output_exit: 1637 tegra_output_exit(&hdmi->output); 1638 1639 return err; 1640} 1641 1642static int tegra_hdmi_exit(struct host1x_client *client) 1643{ 1644 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1645 1646 tegra_hdmi_codec_unregister(hdmi); 1647 1648 tegra_output_exit(&hdmi->output); 1649 1650 regulator_disable(hdmi->vdd); 1651 regulator_disable(hdmi->pll); 1652 regulator_disable(hdmi->hdmi); 1653 1654 return 0; 1655} 1656 1657static int tegra_hdmi_runtime_suspend(struct host1x_client *client) 1658{ 1659 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1660 struct device *dev = client->dev; 1661 int err; 1662 1663 err = reset_control_assert(hdmi->rst); 1664 if (err < 0) { 1665 dev_err(dev, "failed to assert reset: %d\n", err); 1666 return err; 1667 } 1668 1669 usleep_range(1000, 2000); 1670 1671 clk_disable_unprepare(hdmi->clk); 1672 pm_runtime_put_sync(dev); 1673 1674 return 0; 1675} 1676 1677static int tegra_hdmi_runtime_resume(struct host1x_client *client) 1678{ 1679 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1680 struct device *dev = client->dev; 1681 int err; 1682 1683 err = pm_runtime_resume_and_get(dev); 1684 if (err < 0) { 1685 dev_err(dev, "failed to get runtime PM: %d\n", err); 1686 return err; 1687 } 1688 1689 err = clk_prepare_enable(hdmi->clk); 1690 if (err < 0) { 1691 dev_err(dev, "failed to enable clock: %d\n", err); 1692 goto put_rpm; 1693 } 1694 1695 usleep_range(1000, 2000); 1696 1697 err = reset_control_deassert(hdmi->rst); 1698 if (err < 0) { 1699 dev_err(dev, "failed to deassert reset: %d\n", err); 1700 goto disable_clk; 1701 } 1702 1703 return 0; 1704 1705disable_clk: 1706 clk_disable_unprepare(hdmi->clk); 1707put_rpm: 1708 pm_runtime_put_sync(dev); 1709 return err; 1710} 1711 1712static const struct host1x_client_ops hdmi_client_ops = { 1713 .init = tegra_hdmi_init, 1714 .exit = tegra_hdmi_exit, 1715 .suspend = tegra_hdmi_runtime_suspend, 1716 .resume = tegra_hdmi_runtime_resume, 1717}; 1718 1719static const struct tegra_hdmi_config tegra20_hdmi_config = { 1720 .tmds = tegra20_tmds_config, 1721 .num_tmds = ARRAY_SIZE(tegra20_tmds_config), 1722 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1723 .fuse_override_value = 1 << 31, 1724 .has_sor_io_peak_current = false, 1725 .has_hda = false, 1726 .has_hbr = false, 1727}; 1728 1729static const struct tegra_hdmi_config tegra30_hdmi_config = { 1730 .tmds = tegra30_tmds_config, 1731 .num_tmds = ARRAY_SIZE(tegra30_tmds_config), 1732 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1733 .fuse_override_value = 1 << 31, 1734 .has_sor_io_peak_current = false, 1735 .has_hda = true, 1736 .has_hbr = false, 1737}; 1738 1739static const struct tegra_hdmi_config tegra114_hdmi_config = { 1740 .tmds = tegra114_tmds_config, 1741 .num_tmds = ARRAY_SIZE(tegra114_tmds_config), 1742 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1743 .fuse_override_value = 1 << 31, 1744 .has_sor_io_peak_current = true, 1745 .has_hda = true, 1746 .has_hbr = true, 1747}; 1748 1749static const struct tegra_hdmi_config tegra124_hdmi_config = { 1750 .tmds = tegra124_tmds_config, 1751 .num_tmds = ARRAY_SIZE(tegra124_tmds_config), 1752 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1753 .fuse_override_value = 1 << 31, 1754 .has_sor_io_peak_current = true, 1755 .has_hda = true, 1756 .has_hbr = true, 1757}; 1758 1759static const struct of_device_id tegra_hdmi_of_match[] = { 1760 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, 1761 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, 1762 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, 1763 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, 1764 { }, 1765}; 1766MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); 1767 1768static irqreturn_t tegra_hdmi_irq(int irq, void *data) 1769{ 1770 struct tegra_hdmi *hdmi = data; 1771 u32 value; 1772 1773 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS); 1774 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS); 1775 1776 if (value & INT_CODEC_SCRATCH0) { 1777 unsigned int format; 1778 u32 value; 1779 1780 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0); 1781 1782 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 1783 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 1784 1785 tegra_hda_parse_format(format, &hdmi->format); 1786 tegra_hdmi_reconfigure_audio(hdmi); 1787 } else { 1788 tegra_hdmi_disable_audio_infoframe(hdmi); 1789 tegra_hdmi_disable_audio(hdmi); 1790 } 1791 } 1792 1793 return IRQ_HANDLED; 1794} 1795 1796static int tegra_hdmi_probe(struct platform_device *pdev) 1797{ 1798 struct tegra_hdmi *hdmi; 1799 int err; 1800 1801 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 1802 if (!hdmi) 1803 return -ENOMEM; 1804 1805 hdmi->config = of_device_get_match_data(&pdev->dev); 1806 hdmi->dev = &pdev->dev; 1807 1808 hdmi->audio_source = AUTO; 1809 hdmi->stereo = false; 1810 hdmi->dvi = false; 1811 1812 mutex_init(&hdmi->audio_lock); 1813 1814 hdmi->clk = devm_clk_get(&pdev->dev, NULL); 1815 if (IS_ERR(hdmi->clk)) { 1816 dev_err(&pdev->dev, "failed to get clock\n"); 1817 return PTR_ERR(hdmi->clk); 1818 } 1819 1820 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi"); 1821 if (IS_ERR(hdmi->rst)) { 1822 dev_err(&pdev->dev, "failed to get reset\n"); 1823 return PTR_ERR(hdmi->rst); 1824 } 1825 1826 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1827 if (IS_ERR(hdmi->clk_parent)) 1828 return PTR_ERR(hdmi->clk_parent); 1829 1830 err = clk_set_parent(hdmi->clk, hdmi->clk_parent); 1831 if (err < 0) { 1832 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); 1833 return err; 1834 } 1835 1836 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); 1837 err = PTR_ERR_OR_ZERO(hdmi->hdmi); 1838 if (err) 1839 return dev_err_probe(&pdev->dev, err, 1840 "failed to get HDMI regulator\n"); 1841 1842 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1843 err = PTR_ERR_OR_ZERO(hdmi->pll); 1844 if (err) 1845 return dev_err_probe(&pdev->dev, err, 1846 "failed to get PLL regulator\n"); 1847 1848 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1849 err = PTR_ERR_OR_ZERO(hdmi->vdd); 1850 if (err) 1851 return dev_err_probe(&pdev->dev, err, 1852 "failed to get VDD regulator\n"); 1853 1854 hdmi->output.dev = &pdev->dev; 1855 1856 err = tegra_output_probe(&hdmi->output); 1857 if (err < 0) 1858 return err; 1859 1860 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 1861 if (IS_ERR(hdmi->regs)) { 1862 err = PTR_ERR(hdmi->regs); 1863 goto remove; 1864 } 1865 1866 err = platform_get_irq(pdev, 0); 1867 if (err < 0) 1868 goto remove; 1869 1870 hdmi->irq = err; 1871 1872 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0, 1873 dev_name(hdmi->dev), hdmi); 1874 if (err < 0) { 1875 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", 1876 hdmi->irq, err); 1877 goto remove; 1878 } 1879 1880 platform_set_drvdata(pdev, hdmi); 1881 1882 err = devm_pm_runtime_enable(&pdev->dev); 1883 if (err) 1884 goto remove; 1885 1886 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1887 if (err) 1888 goto remove; 1889 1890 INIT_LIST_HEAD(&hdmi->client.list); 1891 hdmi->client.ops = &hdmi_client_ops; 1892 hdmi->client.dev = &pdev->dev; 1893 1894 err = host1x_client_register(&hdmi->client); 1895 if (err < 0) { 1896 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1897 err); 1898 goto remove; 1899 } 1900 1901 return 0; 1902 1903remove: 1904 tegra_output_remove(&hdmi->output); 1905 return err; 1906} 1907 1908static void tegra_hdmi_remove(struct platform_device *pdev) 1909{ 1910 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); 1911 1912 host1x_client_unregister(&hdmi->client); 1913 1914 tegra_output_remove(&hdmi->output); 1915} 1916 1917struct platform_driver tegra_hdmi_driver = { 1918 .driver = { 1919 .name = "tegra-hdmi", 1920 .of_match_table = tegra_hdmi_of_match, 1921 }, 1922 .probe = tegra_hdmi_probe, 1923 .remove = tegra_hdmi_remove, 1924};
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