dpaux.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2013 NVIDIA Corporation
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/delay.h>
  8#include <linux/interrupt.h>
  9#include <linux/io.h>
 10#include <linux/module.h>
 11#include <linux/of.h>
 12#include <linux/pinctrl/pinconf-generic.h>
 13#include <linux/pinctrl/pinctrl.h>
 14#include <linux/pinctrl/pinmux.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_runtime.h>
 17#include <linux/regulator/consumer.h>
 18#include <linux/reset.h>
 19#include <linux/workqueue.h>
 20
 21#include <drm/display/drm_dp_helper.h>
 22#include <drm/display/drm_dp_aux_bus.h>
 23#include <drm/drm_panel.h>
 24
 25#include "dp.h"
 26#include "dpaux.h"
 27#include "drm.h"
 28#include "trace.h"
 29
 30static DEFINE_MUTEX(dpaux_lock);
 31static LIST_HEAD(dpaux_list);
 32
 33struct tegra_dpaux_soc {
 34	unsigned int cmh;
 35	unsigned int drvz;
 36	unsigned int drvi;
 37};
 38
 39struct tegra_dpaux {
 40	struct drm_dp_aux aux;
 41	struct device *dev;
 42
 43	const struct tegra_dpaux_soc *soc;
 44
 45	void __iomem *regs;
 46	int irq;
 47
 48	struct tegra_output *output;
 49
 50	struct reset_control *rst;
 51	struct clk *clk_parent;
 52	struct clk *clk;
 53
 54	struct regulator *vdd;
 55
 56	struct completion complete;
 57	struct work_struct work;
 58	struct list_head list;
 59
 60#ifdef CONFIG_GENERIC_PINCONF
 61	struct pinctrl_dev *pinctrl;
 62	struct pinctrl_desc desc;
 63#endif
 64};
 65
 66static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
 67{
 68	return container_of(aux, struct tegra_dpaux, aux);
 69}
 70
 71static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
 72{
 73	return container_of(work, struct tegra_dpaux, work);
 74}
 75
 76static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
 77				    unsigned int offset)
 78{
 79	u32 value = readl(dpaux->regs + (offset << 2));
 80
 81	trace_dpaux_readl(dpaux->dev, offset, value);
 82
 83	return value;
 84}
 85
 86static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
 87				      u32 value, unsigned int offset)
 88{
 89	trace_dpaux_writel(dpaux->dev, offset, value);
 90	writel(value, dpaux->regs + (offset << 2));
 91}
 92
 93static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
 94				   size_t size)
 95{
 96	size_t i, j;
 97
 98	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
 99		size_t num = min_t(size_t, size - i * 4, 4);
100		u32 value = 0;
101
102		for (j = 0; j < num; j++)
103			value |= buffer[i * 4 + j] << (j * 8);
104
105		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
106	}
107}
108
109static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
110				  size_t size)
111{
112	size_t i, j;
113
114	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
115		size_t num = min_t(size_t, size - i * 4, 4);
116		u32 value;
117
118		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
119
120		for (j = 0; j < num; j++)
121			buffer[i * 4 + j] = value >> (j * 8);
122	}
123}
124
125static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
126				    struct drm_dp_aux_msg *msg)
127{
128	unsigned long timeout = msecs_to_jiffies(250);
129	struct tegra_dpaux *dpaux = to_dpaux(aux);
130	unsigned long status;
131	ssize_t ret = 0;
132	u8 reply = 0;
133	u32 value;
134
135	/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
136	if (msg->size > 16)
137		return -EINVAL;
138
139	/*
140	 * Allow zero-sized messages only for I2C, in which case they specify
141	 * address-only transactions.
142	 */
143	if (msg->size < 1) {
144		switch (msg->request & ~DP_AUX_I2C_MOT) {
145		case DP_AUX_I2C_WRITE_STATUS_UPDATE:
146		case DP_AUX_I2C_WRITE:
147		case DP_AUX_I2C_READ:
148			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
149			break;
150
151		default:
152			return -EINVAL;
153		}
154	} else {
155		/* For non-zero-sized messages, set the CMDLEN field. */
156		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
157	}
158
159	switch (msg->request & ~DP_AUX_I2C_MOT) {
160	case DP_AUX_I2C_WRITE:
161		if (msg->request & DP_AUX_I2C_MOT)
162			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
163		else
164			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
165
166		break;
167
168	case DP_AUX_I2C_READ:
169		if (msg->request & DP_AUX_I2C_MOT)
170			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
171		else
172			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
173
174		break;
175
176	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
177		if (msg->request & DP_AUX_I2C_MOT)
178			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
179		else
180			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
181
182		break;
183
184	case DP_AUX_NATIVE_WRITE:
185		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
186		break;
187
188	case DP_AUX_NATIVE_READ:
189		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
190		break;
191
192	default:
193		return -EINVAL;
194	}
195
196	tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
197	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
198
199	if ((msg->request & DP_AUX_I2C_READ) == 0) {
200		tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
201		ret = msg->size;
202	}
203
204	/* start transaction */
205	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
206	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
207	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
208
209	status = wait_for_completion_timeout(&dpaux->complete, timeout);
210	if (!status)
211		return -ETIMEDOUT;
212
213	/* read status and clear errors */
214	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
215	tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
216
217	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
218		return -ETIMEDOUT;
219
220	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
221	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
222	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
223		return -EIO;
224
225	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
226	case 0x00:
227		reply = DP_AUX_NATIVE_REPLY_ACK;
228		break;
229
230	case 0x01:
231		reply = DP_AUX_NATIVE_REPLY_NACK;
232		break;
233
234	case 0x02:
235		reply = DP_AUX_NATIVE_REPLY_DEFER;
236		break;
237
238	case 0x04:
239		reply = DP_AUX_I2C_REPLY_NACK;
240		break;
241
242	case 0x08:
243		reply = DP_AUX_I2C_REPLY_DEFER;
244		break;
245	}
246
247	if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
248		if (msg->request & DP_AUX_I2C_READ) {
249			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
250
251			/*
252			 * There might be a smarter way to do this, but since
253			 * the DP helpers will already retry transactions for
254			 * an -EBUSY return value, simply reuse that instead.
255			 */
256			if (count != msg->size) {
257				ret = -EBUSY;
258				goto out;
259			}
260
261			tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
262			ret = count;
263		}
264	}
265
266	msg->reply = reply;
267
268out:
269	return ret;
270}
271
272static void tegra_dpaux_hotplug(struct work_struct *work)
273{
274	struct tegra_dpaux *dpaux = work_to_dpaux(work);
275
276	if (dpaux->output)
277		drm_helper_hpd_irq_event(dpaux->output->connector.dev);
278}
279
280static irqreturn_t tegra_dpaux_irq(int irq, void *data)
281{
282	struct tegra_dpaux *dpaux = data;
283	u32 value;
284
285	/* clear interrupts */
286	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
287	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
288
289	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
290		schedule_work(&dpaux->work);
291
292	if (value & DPAUX_INTR_IRQ_EVENT) {
293		/* TODO: handle this */
294	}
295
296	if (value & DPAUX_INTR_AUX_DONE)
297		complete(&dpaux->complete);
298
299	return IRQ_HANDLED;
300}
301
302enum tegra_dpaux_functions {
303	DPAUX_PADCTL_FUNC_AUX,
304	DPAUX_PADCTL_FUNC_I2C,
305	DPAUX_PADCTL_FUNC_OFF,
306};
307
308static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
309{
310	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
311
312	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
313
314	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
315}
316
317static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
318{
319	u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
320
321	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
322
323	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
324}
325
326static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
327{
328	u32 value;
329
330	switch (function) {
331	case DPAUX_PADCTL_FUNC_AUX:
332		value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
333			DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
334			DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
335			DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
336			DPAUX_HYBRID_PADCTL_MODE_AUX;
337		break;
338
339	case DPAUX_PADCTL_FUNC_I2C:
340		value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
341			DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
342			DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
343			DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
344			DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
345			DPAUX_HYBRID_PADCTL_MODE_I2C;
346		break;
347
348	case DPAUX_PADCTL_FUNC_OFF:
349		tegra_dpaux_pad_power_down(dpaux);
350		return 0;
351
352	default:
353		return -ENOTSUPP;
354	}
355
356	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
357	tegra_dpaux_pad_power_up(dpaux);
358
359	return 0;
360}
361
362#ifdef CONFIG_GENERIC_PINCONF
363static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
364	PINCTRL_PIN(0, "DP_AUX_CHx_P"),
365	PINCTRL_PIN(1, "DP_AUX_CHx_N"),
366};
367
368static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
369
370static const char * const tegra_dpaux_groups[] = {
371	"dpaux-io",
372};
373
374static const char * const tegra_dpaux_functions[] = {
375	"aux",
376	"i2c",
377	"off",
378};
379
380static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
381{
382	return ARRAY_SIZE(tegra_dpaux_groups);
383}
384
385static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
386					      unsigned int group)
387{
388	return tegra_dpaux_groups[group];
389}
390
391static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
392				      unsigned group, const unsigned **pins,
393				      unsigned *num_pins)
394{
395	*pins = tegra_dpaux_pin_numbers;
396	*num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
397
398	return 0;
399}
400
401static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
402	.get_groups_count = tegra_dpaux_get_groups_count,
403	.get_group_name = tegra_dpaux_get_group_name,
404	.get_group_pins = tegra_dpaux_get_group_pins,
405	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
406	.dt_free_map = pinconf_generic_dt_free_map,
407};
408
409static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
410{
411	return ARRAY_SIZE(tegra_dpaux_functions);
412}
413
414static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
415						 unsigned int function)
416{
417	return tegra_dpaux_functions[function];
418}
419
420static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
421					   unsigned int function,
422					   const char * const **groups,
423					   unsigned * const num_groups)
424{
425	*num_groups = ARRAY_SIZE(tegra_dpaux_groups);
426	*groups = tegra_dpaux_groups;
427
428	return 0;
429}
430
431static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
432			       unsigned int function, unsigned int group)
433{
434	struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
435
436	return tegra_dpaux_pad_config(dpaux, function);
437}
438
439static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
440	.get_functions_count = tegra_dpaux_get_functions_count,
441	.get_function_name = tegra_dpaux_get_function_name,
442	.get_function_groups = tegra_dpaux_get_function_groups,
443	.set_mux = tegra_dpaux_set_mux,
444};
445#endif
446
447static int tegra_dpaux_probe(struct platform_device *pdev)
448{
449	struct tegra_dpaux *dpaux;
450	u32 value;
451	int err;
452
453	dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
454	if (!dpaux)
455		return -ENOMEM;
456
457	dpaux->soc = of_device_get_match_data(&pdev->dev);
458	INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
459	init_completion(&dpaux->complete);
460	INIT_LIST_HEAD(&dpaux->list);
461	dpaux->dev = &pdev->dev;
462
463	dpaux->regs = devm_platform_ioremap_resource(pdev, 0);
464	if (IS_ERR(dpaux->regs))
465		return PTR_ERR(dpaux->regs);
466
467	dpaux->irq = platform_get_irq(pdev, 0);
468	if (dpaux->irq < 0)
469		return dpaux->irq;
470
471	if (!pdev->dev.pm_domain) {
472		dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
473		if (IS_ERR(dpaux->rst)) {
474			dev_err(&pdev->dev,
475				"failed to get reset control: %ld\n",
476				PTR_ERR(dpaux->rst));
477			return PTR_ERR(dpaux->rst);
478		}
479	}
480
481	dpaux->clk = devm_clk_get(&pdev->dev, NULL);
482	if (IS_ERR(dpaux->clk)) {
483		dev_err(&pdev->dev, "failed to get module clock: %ld\n",
484			PTR_ERR(dpaux->clk));
485		return PTR_ERR(dpaux->clk);
486	}
487
488	dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
489	if (IS_ERR(dpaux->clk_parent)) {
490		dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
491			PTR_ERR(dpaux->clk_parent));
492		return PTR_ERR(dpaux->clk_parent);
493	}
494
495	err = clk_set_rate(dpaux->clk_parent, 270000000);
496	if (err < 0) {
497		dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
498			err);
499		return err;
500	}
501
502	dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
503	if (IS_ERR(dpaux->vdd)) {
504		if (PTR_ERR(dpaux->vdd) != -ENODEV)
505			return dev_err_probe(&pdev->dev, PTR_ERR(dpaux->vdd),
506					     "failed to get VDD supply\n");
507
508		dpaux->vdd = NULL;
509	}
510
511	platform_set_drvdata(pdev, dpaux);
512	pm_runtime_enable(&pdev->dev);
513	pm_runtime_get_sync(&pdev->dev);
514
515	err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
516			       dev_name(dpaux->dev), dpaux);
517	if (err < 0) {
518		dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
519			dpaux->irq, err);
520		goto err_pm_disable;
521	}
522
523	disable_irq(dpaux->irq);
524
525	dpaux->aux.transfer = tegra_dpaux_transfer;
526	dpaux->aux.dev = &pdev->dev;
527
528	drm_dp_aux_init(&dpaux->aux);
529
530	/*
531	 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
532	 * so power them up and configure them in I2C mode.
533	 *
534	 * The DPAUX code paths reconfigure the pads in AUX mode, but there
535	 * is no possibility to perform the I2C mode configuration in the
536	 * HDMI path.
537	 */
538	err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
539	if (err < 0)
540		goto err_pm_disable;
541
542#ifdef CONFIG_GENERIC_PINCONF
543	dpaux->desc.name = dev_name(&pdev->dev);
544	dpaux->desc.pins = tegra_dpaux_pins;
545	dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
546	dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
547	dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
548	dpaux->desc.owner = THIS_MODULE;
549
550	dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
551	if (IS_ERR(dpaux->pinctrl)) {
552		dev_err(&pdev->dev, "failed to register pincontrol\n");
553		err = PTR_ERR(dpaux->pinctrl);
554		goto err_pm_disable;
555	}
556#endif
557	/* enable and clear all interrupts */
558	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
559		DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
560	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
561	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
562
563	mutex_lock(&dpaux_lock);
564	list_add_tail(&dpaux->list, &dpaux_list);
565	mutex_unlock(&dpaux_lock);
566
567	err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux);
568	if (err < 0) {
569		dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err);
570		goto err_pm_disable;
571	}
572
573	return 0;
574
575err_pm_disable:
576	pm_runtime_put_sync(&pdev->dev);
577	pm_runtime_disable(&pdev->dev);
578	return err;
579}
580
581static void tegra_dpaux_remove(struct platform_device *pdev)
582{
583	struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
584
585	cancel_work_sync(&dpaux->work);
586
587	/* make sure pads are powered down when not in use */
588	tegra_dpaux_pad_power_down(dpaux);
589
590	pm_runtime_put_sync(&pdev->dev);
591	pm_runtime_disable(&pdev->dev);
592
593	mutex_lock(&dpaux_lock);
594	list_del(&dpaux->list);
595	mutex_unlock(&dpaux_lock);
596}
597
598static int tegra_dpaux_suspend(struct device *dev)
599{
600	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
601	int err = 0;
602
603	if (dpaux->rst) {
604		err = reset_control_assert(dpaux->rst);
605		if (err < 0) {
606			dev_err(dev, "failed to assert reset: %d\n", err);
607			return err;
608		}
609	}
610
611	usleep_range(1000, 2000);
612
613	clk_disable_unprepare(dpaux->clk_parent);
614	clk_disable_unprepare(dpaux->clk);
615
616	return err;
617}
618
619static int tegra_dpaux_resume(struct device *dev)
620{
621	struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
622	int err;
623
624	err = clk_prepare_enable(dpaux->clk);
625	if (err < 0) {
626		dev_err(dev, "failed to enable clock: %d\n", err);
627		return err;
628	}
629
630	err = clk_prepare_enable(dpaux->clk_parent);
631	if (err < 0) {
632		dev_err(dev, "failed to enable parent clock: %d\n", err);
633		goto disable_clk;
634	}
635
636	usleep_range(1000, 2000);
637
638	if (dpaux->rst) {
639		err = reset_control_deassert(dpaux->rst);
640		if (err < 0) {
641			dev_err(dev, "failed to deassert reset: %d\n", err);
642			goto disable_parent;
643		}
644
645		usleep_range(1000, 2000);
646	}
647
648	return 0;
649
650disable_parent:
651	clk_disable_unprepare(dpaux->clk_parent);
652disable_clk:
653	clk_disable_unprepare(dpaux->clk);
654	return err;
655}
656
657static const struct dev_pm_ops tegra_dpaux_pm_ops = {
658	RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
659};
660
661static const struct tegra_dpaux_soc tegra124_dpaux_soc = {
662	.cmh = 0x02,
663	.drvz = 0x04,
664	.drvi = 0x18,
665};
666
667static const struct tegra_dpaux_soc tegra210_dpaux_soc = {
668	.cmh = 0x02,
669	.drvz = 0x04,
670	.drvi = 0x30,
671};
672
673static const struct tegra_dpaux_soc tegra194_dpaux_soc = {
674	.cmh = 0x02,
675	.drvz = 0x04,
676	.drvi = 0x2c,
677};
678
679static const struct of_device_id tegra_dpaux_of_match[] = {
680	{ .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
681	{ .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
682	{ .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
683	{ .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
684	{ },
685};
686MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
687
688struct platform_driver tegra_dpaux_driver = {
689	.driver = {
690		.name = "tegra-dpaux",
691		.of_match_table = tegra_dpaux_of_match,
692		.pm = pm_ptr(&tegra_dpaux_pm_ops),
693	},
694	.probe = tegra_dpaux_probe,
695	.remove = tegra_dpaux_remove,
696};
697
698struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
699{
700	struct tegra_dpaux *dpaux;
701
702	mutex_lock(&dpaux_lock);
703
704	list_for_each_entry(dpaux, &dpaux_list, list)
705		if (np == dpaux->dev->of_node) {
706			mutex_unlock(&dpaux_lock);
707			return &dpaux->aux;
708		}
709
710	mutex_unlock(&dpaux_lock);
711
712	return NULL;
713}
714
715int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
716{
717	struct tegra_dpaux *dpaux = to_dpaux(aux);
718	unsigned long timeout;
719	int err;
720
721	aux->drm_dev = output->connector.dev;
722	err = drm_dp_aux_register(aux);
723	if (err < 0)
724		return err;
725
726	output->connector.polled = DRM_CONNECTOR_POLL_HPD;
727	dpaux->output = output;
728
729	if (output->panel) {
730		enum drm_connector_status status;
731
732		if (dpaux->vdd) {
733			err = regulator_enable(dpaux->vdd);
734			if (err < 0)
735				return err;
736		}
737
738		timeout = jiffies + msecs_to_jiffies(250);
739
740		while (time_before(jiffies, timeout)) {
741			status = drm_dp_aux_detect(aux);
742
743			if (status == connector_status_connected)
744				break;
745
746			usleep_range(1000, 2000);
747		}
748
749		if (status != connector_status_connected)
750			return -ETIMEDOUT;
751	}
752
753	enable_irq(dpaux->irq);
754	return 0;
755}
756
757int drm_dp_aux_detach(struct drm_dp_aux *aux)
758{
759	struct tegra_dpaux *dpaux = to_dpaux(aux);
760	unsigned long timeout;
761	int err;
762
763	drm_dp_aux_unregister(aux);
764	disable_irq(dpaux->irq);
765
766	if (dpaux->output->panel) {
767		enum drm_connector_status status;
768
769		if (dpaux->vdd) {
770			err = regulator_disable(dpaux->vdd);
771			if (err < 0)
772				return err;
773		}
774
775		timeout = jiffies + msecs_to_jiffies(250);
776
777		while (time_before(jiffies, timeout)) {
778			status = drm_dp_aux_detect(aux);
779
780			if (status == connector_status_disconnected)
781				break;
782
783			usleep_range(1000, 2000);
784		}
785
786		if (status != connector_status_disconnected)
787			return -ETIMEDOUT;
788
789		dpaux->output = NULL;
790	}
791
792	return 0;
793}
794
795enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
796{
797	struct tegra_dpaux *dpaux = to_dpaux(aux);
798	u32 value;
799
800	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
801
802	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
803		return connector_status_connected;
804
805	return connector_status_disconnected;
806}
807
808int drm_dp_aux_enable(struct drm_dp_aux *aux)
809{
810	struct tegra_dpaux *dpaux = to_dpaux(aux);
811
812	return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
813}
814
815int drm_dp_aux_disable(struct drm_dp_aux *aux)
816{
817	struct tegra_dpaux *dpaux = to_dpaux(aux);
818
819	tegra_dpaux_pad_power_down(dpaux);
820
821	return 0;
822}