dc.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2012 Avionic Design GmbH
   4 * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/debugfs.h>
   9#include <linux/delay.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/iommu.h>
  12#include <linux/interconnect.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/platform_device.h>
  16#include <linux/pm_domain.h>
  17#include <linux/pm_opp.h>
  18#include <linux/pm_runtime.h>
  19#include <linux/reset.h>
  20
  21#include <soc/tegra/common.h>
  22#include <soc/tegra/pmc.h>
  23
  24#include <drm/drm_atomic.h>
  25#include <drm/drm_atomic_helper.h>
  26#include <drm/drm_blend.h>
  27#include <drm/drm_debugfs.h>
  28#include <drm/drm_fourcc.h>
  29#include <drm/drm_framebuffer.h>
  30#include <drm/drm_print.h>
  31#include <drm/drm_vblank.h>
  32
  33#include "dc.h"
  34#include "drm.h"
  35#include "gem.h"
  36#include "hub.h"
  37#include "plane.h"
  38
  39static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
  40					    struct drm_crtc_state *state);
  41
  42static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  43{
  44	stats->frames = 0;
  45	stats->vblank = 0;
  46	stats->underflow = 0;
  47	stats->overflow = 0;
  48}
  49
  50/* Reads the active copy of a register. */
  51static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  52{
  53	u32 value;
  54
  55	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  56	value = tegra_dc_readl(dc, offset);
  57	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  58
  59	return value;
  60}
  61
  62static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  63					      unsigned int offset)
  64{
  65	if (offset >= 0x500 && offset <= 0x638) {
  66		offset = 0x000 + (offset - 0x500);
  67		return plane->offset + offset;
  68	}
  69
  70	if (offset >= 0x700 && offset <= 0x719) {
  71		offset = 0x180 + (offset - 0x700);
  72		return plane->offset + offset;
  73	}
  74
  75	if (offset >= 0x800 && offset <= 0x839) {
  76		offset = 0x1c0 + (offset - 0x800);
  77		return plane->offset + offset;
  78	}
  79
  80	dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  81
  82	return plane->offset + offset;
  83}
  84
  85static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  86				    unsigned int offset)
  87{
  88	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  89}
  90
  91static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  92				      unsigned int offset)
  93{
  94	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  95}
  96
  97bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  98{
  99	struct device_node *np = dc->dev->of_node;
 100	struct of_phandle_iterator it;
 101	int err;
 102
 103	of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
 104		if (it.node == dev->of_node)
 105			return true;
 106
 107	return false;
 108}
 109
 110/*
 111 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 112 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 113 * Latching happens mmediately if the display controller is in STOP mode or
 114 * on the next frame boundary otherwise.
 115 *
 116 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 117 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 118 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 119 * into the ACTIVE copy, either immediately if the display controller is in
 120 * STOP mode, or at the next frame boundary otherwise.
 121 */
 122void tegra_dc_commit(struct tegra_dc *dc)
 123{
 124	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 125	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 126}
 127
 128static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 129				  unsigned int bpp)
 130{
 131	fixed20_12 outf = dfixed_init(out);
 132	fixed20_12 inf = dfixed_init(in);
 133	u32 dda_inc;
 134	int max;
 135
 136	if (v)
 137		max = 15;
 138	else {
 139		switch (bpp) {
 140		case 2:
 141			max = 8;
 142			break;
 143
 144		default:
 145			WARN_ON_ONCE(1);
 146			fallthrough;
 147		case 4:
 148			max = 4;
 149			break;
 150		}
 151	}
 152
 153	outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 154	inf.full -= dfixed_const(1);
 155
 156	dda_inc = dfixed_div(inf, outf);
 157	dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 158
 159	return dda_inc;
 160}
 161
 162static inline u32 compute_initial_dda(unsigned int in)
 163{
 164	fixed20_12 inf = dfixed_init(in);
 165	return dfixed_frac(inf);
 166}
 167
 168static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 169{
 170	u32 background[3] = {
 171		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 172		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 173		BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 174	};
 175	u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 176			 BLEND_COLOR_KEY_NONE;
 177	u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 178	struct tegra_plane_state *state;
 179	u32 blending[2];
 180	unsigned int i;
 181
 182	/* disable blending for non-overlapping case */
 183	tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 184	tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 185
 186	state = to_tegra_plane_state(plane->base.state);
 187
 188	if (state->opaque) {
 189		/*
 190		 * Since custom fix-weight blending isn't utilized and weight
 191		 * of top window is set to max, we can enforce dependent
 192		 * blending which in this case results in transparent bottom
 193		 * window if top window is opaque and if top window enables
 194		 * alpha blending, then bottom window is getting alpha value
 195		 * of 1 minus the sum of alpha components of the overlapping
 196		 * plane.
 197		 */
 198		background[0] |= BLEND_CONTROL_DEPENDENT;
 199		background[1] |= BLEND_CONTROL_DEPENDENT;
 200
 201		/*
 202		 * The region where three windows overlap is the intersection
 203		 * of the two regions where two windows overlap. It contributes
 204		 * to the area if all of the windows on top of it have an alpha
 205		 * component.
 206		 */
 207		switch (state->base.normalized_zpos) {
 208		case 0:
 209			if (state->blending[0].alpha &&
 210			    state->blending[1].alpha)
 211				background[2] |= BLEND_CONTROL_DEPENDENT;
 212			break;
 213
 214		case 1:
 215			background[2] |= BLEND_CONTROL_DEPENDENT;
 216			break;
 217		}
 218	} else {
 219		/*
 220		 * Enable alpha blending if pixel format has an alpha
 221		 * component.
 222		 */
 223		foreground |= BLEND_CONTROL_ALPHA;
 224
 225		/*
 226		 * If any of the windows on top of this window is opaque, it
 227		 * will completely conceal this window within that area. If
 228		 * top window has an alpha component, it is blended over the
 229		 * bottom window.
 230		 */
 231		for (i = 0; i < 2; i++) {
 232			if (state->blending[i].alpha &&
 233			    state->blending[i].top)
 234				background[i] |= BLEND_CONTROL_DEPENDENT;
 235		}
 236
 237		switch (state->base.normalized_zpos) {
 238		case 0:
 239			if (state->blending[0].alpha &&
 240			    state->blending[1].alpha)
 241				background[2] |= BLEND_CONTROL_DEPENDENT;
 242			break;
 243
 244		case 1:
 245			/*
 246			 * When both middle and topmost windows have an alpha,
 247			 * these windows a mixed together and then the result
 248			 * is blended over the bottom window.
 249			 */
 250			if (state->blending[0].alpha &&
 251			    state->blending[0].top)
 252				background[2] |= BLEND_CONTROL_ALPHA;
 253
 254			if (state->blending[1].alpha &&
 255			    state->blending[1].top)
 256				background[2] |= BLEND_CONTROL_ALPHA;
 257			break;
 258		}
 259	}
 260
 261	switch (state->base.normalized_zpos) {
 262	case 0:
 263		tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 264		tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 265		tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 266		break;
 267
 268	case 1:
 269		/*
 270		 * If window B / C is topmost, then X / Y registers are
 271		 * matching the order of blending[...] state indices,
 272		 * otherwise a swap is required.
 273		 */
 274		if (!state->blending[0].top && state->blending[1].top) {
 275			blending[0] = foreground;
 276			blending[1] = background[1];
 277		} else {
 278			blending[0] = background[0];
 279			blending[1] = foreground;
 280		}
 281
 282		tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 283		tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 284		tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 285		break;
 286
 287	case 2:
 288		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 289		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 290		tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 291		break;
 292	}
 293}
 294
 295static void tegra_plane_setup_blending(struct tegra_plane *plane,
 296				       const struct tegra_dc_window *window)
 297{
 298	u32 value;
 299
 300	value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 301		BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 302		BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 303	tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 304
 305	value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 306		BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 307		BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 308	tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 309
 310	value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 311	tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 312}
 313
 314static bool
 315tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 316				     const struct tegra_dc_window *window)
 317{
 318	struct tegra_dc *dc = plane->dc;
 319
 320	if (window->src.w == window->dst.w)
 321		return false;
 322
 323	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 324		return false;
 325
 326	return true;
 327}
 328
 329static bool
 330tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 331				   const struct tegra_dc_window *window)
 332{
 333	struct tegra_dc *dc = plane->dc;
 334
 335	if (window->src.h == window->dst.h)
 336		return false;
 337
 338	if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 339		return false;
 340
 341	if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 342		return false;
 343
 344	return true;
 345}
 346
 347static void tegra_dc_setup_window(struct tegra_plane *plane,
 348				  const struct tegra_dc_window *window)
 349{
 350	unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 351	struct tegra_dc *dc = plane->dc;
 352	unsigned int planes;
 353	u32 value;
 354	bool yuv;
 355
 356	/*
 357	 * For YUV planar modes, the number of bytes per pixel takes into
 358	 * account only the luma component and therefore is 1.
 359	 */
 360	yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL);
 361	if (!yuv)
 362		bpp = window->bits_per_pixel / 8;
 363	else
 364		bpp = (planes > 1) ? 1 : 2;
 365
 366	tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 367	tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 368
 369	value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 370	tegra_plane_writel(plane, value, DC_WIN_POSITION);
 371
 372	value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 373	tegra_plane_writel(plane, value, DC_WIN_SIZE);
 374
 375	h_offset = window->src.x * bpp;
 376	v_offset = window->src.y;
 377	h_size = window->src.w * bpp;
 378	v_size = window->src.h;
 379
 380	if (window->reflect_x)
 381		h_offset += (window->src.w - 1) * bpp;
 382
 383	if (window->reflect_y)
 384		v_offset += window->src.h - 1;
 385
 386	value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 387	tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 388
 389	/*
 390	 * For DDA computations the number of bytes per pixel for YUV planar
 391	 * modes needs to take into account all Y, U and V components.
 392	 */
 393	if (yuv && planes > 1)
 394		bpp = 2;
 395
 396	h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 397	v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 398
 399	value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 400	tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 401
 402	h_dda = compute_initial_dda(window->src.x);
 403	v_dda = compute_initial_dda(window->src.y);
 404
 405	tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 406	tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 407
 408	tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 409	tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 410
 411	tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 412
 413	if (yuv && planes > 1) {
 414		tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 415
 416		if (planes > 2)
 417			tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 418
 419		value = window->stride[1] << 16 | window->stride[0];
 420		tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 421	} else {
 422		tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 423	}
 424
 425	tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 426	tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 427
 428	if (dc->soc->supports_block_linear) {
 429		unsigned long height = window->tiling.value;
 430
 431		switch (window->tiling.mode) {
 432		case TEGRA_BO_TILING_MODE_PITCH:
 433			value = DC_WINBUF_SURFACE_KIND_PITCH;
 434			break;
 435
 436		case TEGRA_BO_TILING_MODE_TILED:
 437			value = DC_WINBUF_SURFACE_KIND_TILED;
 438			break;
 439
 440		case TEGRA_BO_TILING_MODE_BLOCK:
 441			value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 442				DC_WINBUF_SURFACE_KIND_BLOCK;
 443			break;
 444		}
 445
 446		tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 447	} else {
 448		switch (window->tiling.mode) {
 449		case TEGRA_BO_TILING_MODE_PITCH:
 450			value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 451				DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 452			break;
 453
 454		case TEGRA_BO_TILING_MODE_TILED:
 455			value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 456				DC_WIN_BUFFER_ADDR_MODE_TILE;
 457			break;
 458
 459		case TEGRA_BO_TILING_MODE_BLOCK:
 460			/*
 461			 * No need to handle this here because ->atomic_check
 462			 * will already have filtered it out.
 463			 */
 464			break;
 465		}
 466
 467		tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 468	}
 469
 470	value = WIN_ENABLE;
 471
 472	if (yuv) {
 473		/* setup default colorspace conversion coefficients */
 474		tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 475		tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 476		tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 477		tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 478		tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 479		tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 480		tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 481		tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 482
 483		value |= CSC_ENABLE;
 484	} else if (window->bits_per_pixel < 24) {
 485		value |= COLOR_EXPAND;
 486	}
 487
 488	if (window->reflect_x)
 489		value |= H_DIRECTION;
 490
 491	if (window->reflect_y)
 492		value |= V_DIRECTION;
 493
 494	if (tegra_plane_use_horizontal_filtering(plane, window)) {
 495		/*
 496		 * Enable horizontal 6-tap filter and set filtering
 497		 * coefficients to the default values defined in TRM.
 498		 */
 499		tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 500		tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 501		tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 502		tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 503		tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 504		tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 505		tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 506		tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 507		tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 508		tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 509		tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 510		tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 511		tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 512		tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 513		tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 514		tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 515
 516		value |= H_FILTER;
 517	}
 518
 519	if (tegra_plane_use_vertical_filtering(plane, window)) {
 520		unsigned int i, k;
 521
 522		/*
 523		 * Enable vertical 2-tap filter and set filtering
 524		 * coefficients to the default values defined in TRM.
 525		 */
 526		for (i = 0, k = 128; i < 16; i++, k -= 8)
 527			tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 528
 529		value |= V_FILTER;
 530	}
 531
 532	tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 533
 534	if (dc->soc->has_legacy_blending)
 535		tegra_plane_setup_blending_legacy(plane);
 536	else
 537		tegra_plane_setup_blending(plane, window);
 538}
 539
 540static const u32 tegra20_primary_formats[] = {
 541	DRM_FORMAT_ARGB4444,
 542	DRM_FORMAT_ARGB1555,
 543	DRM_FORMAT_RGB565,
 544	DRM_FORMAT_RGBA5551,
 545	DRM_FORMAT_ABGR8888,
 546	DRM_FORMAT_ARGB8888,
 547	/* non-native formats */
 548	DRM_FORMAT_XRGB1555,
 549	DRM_FORMAT_RGBX5551,
 550	DRM_FORMAT_XBGR8888,
 551	DRM_FORMAT_XRGB8888,
 552};
 553
 554static const u64 tegra20_modifiers[] = {
 555	DRM_FORMAT_MOD_LINEAR,
 556	DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 557	DRM_FORMAT_MOD_INVALID
 558};
 559
 560static const u32 tegra114_primary_formats[] = {
 561	DRM_FORMAT_ARGB4444,
 562	DRM_FORMAT_ARGB1555,
 563	DRM_FORMAT_RGB565,
 564	DRM_FORMAT_RGBA5551,
 565	DRM_FORMAT_ABGR8888,
 566	DRM_FORMAT_ARGB8888,
 567	/* new on Tegra114 */
 568	DRM_FORMAT_ABGR4444,
 569	DRM_FORMAT_ABGR1555,
 570	DRM_FORMAT_BGRA5551,
 571	DRM_FORMAT_XRGB1555,
 572	DRM_FORMAT_RGBX5551,
 573	DRM_FORMAT_XBGR1555,
 574	DRM_FORMAT_BGRX5551,
 575	DRM_FORMAT_BGR565,
 576	DRM_FORMAT_BGRA8888,
 577	DRM_FORMAT_RGBA8888,
 578	DRM_FORMAT_XRGB8888,
 579	DRM_FORMAT_XBGR8888,
 580};
 581
 582static const u32 tegra124_primary_formats[] = {
 583	DRM_FORMAT_ARGB4444,
 584	DRM_FORMAT_ARGB1555,
 585	DRM_FORMAT_RGB565,
 586	DRM_FORMAT_RGBA5551,
 587	DRM_FORMAT_ABGR8888,
 588	DRM_FORMAT_ARGB8888,
 589	/* new on Tegra114 */
 590	DRM_FORMAT_ABGR4444,
 591	DRM_FORMAT_ABGR1555,
 592	DRM_FORMAT_BGRA5551,
 593	DRM_FORMAT_XRGB1555,
 594	DRM_FORMAT_RGBX5551,
 595	DRM_FORMAT_XBGR1555,
 596	DRM_FORMAT_BGRX5551,
 597	DRM_FORMAT_BGR565,
 598	DRM_FORMAT_BGRA8888,
 599	DRM_FORMAT_RGBA8888,
 600	DRM_FORMAT_XRGB8888,
 601	DRM_FORMAT_XBGR8888,
 602	/* new on Tegra124 */
 603	DRM_FORMAT_RGBX8888,
 604	DRM_FORMAT_BGRX8888,
 605};
 606
 607static const u64 tegra124_modifiers[] = {
 608	DRM_FORMAT_MOD_LINEAR,
 609	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 610	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 611	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 612	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 613	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 614	DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 615	DRM_FORMAT_MOD_INVALID
 616};
 617
 618static int tegra_plane_atomic_check(struct drm_plane *plane,
 619				    struct drm_atomic_state *state)
 620{
 621	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 622										 plane);
 623	struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
 624	unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
 625					  DRM_MODE_REFLECT_X |
 626					  DRM_MODE_REFLECT_Y;
 627	unsigned int rotation = new_plane_state->rotation;
 628	struct tegra_bo_tiling *tiling = &plane_state->tiling;
 629	struct tegra_plane *tegra = to_tegra_plane(plane);
 630	struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
 631	int err;
 632
 633	plane_state->peak_memory_bandwidth = 0;
 634	plane_state->avg_memory_bandwidth = 0;
 635
 636	/* no need for further checks if the plane is being disabled */
 637	if (!new_plane_state->crtc) {
 638		plane_state->total_peak_memory_bandwidth = 0;
 639		return 0;
 640	}
 641
 642	err = tegra_plane_format(new_plane_state->fb->format->format,
 643				 &plane_state->format,
 644				 &plane_state->swap);
 645	if (err < 0)
 646		return err;
 647
 648	/*
 649	 * Tegra20 and Tegra30 are special cases here because they support
 650	 * only variants of specific formats with an alpha component, but not
 651	 * the corresponding opaque formats. However, the opaque formats can
 652	 * be emulated by disabling alpha blending for the plane.
 653	 */
 654	if (dc->soc->has_legacy_blending) {
 655		err = tegra_plane_setup_legacy_state(tegra, plane_state);
 656		if (err < 0)
 657			return err;
 658	}
 659
 660	err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
 661	if (err < 0)
 662		return err;
 663
 664	if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 665	    !dc->soc->supports_block_linear) {
 666		DRM_ERROR("hardware doesn't support block linear mode\n");
 667		return -EINVAL;
 668	}
 669
 670	/*
 671	 * Older userspace used custom BO flag in order to specify the Y
 672	 * reflection, while modern userspace uses the generic DRM rotation
 673	 * property in order to achieve the same result.  The legacy BO flag
 674	 * duplicates the DRM rotation property when both are set.
 675	 */
 676	if (tegra_fb_is_bottom_up(new_plane_state->fb))
 677		rotation |= DRM_MODE_REFLECT_Y;
 678
 679	rotation = drm_rotation_simplify(rotation, supported_rotation);
 680
 681	if (rotation & DRM_MODE_REFLECT_X)
 682		plane_state->reflect_x = true;
 683	else
 684		plane_state->reflect_x = false;
 685
 686	if (rotation & DRM_MODE_REFLECT_Y)
 687		plane_state->reflect_y = true;
 688	else
 689		plane_state->reflect_y = false;
 690
 691	/*
 692	 * Tegra doesn't support different strides for U and V planes so we
 693	 * error out if the user tries to display a framebuffer with such a
 694	 * configuration.
 695	 */
 696	if (new_plane_state->fb->format->num_planes > 2) {
 697		if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
 698			DRM_ERROR("unsupported UV-plane configuration\n");
 699			return -EINVAL;
 700		}
 701	}
 702
 703	err = tegra_plane_state_add(tegra, new_plane_state);
 704	if (err < 0)
 705		return err;
 706
 707	return 0;
 708}
 709
 710static void tegra_plane_atomic_disable(struct drm_plane *plane,
 711				       struct drm_atomic_state *state)
 712{
 713	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 714									   plane);
 715	struct tegra_plane *p = to_tegra_plane(plane);
 716	u32 value;
 717
 718	/* rien ne va plus */
 719	if (!old_state || !old_state->crtc)
 720		return;
 721
 722	value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 723	value &= ~WIN_ENABLE;
 724	tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 725}
 726
 727static void tegra_plane_atomic_update(struct drm_plane *plane,
 728				      struct drm_atomic_state *state)
 729{
 730	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 731									   plane);
 732	struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 733	struct drm_framebuffer *fb = new_state->fb;
 734	struct tegra_plane *p = to_tegra_plane(plane);
 735	struct tegra_dc_window window;
 736	unsigned int i;
 737
 738	/* rien ne va plus */
 739	if (!new_state->crtc || !new_state->fb)
 740		return;
 741
 742	if (!new_state->visible)
 743		return tegra_plane_atomic_disable(plane, state);
 744
 745	memset(&window, 0, sizeof(window));
 746	window.src.x = new_state->src.x1 >> 16;
 747	window.src.y = new_state->src.y1 >> 16;
 748	window.src.w = drm_rect_width(&new_state->src) >> 16;
 749	window.src.h = drm_rect_height(&new_state->src) >> 16;
 750	window.dst.x = new_state->dst.x1;
 751	window.dst.y = new_state->dst.y1;
 752	window.dst.w = drm_rect_width(&new_state->dst);
 753	window.dst.h = drm_rect_height(&new_state->dst);
 754	window.bits_per_pixel = fb->format->cpp[0] * 8;
 755	window.reflect_x = tegra_plane_state->reflect_x;
 756	window.reflect_y = tegra_plane_state->reflect_y;
 757
 758	/* copy from state */
 759	window.zpos = new_state->normalized_zpos;
 760	window.tiling = tegra_plane_state->tiling;
 761	window.format = tegra_plane_state->format;
 762	window.swap = tegra_plane_state->swap;
 763
 764	for (i = 0; i < fb->format->num_planes; i++) {
 765		window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
 766
 767		/*
 768		 * Tegra uses a shared stride for UV planes. Framebuffers are
 769		 * already checked for this in the tegra_plane_atomic_check()
 770		 * function, so it's safe to ignore the V-plane pitch here.
 771		 */
 772		if (i < 2)
 773			window.stride[i] = fb->pitches[i];
 774	}
 775
 776	tegra_dc_setup_window(p, &window);
 777}
 778
 779static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 780	.prepare_fb = tegra_plane_prepare_fb,
 781	.cleanup_fb = tegra_plane_cleanup_fb,
 782	.atomic_check = tegra_plane_atomic_check,
 783	.atomic_disable = tegra_plane_atomic_disable,
 784	.atomic_update = tegra_plane_atomic_update,
 785};
 786
 787static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 788{
 789	/*
 790	 * Ideally this would use drm_crtc_mask(), but that would require the
 791	 * CRTC to already be in the mode_config's list of CRTCs. However, it
 792	 * will only be added to that list in the drm_crtc_init_with_planes()
 793	 * (in tegra_dc_init()), which in turn requires registration of these
 794	 * planes. So we have ourselves a nice little chicken and egg problem
 795	 * here.
 796	 *
 797	 * We work around this by manually creating the mask from the number
 798	 * of CRTCs that have been registered, and should therefore always be
 799	 * the same as drm_crtc_index() after registration.
 800	 */
 801	return 1 << drm->mode_config.num_crtc;
 802}
 803
 804static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 805						    struct tegra_dc *dc)
 806{
 807	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 808	enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 809	struct tegra_plane *plane;
 810	unsigned int num_formats;
 811	const u64 *modifiers;
 812	const u32 *formats;
 813	int err;
 814
 815	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 816	if (!plane)
 817		return ERR_PTR(-ENOMEM);
 818
 819	/* Always use window A as primary window */
 820	plane->offset = 0xa00;
 821	plane->index = 0;
 822	plane->dc = dc;
 823
 824	num_formats = dc->soc->num_primary_formats;
 825	formats = dc->soc->primary_formats;
 826	modifiers = dc->soc->modifiers;
 827
 828	err = tegra_plane_interconnect_init(plane);
 829	if (err) {
 830		kfree(plane);
 831		return ERR_PTR(err);
 832	}
 833
 834	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 835				       &tegra_plane_funcs, formats,
 836				       num_formats, modifiers, type, NULL);
 837	if (err < 0) {
 838		kfree(plane);
 839		return ERR_PTR(err);
 840	}
 841
 842	drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 843	drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 844
 845	err = drm_plane_create_rotation_property(&plane->base,
 846						 DRM_MODE_ROTATE_0,
 847						 DRM_MODE_ROTATE_0 |
 848						 DRM_MODE_ROTATE_180 |
 849						 DRM_MODE_REFLECT_X |
 850						 DRM_MODE_REFLECT_Y);
 851	if (err < 0)
 852		dev_err(dc->dev, "failed to create rotation property: %d\n",
 853			err);
 854
 855	return &plane->base;
 856}
 857
 858static const u32 tegra_legacy_cursor_plane_formats[] = {
 859	DRM_FORMAT_RGBA8888,
 860};
 861
 862static const u32 tegra_cursor_plane_formats[] = {
 863	DRM_FORMAT_ARGB8888,
 864};
 865
 866static int tegra_cursor_atomic_check(struct drm_plane *plane,
 867				     struct drm_atomic_state *state)
 868{
 869	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 870										 plane);
 871	struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
 872	struct tegra_plane *tegra = to_tegra_plane(plane);
 873	int err;
 874
 875	plane_state->peak_memory_bandwidth = 0;
 876	plane_state->avg_memory_bandwidth = 0;
 877
 878	/* no need for further checks if the plane is being disabled */
 879	if (!new_plane_state->crtc) {
 880		plane_state->total_peak_memory_bandwidth = 0;
 881		return 0;
 882	}
 883
 884	/* scaling not supported for cursor */
 885	if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
 886	    (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
 887		return -EINVAL;
 888
 889	/* only square cursors supported */
 890	if (new_plane_state->src_w != new_plane_state->src_h)
 891		return -EINVAL;
 892
 893	if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
 894	    new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
 895		return -EINVAL;
 896
 897	err = tegra_plane_state_add(tegra, new_plane_state);
 898	if (err < 0)
 899		return err;
 900
 901	return 0;
 902}
 903
 904static void __tegra_cursor_atomic_update(struct drm_plane *plane,
 905					 struct drm_plane_state *new_state)
 906{
 907	struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 908	struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
 909	struct tegra_drm *tegra = plane->dev->dev_private;
 910#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 911	u64 dma_mask = *dc->dev->dma_mask;
 912#endif
 913	unsigned int x, y;
 914	u32 value = 0;
 915
 916	/* rien ne va plus */
 917	if (!new_state->crtc || !new_state->fb)
 918		return;
 919
 920	/*
 921	 * Legacy display supports hardware clipping of the cursor, but
 922	 * nvdisplay relies on software to clip the cursor to the screen.
 923	 */
 924	if (!dc->soc->has_nvdisplay)
 925		value |= CURSOR_CLIP_DISPLAY;
 926
 927	switch (new_state->crtc_w) {
 928	case 32:
 929		value |= CURSOR_SIZE_32x32;
 930		break;
 931
 932	case 64:
 933		value |= CURSOR_SIZE_64x64;
 934		break;
 935
 936	case 128:
 937		value |= CURSOR_SIZE_128x128;
 938		break;
 939
 940	case 256:
 941		value |= CURSOR_SIZE_256x256;
 942		break;
 943
 944	default:
 945		WARN(1, "cursor size %ux%u not supported\n",
 946		     new_state->crtc_w, new_state->crtc_h);
 947		return;
 948	}
 949
 950	value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
 951	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 952
 953#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 954	value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
 955	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 956#endif
 957
 958	/* enable cursor and set blend mode */
 959	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 960	value |= CURSOR_ENABLE;
 961	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 962
 963	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 964	value &= ~CURSOR_DST_BLEND_MASK;
 965	value &= ~CURSOR_SRC_BLEND_MASK;
 966
 967	if (dc->soc->has_nvdisplay)
 968		value &= ~CURSOR_COMPOSITION_MODE_XOR;
 969	else
 970		value |= CURSOR_MODE_NORMAL;
 971
 972	value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 973	value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 974	value |= CURSOR_ALPHA;
 975	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 976
 977	/* nvdisplay relies on software for clipping */
 978	if (dc->soc->has_nvdisplay) {
 979		struct drm_rect src;
 980
 981		x = new_state->dst.x1;
 982		y = new_state->dst.y1;
 983
 984		drm_rect_fp_to_int(&src, &new_state->src);
 985
 986		value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
 987		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
 988
 989		value = (drm_rect_height(&src) & tegra->vmask) << 16 |
 990			(drm_rect_width(&src) & tegra->hmask);
 991		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
 992	} else {
 993		x = new_state->crtc_x;
 994		y = new_state->crtc_y;
 995	}
 996
 997	/* position the cursor */
 998	value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
 999	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
1000}
1001
1002static void tegra_cursor_atomic_update(struct drm_plane *plane,
1003				       struct drm_atomic_state *state)
1004{
1005	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1006
1007	__tegra_cursor_atomic_update(plane, new_state);
1008}
1009
1010static void tegra_cursor_atomic_disable(struct drm_plane *plane,
1011					struct drm_atomic_state *state)
1012{
1013	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
1014									   plane);
1015	struct tegra_dc *dc;
1016	u32 value;
1017
1018	/* rien ne va plus */
1019	if (!old_state || !old_state->crtc)
1020		return;
1021
1022	dc = to_tegra_dc(old_state->crtc);
1023
1024	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1025	value &= ~CURSOR_ENABLE;
1026	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1027}
1028
1029static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state,
1030					   bool flip)
1031{
1032	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1033	struct drm_crtc_state *crtc_state;
1034	int min_scale, max_scale;
1035	int err;
1036
1037	crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
1038	if (WARN_ON(!crtc_state))
1039		return -EINVAL;
1040
1041	if (!crtc_state->active)
1042		return -EINVAL;
1043
1044	if (plane->state->crtc != new_state->crtc ||
1045	    plane->state->src_w != new_state->src_w ||
1046	    plane->state->src_h != new_state->src_h ||
1047	    plane->state->crtc_w != new_state->crtc_w ||
1048	    plane->state->crtc_h != new_state->crtc_h ||
1049	    plane->state->fb != new_state->fb ||
1050	    plane->state->fb == NULL)
1051		return -EINVAL;
1052
1053	min_scale = (1 << 16) / 8;
1054	max_scale = (8 << 16) / 1;
1055
1056	err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,
1057						  true, true);
1058	if (err < 0)
1059		return err;
1060
1061	if (new_state->visible != plane->state->visible)
1062		return -EINVAL;
1063
1064	return 0;
1065}
1066
1067static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
1068					     struct drm_atomic_state *state)
1069{
1070	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1071	struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
1072
1073	plane->state->src_x = new_state->src_x;
1074	plane->state->src_y = new_state->src_y;
1075	plane->state->crtc_x = new_state->crtc_x;
1076	plane->state->crtc_y = new_state->crtc_y;
1077
1078	if (new_state->visible) {
1079		struct tegra_plane *p = to_tegra_plane(plane);
1080		u32 value;
1081
1082		__tegra_cursor_atomic_update(plane, new_state);
1083
1084		value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE;
1085		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1086		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1087
1088		value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ;
1089		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1090		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1091	}
1092}
1093
1094static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
1095	.prepare_fb = tegra_plane_prepare_fb,
1096	.cleanup_fb = tegra_plane_cleanup_fb,
1097	.atomic_check = tegra_cursor_atomic_check,
1098	.atomic_update = tegra_cursor_atomic_update,
1099	.atomic_disable = tegra_cursor_atomic_disable,
1100	.atomic_async_check = tegra_cursor_atomic_async_check,
1101	.atomic_async_update = tegra_cursor_atomic_async_update,
1102};
1103
1104static const uint64_t linear_modifiers[] = {
1105	DRM_FORMAT_MOD_LINEAR,
1106	DRM_FORMAT_MOD_INVALID
1107};
1108
1109static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1110						      struct tegra_dc *dc)
1111{
1112	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1113	struct tegra_plane *plane;
1114	unsigned int num_formats;
1115	const u32 *formats;
1116	int err;
1117
1118	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1119	if (!plane)
1120		return ERR_PTR(-ENOMEM);
1121
1122	/*
1123	 * This index is kind of fake. The cursor isn't a regular plane, but
1124	 * its update and activation request bits in DC_CMD_STATE_CONTROL do
1125	 * use the same programming. Setting this fake index here allows the
1126	 * code in tegra_add_plane_state() to do the right thing without the
1127	 * need to special-casing the cursor plane.
1128	 */
1129	plane->index = 6;
1130	plane->dc = dc;
1131
1132	if (!dc->soc->has_nvdisplay) {
1133		num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1134		formats = tegra_legacy_cursor_plane_formats;
1135
1136		err = tegra_plane_interconnect_init(plane);
1137		if (err) {
1138			kfree(plane);
1139			return ERR_PTR(err);
1140		}
1141	} else {
1142		num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1143		formats = tegra_cursor_plane_formats;
1144	}
1145
1146	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1147				       &tegra_plane_funcs, formats,
1148				       num_formats, linear_modifiers,
1149				       DRM_PLANE_TYPE_CURSOR, NULL);
1150	if (err < 0) {
1151		kfree(plane);
1152		return ERR_PTR(err);
1153	}
1154
1155	drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1156	drm_plane_create_zpos_immutable_property(&plane->base, 255);
1157
1158	return &plane->base;
1159}
1160
1161static const u32 tegra20_overlay_formats[] = {
1162	DRM_FORMAT_ARGB4444,
1163	DRM_FORMAT_ARGB1555,
1164	DRM_FORMAT_RGB565,
1165	DRM_FORMAT_RGBA5551,
1166	DRM_FORMAT_ABGR8888,
1167	DRM_FORMAT_ARGB8888,
1168	/* non-native formats */
1169	DRM_FORMAT_XRGB1555,
1170	DRM_FORMAT_RGBX5551,
1171	DRM_FORMAT_XBGR8888,
1172	DRM_FORMAT_XRGB8888,
1173	/* planar formats */
1174	DRM_FORMAT_UYVY,
1175	DRM_FORMAT_YUYV,
1176	DRM_FORMAT_YUV420,
1177	DRM_FORMAT_YUV422,
1178};
1179
1180static const u32 tegra114_overlay_formats[] = {
1181	DRM_FORMAT_ARGB4444,
1182	DRM_FORMAT_ARGB1555,
1183	DRM_FORMAT_RGB565,
1184	DRM_FORMAT_RGBA5551,
1185	DRM_FORMAT_ABGR8888,
1186	DRM_FORMAT_ARGB8888,
1187	/* new on Tegra114 */
1188	DRM_FORMAT_ABGR4444,
1189	DRM_FORMAT_ABGR1555,
1190	DRM_FORMAT_BGRA5551,
1191	DRM_FORMAT_XRGB1555,
1192	DRM_FORMAT_RGBX5551,
1193	DRM_FORMAT_XBGR1555,
1194	DRM_FORMAT_BGRX5551,
1195	DRM_FORMAT_BGR565,
1196	DRM_FORMAT_BGRA8888,
1197	DRM_FORMAT_RGBA8888,
1198	DRM_FORMAT_XRGB8888,
1199	DRM_FORMAT_XBGR8888,
1200	/* planar formats */
1201	DRM_FORMAT_UYVY,
1202	DRM_FORMAT_YUYV,
1203	DRM_FORMAT_YUV420,
1204	DRM_FORMAT_YUV422,
1205	/* semi-planar formats */
1206	DRM_FORMAT_NV12,
1207	DRM_FORMAT_NV21,
1208	DRM_FORMAT_NV16,
1209	DRM_FORMAT_NV61,
1210	DRM_FORMAT_NV24,
1211	DRM_FORMAT_NV42,
1212};
1213
1214static const u32 tegra124_overlay_formats[] = {
1215	DRM_FORMAT_ARGB4444,
1216	DRM_FORMAT_ARGB1555,
1217	DRM_FORMAT_RGB565,
1218	DRM_FORMAT_RGBA5551,
1219	DRM_FORMAT_ABGR8888,
1220	DRM_FORMAT_ARGB8888,
1221	/* new on Tegra114 */
1222	DRM_FORMAT_ABGR4444,
1223	DRM_FORMAT_ABGR1555,
1224	DRM_FORMAT_BGRA5551,
1225	DRM_FORMAT_XRGB1555,
1226	DRM_FORMAT_RGBX5551,
1227	DRM_FORMAT_XBGR1555,
1228	DRM_FORMAT_BGRX5551,
1229	DRM_FORMAT_BGR565,
1230	DRM_FORMAT_BGRA8888,
1231	DRM_FORMAT_RGBA8888,
1232	DRM_FORMAT_XRGB8888,
1233	DRM_FORMAT_XBGR8888,
1234	/* new on Tegra124 */
1235	DRM_FORMAT_RGBX8888,
1236	DRM_FORMAT_BGRX8888,
1237	/* planar formats */
1238	DRM_FORMAT_UYVY,
1239	DRM_FORMAT_YUYV,
1240	DRM_FORMAT_YVYU,
1241	DRM_FORMAT_VYUY,
1242	DRM_FORMAT_YUV420, /* YU12 */
1243	DRM_FORMAT_YUV422, /* YU16 */
1244	DRM_FORMAT_YUV444, /* YU24 */
1245	/* semi-planar formats */
1246	DRM_FORMAT_NV12,
1247	DRM_FORMAT_NV21,
1248	DRM_FORMAT_NV16,
1249	DRM_FORMAT_NV61,
1250	DRM_FORMAT_NV24,
1251	DRM_FORMAT_NV42,
1252};
1253
1254static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1255						       struct tegra_dc *dc,
1256						       unsigned int index,
1257						       bool cursor)
1258{
1259	unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1260	struct tegra_plane *plane;
1261	unsigned int num_formats;
1262	enum drm_plane_type type;
1263	const u32 *formats;
1264	int err;
1265
1266	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1267	if (!plane)
1268		return ERR_PTR(-ENOMEM);
1269
1270	plane->offset = 0xa00 + 0x200 * index;
1271	plane->index = index;
1272	plane->dc = dc;
1273
1274	num_formats = dc->soc->num_overlay_formats;
1275	formats = dc->soc->overlay_formats;
1276
1277	err = tegra_plane_interconnect_init(plane);
1278	if (err) {
1279		kfree(plane);
1280		return ERR_PTR(err);
1281	}
1282
1283	if (!cursor)
1284		type = DRM_PLANE_TYPE_OVERLAY;
1285	else
1286		type = DRM_PLANE_TYPE_CURSOR;
1287
1288	err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1289				       &tegra_plane_funcs, formats,
1290				       num_formats, linear_modifiers,
1291				       type, NULL);
1292	if (err < 0) {
1293		kfree(plane);
1294		return ERR_PTR(err);
1295	}
1296
1297	drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1298	drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1299
1300	err = drm_plane_create_rotation_property(&plane->base,
1301						 DRM_MODE_ROTATE_0,
1302						 DRM_MODE_ROTATE_0 |
1303						 DRM_MODE_ROTATE_180 |
1304						 DRM_MODE_REFLECT_X |
1305						 DRM_MODE_REFLECT_Y);
1306	if (err < 0)
1307		dev_err(dc->dev, "failed to create rotation property: %d\n",
1308			err);
1309
1310	return &plane->base;
1311}
1312
1313static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1314						    struct tegra_dc *dc)
1315{
1316	struct drm_plane *plane, *primary = NULL;
1317	unsigned int i, j;
1318
1319	for (i = 0; i < dc->soc->num_wgrps; i++) {
1320		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1321
1322		if (wgrp->dc == dc->pipe) {
1323			for (j = 0; j < wgrp->num_windows; j++) {
1324				unsigned int index = wgrp->windows[j];
1325				enum drm_plane_type type;
1326
1327				if (primary)
1328					type = DRM_PLANE_TYPE_OVERLAY;
1329				else
1330					type = DRM_PLANE_TYPE_PRIMARY;
1331
1332				plane = tegra_shared_plane_create(drm, dc,
1333								  wgrp->index,
1334								  index, type);
1335				if (IS_ERR(plane))
1336					return plane;
1337
1338				/*
1339				 * Choose the first shared plane owned by this
1340				 * head as the primary plane.
1341				 */
1342				if (!primary)
1343					primary = plane;
1344			}
1345		}
1346	}
1347
1348	return primary;
1349}
1350
1351static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1352					     struct tegra_dc *dc)
1353{
1354	struct drm_plane *planes[2], *primary;
1355	unsigned int planes_num;
1356	unsigned int i;
1357	int err;
1358
1359	primary = tegra_primary_plane_create(drm, dc);
1360	if (IS_ERR(primary))
1361		return primary;
1362
1363	if (dc->soc->supports_cursor)
1364		planes_num = 2;
1365	else
1366		planes_num = 1;
1367
1368	for (i = 0; i < planes_num; i++) {
1369		planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1370							  false);
1371		if (IS_ERR(planes[i])) {
1372			err = PTR_ERR(planes[i]);
1373
1374			while (i--)
1375				planes[i]->funcs->destroy(planes[i]);
1376
1377			primary->funcs->destroy(primary);
1378			return ERR_PTR(err);
1379		}
1380	}
1381
1382	return primary;
1383}
1384
1385static void tegra_dc_destroy(struct drm_crtc *crtc)
1386{
1387	drm_crtc_cleanup(crtc);
1388}
1389
1390static void tegra_crtc_reset(struct drm_crtc *crtc)
1391{
1392	struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1393
1394	if (crtc->state)
1395		tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1396
1397	if (state)
1398		__drm_atomic_helper_crtc_reset(crtc, &state->base);
1399	else
1400		__drm_atomic_helper_crtc_reset(crtc, NULL);
1401}
1402
1403static struct drm_crtc_state *
1404tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1405{
1406	struct tegra_dc_state *state = to_dc_state(crtc->state);
1407	struct tegra_dc_state *copy;
1408
1409	copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1410	if (!copy)
1411		return NULL;
1412
1413	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1414	copy->clk = state->clk;
1415	copy->pclk = state->pclk;
1416	copy->div = state->div;
1417	copy->planes = state->planes;
1418
1419	return &copy->base;
1420}
1421
1422static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1423					    struct drm_crtc_state *state)
1424{
1425	__drm_atomic_helper_crtc_destroy_state(state);
1426	kfree(state);
1427}
1428
1429#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1430
1431static const struct debugfs_reg32 tegra_dc_regs[] = {
1432	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1433	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1434	DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1435	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1436	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1437	DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1438	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1439	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1440	DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1441	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1442	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1443	DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1444	DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1445	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1446	DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1447	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1448	DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1449	DEBUGFS_REG32(DC_CMD_INT_STATUS),
1450	DEBUGFS_REG32(DC_CMD_INT_MASK),
1451	DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1452	DEBUGFS_REG32(DC_CMD_INT_TYPE),
1453	DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1454	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1455	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1456	DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1457	DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1458	DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1459	DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1460	DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1461	DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1462	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1463	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1464	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1465	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1466	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1467	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1468	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1469	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1470	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1471	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1472	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1473	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1474	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1475	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1476	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1477	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1478	DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1479	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1480	DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1481	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1482	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1483	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1484	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1485	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1486	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1487	DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1488	DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1489	DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1490	DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1491	DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1492	DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1493	DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1494	DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1495	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1496	DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1497	DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1498	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1499	DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1500	DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1501	DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1502	DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1503	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1504	DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1505	DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1506	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1507	DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1508	DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1509	DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1510	DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1511	DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1512	DEBUGFS_REG32(DC_DISP_ACTIVE),
1513	DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1514	DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1515	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1516	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1517	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1518	DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1519	DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1520	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1521	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1522	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1523	DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1524	DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1525	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1526	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1527	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1528	DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1529	DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1530	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1531	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1532	DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1533	DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1534	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1535	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1536	DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1537	DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1538	DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1539	DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1540	DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1541	DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1542	DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1543	DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1544	DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1545	DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1546	DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1547	DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1548	DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1549	DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1550	DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1551	DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1552	DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1553	DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1554	DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1555	DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1556	DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1557	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1558	DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1559	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1560	DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1561	DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1562	DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1563	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1564	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1565	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1566	DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1567	DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1568	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1569	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1570	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1571	DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1572	DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1573	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1574	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1575	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1576	DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1577	DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1578	DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1579	DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1580	DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1581	DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1582	DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1583	DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1584	DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1585	DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1586	DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1587	DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1588	DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1589	DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1590	DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1591	DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1592	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1593	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1594	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1595	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1596	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1597	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1598	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1599	DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1600	DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1601	DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1602	DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1603	DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1604	DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1605	DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1606	DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1607	DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1608	DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1609	DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1610	DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1611	DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1612	DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1613	DEBUGFS_REG32(DC_WIN_POSITION),
1614	DEBUGFS_REG32(DC_WIN_SIZE),
1615	DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1616	DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1617	DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1618	DEBUGFS_REG32(DC_WIN_DDA_INC),
1619	DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1620	DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1621	DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1622	DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1623	DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1624	DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1625	DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1626	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1627	DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1628	DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1629	DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1630	DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1631	DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1632	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1633	DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1634	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1635	DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1636	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1637	DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1638	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1639	DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1640	DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1641	DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1642	DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1643	DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1644};
1645
1646static int tegra_dc_show_regs(struct seq_file *s, void *data)
1647{
1648	struct drm_info_node *node = s->private;
1649	struct tegra_dc *dc = node->info_ent->data;
1650	unsigned int i;
1651	int err = 0;
1652
1653	drm_modeset_lock(&dc->base.mutex, NULL);
1654
1655	if (!dc->base.state->active) {
1656		err = -EBUSY;
1657		goto unlock;
1658	}
1659
1660	for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1661		unsigned int offset = tegra_dc_regs[i].offset;
1662
1663		seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1664			   offset, tegra_dc_readl(dc, offset));
1665	}
1666
1667unlock:
1668	drm_modeset_unlock(&dc->base.mutex);
1669	return err;
1670}
1671
1672static int tegra_dc_show_crc(struct seq_file *s, void *data)
1673{
1674	struct drm_info_node *node = s->private;
1675	struct tegra_dc *dc = node->info_ent->data;
1676	int err = 0;
1677	u32 value;
1678
1679	drm_modeset_lock(&dc->base.mutex, NULL);
1680
1681	if (!dc->base.state->active) {
1682		err = -EBUSY;
1683		goto unlock;
1684	}
1685
1686	value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1687	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1688	tegra_dc_commit(dc);
1689
1690	drm_crtc_wait_one_vblank(&dc->base);
1691	drm_crtc_wait_one_vblank(&dc->base);
1692
1693	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1694	seq_printf(s, "%08x\n", value);
1695
1696	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1697
1698unlock:
1699	drm_modeset_unlock(&dc->base.mutex);
1700	return err;
1701}
1702
1703static int tegra_dc_show_stats(struct seq_file *s, void *data)
1704{
1705	struct drm_info_node *node = s->private;
1706	struct tegra_dc *dc = node->info_ent->data;
1707
1708	seq_printf(s, "frames: %lu\n", dc->stats.frames);
1709	seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1710	seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1711	seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1712
1713	seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
1714	seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
1715	seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
1716	seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
1717
1718	return 0;
1719}
1720
1721static struct drm_info_list debugfs_files[] = {
1722	{ "regs", tegra_dc_show_regs, 0, NULL },
1723	{ "crc", tegra_dc_show_crc, 0, NULL },
1724	{ "stats", tegra_dc_show_stats, 0, NULL },
1725};
1726
1727static int tegra_dc_late_register(struct drm_crtc *crtc)
1728{
1729	unsigned int i, count = ARRAY_SIZE(debugfs_files);
1730	struct drm_minor *minor = crtc->dev->primary;
1731	struct dentry *root;
1732	struct tegra_dc *dc = to_tegra_dc(crtc);
1733
1734#ifdef CONFIG_DEBUG_FS
1735	root = crtc->debugfs_entry;
1736#else
1737	root = NULL;
1738#endif
1739
1740	dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1741				    GFP_KERNEL);
1742	if (!dc->debugfs_files)
1743		return -ENOMEM;
1744
1745	for (i = 0; i < count; i++)
1746		dc->debugfs_files[i].data = dc;
1747
1748	drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1749
1750	return 0;
1751}
1752
1753static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1754{
1755	unsigned int count = ARRAY_SIZE(debugfs_files);
1756	struct drm_minor *minor = crtc->dev->primary;
1757	struct tegra_dc *dc = to_tegra_dc(crtc);
1758	struct dentry *root;
1759
1760#ifdef CONFIG_DEBUG_FS
1761	root = crtc->debugfs_entry;
1762#else
1763	root = NULL;
1764#endif
1765
1766	drm_debugfs_remove_files(dc->debugfs_files, count, root, minor);
1767	kfree(dc->debugfs_files);
1768	dc->debugfs_files = NULL;
1769}
1770
1771static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1772{
1773	struct tegra_dc *dc = to_tegra_dc(crtc);
1774
1775	/* XXX vblank syncpoints don't work with nvdisplay yet */
1776	if (dc->syncpt && !dc->soc->has_nvdisplay)
1777		return host1x_syncpt_read(dc->syncpt);
1778
1779	/* fallback to software emulated VBLANK counter */
1780	return (u32)drm_crtc_vblank_count(&dc->base);
1781}
1782
1783static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1784{
1785	struct tegra_dc *dc = to_tegra_dc(crtc);
1786	u32 value;
1787
1788	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1789	value |= VBLANK_INT;
1790	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1791
1792	return 0;
1793}
1794
1795static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1796{
1797	struct tegra_dc *dc = to_tegra_dc(crtc);
1798	u32 value;
1799
1800	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1801	value &= ~VBLANK_INT;
1802	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1803}
1804
1805static const struct drm_crtc_funcs tegra_crtc_funcs = {
1806	.page_flip = drm_atomic_helper_page_flip,
1807	.set_config = drm_atomic_helper_set_config,
1808	.destroy = tegra_dc_destroy,
1809	.reset = tegra_crtc_reset,
1810	.atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1811	.atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1812	.late_register = tegra_dc_late_register,
1813	.early_unregister = tegra_dc_early_unregister,
1814	.get_vblank_counter = tegra_dc_get_vblank_counter,
1815	.enable_vblank = tegra_dc_enable_vblank,
1816	.disable_vblank = tegra_dc_disable_vblank,
1817};
1818
1819static int tegra_dc_set_timings(struct tegra_dc *dc,
1820				struct drm_display_mode *mode)
1821{
1822	unsigned int h_ref_to_sync = 1;
1823	unsigned int v_ref_to_sync = 1;
1824	unsigned long value;
1825
1826	if (!dc->soc->has_nvdisplay) {
1827		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1828
1829		value = (v_ref_to_sync << 16) | h_ref_to_sync;
1830		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1831	}
1832
1833	value = ((mode->vsync_end - mode->vsync_start) << 16) |
1834		((mode->hsync_end - mode->hsync_start) <<  0);
1835	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1836
1837	value = ((mode->vtotal - mode->vsync_end) << 16) |
1838		((mode->htotal - mode->hsync_end) <<  0);
1839	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1840
1841	value = ((mode->vsync_start - mode->vdisplay) << 16) |
1842		((mode->hsync_start - mode->hdisplay) <<  0);
1843	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1844
1845	value = (mode->vdisplay << 16) | mode->hdisplay;
1846	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1847
1848	return 0;
1849}
1850
1851/**
1852 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1853 *     state
1854 * @dc: display controller
1855 * @crtc_state: CRTC atomic state
1856 * @clk: parent clock for display controller
1857 * @pclk: pixel clock
1858 * @div: shift clock divider
1859 *
1860 * Returns:
1861 * 0 on success or a negative error-code on failure.
1862 */
1863int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1864			       struct drm_crtc_state *crtc_state,
1865			       struct clk *clk, unsigned long pclk,
1866			       unsigned int div)
1867{
1868	struct tegra_dc_state *state = to_dc_state(crtc_state);
1869
1870	if (!clk_has_parent(dc->clk, clk))
1871		return -EINVAL;
1872
1873	state->clk = clk;
1874	state->pclk = pclk;
1875	state->div = div;
1876
1877	return 0;
1878}
1879
1880static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
1881					  struct tegra_dc_state *state)
1882{
1883	unsigned long rate, pstate;
1884	struct dev_pm_opp *opp;
1885	int err;
1886
1887	if (!dc->has_opp_table)
1888		return;
1889
1890	/* calculate actual pixel clock rate which depends on internal divider */
1891	rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
1892
1893	/* find suitable OPP for the rate */
1894	opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
1895
1896	/*
1897	 * Very high resolution modes may results in a clock rate that is
1898	 * above the characterized maximum. In this case it's okay to fall
1899	 * back to the characterized maximum.
1900	 */
1901	if (opp == ERR_PTR(-ERANGE))
1902		opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
1903
1904	if (IS_ERR(opp)) {
1905		dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
1906			rate, opp);
1907		return;
1908	}
1909
1910	pstate = dev_pm_opp_get_required_pstate(opp, 0);
1911	dev_pm_opp_put(opp);
1912
1913	/*
1914	 * The minimum core voltage depends on the pixel clock rate (which
1915	 * depends on internal clock divider of the CRTC) and not on the
1916	 * rate of the display controller clock. This is why we're not using
1917	 * dev_pm_opp_set_rate() API and instead controlling the power domain
1918	 * directly.
1919	 */
1920	err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
1921	if (err)
1922		dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
1923			pstate, err);
1924}
1925
1926static void tegra_dc_set_clock_rate(struct tegra_dc *dc,
1927				    struct tegra_dc_state *state)
1928{
1929	int err;
1930
1931	err = clk_set_parent(dc->clk, state->clk);
1932	if (err < 0)
1933		dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1934
1935	/*
1936	 * Outputs may not want to change the parent clock rate. This is only
1937	 * relevant to Tegra20 where only a single display PLL is available.
1938	 * Since that PLL would typically be used for HDMI, an internal LVDS
1939	 * panel would need to be driven by some other clock such as PLL_P
1940	 * which is shared with other peripherals. Changing the clock rate
1941	 * should therefore be avoided.
1942	 */
1943	if (state->pclk > 0) {
1944		err = clk_set_rate(state->clk, state->pclk);
1945		if (err < 0)
1946			dev_err(dc->dev,
1947				"failed to set clock rate to %lu Hz\n",
1948				state->pclk);
1949
1950		err = clk_set_rate(dc->clk, state->pclk);
1951		if (err < 0)
1952			dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1953				dc->clk, state->pclk, err);
1954	}
1955
1956	DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1957		      state->div);
1958	DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1959
1960	tegra_dc_update_voltage_state(dc, state);
1961}
1962
1963static void tegra_dc_stop(struct tegra_dc *dc)
1964{
1965	u32 value;
1966
1967	/* stop the display controller */
1968	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1969	value &= ~DISP_CTRL_MODE_MASK;
1970	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1971
1972	tegra_dc_commit(dc);
1973}
1974
1975static bool tegra_dc_idle(struct tegra_dc *dc)
1976{
1977	u32 value;
1978
1979	value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1980
1981	return (value & DISP_CTRL_MODE_MASK) == 0;
1982}
1983
1984static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1985{
1986	timeout = jiffies + msecs_to_jiffies(timeout);
1987
1988	while (time_before(jiffies, timeout)) {
1989		if (tegra_dc_idle(dc))
1990			return 0;
1991
1992		usleep_range(1000, 2000);
1993	}
1994
1995	dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1996	return -ETIMEDOUT;
1997}
1998
1999static void
2000tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
2001				   struct drm_atomic_state *state,
2002				   bool prepare_bandwidth_transition)
2003{
2004	const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
2005	u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
2006	const struct drm_plane_state *old_plane_state;
2007	const struct drm_crtc_state *old_crtc_state;
2008	struct tegra_dc_window window, old_window;
2009	struct tegra_dc *dc = to_tegra_dc(crtc);
2010	struct tegra_plane *tegra;
2011	struct drm_plane *plane;
2012
2013	if (dc->soc->has_nvdisplay)
2014		return;
2015
2016	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
2017
2018	if (!crtc->state->active) {
2019		if (!old_crtc_state->active)
2020			return;
2021
2022		/*
2023		 * When CRTC is disabled on DPMS, the state of attached planes
2024		 * is kept unchanged. Hence we need to enforce removal of the
2025		 * bandwidths from the ICC paths.
2026		 */
2027		drm_atomic_crtc_for_each_plane(plane, crtc) {
2028			tegra = to_tegra_plane(plane);
2029
2030			icc_set_bw(tegra->icc_mem, 0, 0);
2031			icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2032		}
2033
2034		return;
2035	}
2036
2037	for_each_old_plane_in_state(old_crtc_state->state, plane,
2038				    old_plane_state, i) {
2039		old_tegra_state = to_const_tegra_plane_state(old_plane_state);
2040		new_tegra_state = to_const_tegra_plane_state(plane->state);
2041		tegra = to_tegra_plane(plane);
2042
2043		/*
2044		 * We're iterating over the global atomic state and it contains
2045		 * planes from another CRTC, hence we need to filter out the
2046		 * planes unrelated to this CRTC.
2047		 */
2048		if (tegra->dc != dc)
2049			continue;
2050
2051		new_avg_bw = new_tegra_state->avg_memory_bandwidth;
2052		old_avg_bw = old_tegra_state->avg_memory_bandwidth;
2053
2054		new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
2055		old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
2056
2057		/*
2058		 * See the comment related to !crtc->state->active above,
2059		 * which explains why bandwidths need to be updated when
2060		 * CRTC is turning ON.
2061		 */
2062		if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
2063		    old_crtc_state->active)
2064			continue;
2065
2066		window.src.h = drm_rect_height(&plane->state->src) >> 16;
2067		window.dst.h = drm_rect_height(&plane->state->dst);
2068
2069		old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
2070		old_window.dst.h = drm_rect_height(&old_plane_state->dst);
2071
2072		/*
2073		 * During the preparation phase (atomic_begin), the memory
2074		 * freq should go high before the DC changes are committed
2075		 * if bandwidth requirement goes up, otherwise memory freq
2076		 * should to stay high if BW requirement goes down.  The
2077		 * opposite applies to the completion phase (post_commit).
2078		 */
2079		if (prepare_bandwidth_transition) {
2080			new_avg_bw = max(old_avg_bw, new_avg_bw);
2081			new_peak_bw = max(old_peak_bw, new_peak_bw);
2082
2083			if (tegra_plane_use_vertical_filtering(tegra, &old_window))
2084				window = old_window;
2085		}
2086
2087		icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
2088
2089		if (tegra_plane_use_vertical_filtering(tegra, &window))
2090			icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
2091		else
2092			icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2093	}
2094}
2095
2096static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
2097				      struct drm_atomic_state *state)
2098{
2099	struct tegra_dc *dc = to_tegra_dc(crtc);
2100	u32 value;
2101	int err;
2102
2103	if (!tegra_dc_idle(dc)) {
2104		tegra_dc_stop(dc);
2105
2106		/*
2107		 * Ignore the return value, there isn't anything useful to do
2108		 * in case this fails.
2109		 */
2110		tegra_dc_wait_idle(dc, 100);
2111	}
2112
2113	/*
2114	 * This should really be part of the RGB encoder driver, but clearing
2115	 * these bits has the side-effect of stopping the display controller.
2116	 * When that happens no VBLANK interrupts will be raised. At the same
2117	 * time the encoder is disabled before the display controller, so the
2118	 * above code is always going to timeout waiting for the controller
2119	 * to go idle.
2120	 *
2121	 * Given the close coupling between the RGB encoder and the display
2122	 * controller doing it here is still kind of okay. None of the other
2123	 * encoder drivers require these bits to be cleared.
2124	 *
2125	 * XXX: Perhaps given that the display controller is switched off at
2126	 * this point anyway maybe clearing these bits isn't even useful for
2127	 * the RGB encoder?
2128	 */
2129	if (dc->rgb) {
2130		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2131		value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2132			   PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
2133		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2134	}
2135
2136	tegra_dc_stats_reset(&dc->stats);
2137	drm_crtc_vblank_off(crtc);
2138
2139	spin_lock_irq(&crtc->dev->event_lock);
2140
2141	if (crtc->state->event) {
2142		drm_crtc_send_vblank_event(crtc, crtc->state->event);
2143		crtc->state->event = NULL;
2144	}
2145
2146	spin_unlock_irq(&crtc->dev->event_lock);
2147
2148	err = host1x_client_suspend(&dc->client);
2149	if (err < 0)
2150		dev_err(dc->dev, "failed to suspend: %d\n", err);
2151
2152	if (dc->has_opp_table) {
2153		err = dev_pm_genpd_set_performance_state(dc->dev, 0);
2154		if (err)
2155			dev_err(dc->dev,
2156				"failed to clear power domain state: %d\n", err);
2157	}
2158}
2159
2160static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
2161				     struct drm_atomic_state *state)
2162{
2163	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2164	struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
2165	struct tegra_dc *dc = to_tegra_dc(crtc);
2166	u32 value;
2167	int err;
2168
2169	/* apply PLL changes */
2170	tegra_dc_set_clock_rate(dc, crtc_state);
2171
2172	err = host1x_client_resume(&dc->client);
2173	if (err < 0) {
2174		dev_err(dc->dev, "failed to resume: %d\n", err);
2175		return;
2176	}
2177
2178	/* initialize display controller */
2179	if (dc->syncpt) {
2180		u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
2181
2182		if (dc->soc->has_nvdisplay)
2183			enable = 1 << 31;
2184		else
2185			enable = 1 << 8;
2186
2187		value = SYNCPT_CNTRL_NO_STALL;
2188		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2189
2190		value = enable | syncpt;
2191		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
2192	}
2193
2194	if (dc->soc->has_nvdisplay) {
2195		value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2196			DSC_OBUF_UF_INT;
2197		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2198
2199		value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2200			DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
2201			HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
2202			REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
2203			VBLANK_INT | FRAME_END_INT;
2204		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2205
2206		value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
2207			FRAME_END_INT;
2208		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2209
2210		value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
2211		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2212
2213		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
2214	} else {
2215		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2216			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2217		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2218
2219		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2220			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2221		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2222
2223		/* initialize timer */
2224		value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
2225			WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
2226		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
2227
2228		value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
2229			WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
2230		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
2231
2232		value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2233			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2234		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2235
2236		value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2237			WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2238		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2239	}
2240
2241	if (dc->soc->supports_background_color)
2242		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
2243	else
2244		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
2245
2246	/* apply pixel clock changes */
2247	if (!dc->soc->has_nvdisplay) {
2248		value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;
2249		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
2250	}
2251
2252	/* program display mode */
2253	tegra_dc_set_timings(dc, mode);
2254
2255	/* interlacing isn't supported yet, so disable it */
2256	if (dc->soc->supports_interlacing) {
2257		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
2258		value &= ~INTERLACE_ENABLE;
2259		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
2260	}
2261
2262	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
2263	value &= ~DISP_CTRL_MODE_MASK;
2264	value |= DISP_CTRL_MODE_C_DISPLAY;
2265	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
2266
2267	if (!dc->soc->has_nvdisplay) {
2268		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2269		value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2270			 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
2271		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2272	}
2273
2274	/* enable underflow reporting and display red for missing pixels */
2275	if (dc->soc->has_nvdisplay) {
2276		value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
2277		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
2278	}
2279
2280	if (dc->rgb) {
2281		/* XXX: parameterize? */
2282		value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
2283		tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
2284	}
2285
2286	tegra_dc_commit(dc);
2287
2288	drm_crtc_vblank_on(crtc);
2289}
2290
2291static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
2292				    struct drm_atomic_state *state)
2293{
2294	unsigned long flags;
2295
2296	tegra_crtc_update_memory_bandwidth(crtc, state, true);
2297
2298	if (crtc->state->event) {
2299		spin_lock_irqsave(&crtc->dev->event_lock, flags);
2300
2301		if (drm_crtc_vblank_get(crtc) != 0)
2302			drm_crtc_send_vblank_event(crtc, crtc->state->event);
2303		else
2304			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
2305
2306		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2307
2308		crtc->state->event = NULL;
2309	}
2310}
2311
2312static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2313				    struct drm_atomic_state *state)
2314{
2315	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2316									  crtc);
2317	struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2318	struct tegra_dc *dc = to_tegra_dc(crtc);
2319	u32 value;
2320
2321	value = dc_state->planes << 8 | GENERAL_UPDATE;
2322	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2323	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2324
2325	value = dc_state->planes | GENERAL_ACT_REQ;
2326	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2327	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2328}
2329
2330static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
2331{
2332	const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
2333	const struct drm_format_info *fmt = state->fb->format;
2334	unsigned int src_w = drm_rect_width(&state->src) >> 16;
2335	unsigned int dst_w = drm_rect_width(&state->dst);
2336
2337	if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2338		return false;
2339
2340	if (soc->supports_cursor)
2341		return true;
2342
2343	if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
2344		return false;
2345
2346	return true;
2347}
2348
2349static unsigned long
2350tegra_plane_overlap_mask(struct drm_crtc_state *state,
2351			 const struct drm_plane_state *plane_state)
2352{
2353	const struct drm_plane_state *other_state;
2354	const struct tegra_plane *tegra;
2355	unsigned long overlap_mask = 0;
2356	struct drm_plane *plane;
2357	struct drm_rect rect;
2358
2359	if (!plane_state->visible || !plane_state->fb)
2360		return 0;
2361
2362	/*
2363	 * Data-prefetch FIFO will easily help to overcome temporal memory
2364	 * pressure if other plane overlaps with the cursor plane.
2365	 */
2366	if (tegra_plane_is_cursor(plane_state))
2367		return 0;
2368
2369	drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2370		rect = plane_state->dst;
2371
2372		tegra = to_tegra_plane(other_state->plane);
2373
2374		if (!other_state->visible || !other_state->fb)
2375			continue;
2376
2377		/*
2378		 * Ignore cursor plane overlaps because it's not practical to
2379		 * assume that it contributes to the bandwidth in overlapping
2380		 * area if window width is small.
2381		 */
2382		if (tegra_plane_is_cursor(other_state))
2383			continue;
2384
2385		if (drm_rect_intersect(&rect, &other_state->dst))
2386			overlap_mask |= BIT(tegra->index);
2387	}
2388
2389	return overlap_mask;
2390}
2391
2392static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
2393						 struct drm_atomic_state *state)
2394{
2395	ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
2396	u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
2397	bool all_planes_overlap_simultaneously = true;
2398	const struct tegra_plane_state *tegra_state;
2399	const struct drm_plane_state *plane_state;
2400	struct tegra_dc *dc = to_tegra_dc(crtc);
2401	struct drm_crtc_state *new_state;
2402	struct tegra_plane *tegra;
2403	struct drm_plane *plane;
2404
2405	/*
2406	 * The nv-display uses shared planes.  The algorithm below assumes
2407	 * maximum 3 planes per-CRTC, this assumption isn't applicable to
2408	 * the nv-display.  Note that T124 support has additional windows,
2409	 * but currently they aren't supported by the driver.
2410	 */
2411	if (dc->soc->has_nvdisplay)
2412		return 0;
2413
2414	new_state = drm_atomic_get_new_crtc_state(state, crtc);
2415
2416	/*
2417	 * For overlapping planes pixel's data is fetched for each plane at
2418	 * the same time, hence bandwidths are accumulated in this case.
2419	 * This needs to be taken into account for calculating total bandwidth
2420	 * consumed by all planes.
2421	 *
2422	 * Here we get the overlapping state of each plane, which is a
2423	 * bitmask of plane indices telling with what planes there is an
2424	 * overlap. Note that bitmask[plane] includes BIT(plane) in order
2425	 * to make further code nicer and simpler.
2426	 */
2427	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2428		tegra_state = to_const_tegra_plane_state(plane_state);
2429		tegra = to_tegra_plane(plane);
2430
2431		if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
2432			return -EINVAL;
2433
2434		plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
2435		mask = tegra_plane_overlap_mask(new_state, plane_state);
2436		overlap_mask[tegra->index] = mask;
2437
2438		if (hweight_long(mask) != 3)
2439			all_planes_overlap_simultaneously = false;
2440	}
2441
2442	/*
2443	 * Then we calculate maximum bandwidth of each plane state.
2444	 * The bandwidth includes the plane BW + BW of the "simultaneously"
2445	 * overlapping planes, where "simultaneously" means areas where DC
2446	 * fetches from the planes simultaneously during of scan-out process.
2447	 *
2448	 * For example, if plane A overlaps with planes B and C, but B and C
2449	 * don't overlap, then the peak bandwidth will be either in area where
2450	 * A-and-B or A-and-C planes overlap.
2451	 *
2452	 * The plane_peak_bw[] contains peak memory bandwidth values of
2453	 * each plane, this information is needed by interconnect provider
2454	 * in order to set up latency allowance based on the peak BW, see
2455	 * tegra_crtc_update_memory_bandwidth().
2456	 */
2457	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2458		u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
2459
2460		/*
2461		 * Note that plane's atomic check doesn't touch the
2462		 * total_peak_memory_bandwidth of enabled plane, hence the
2463		 * current state contains the old bandwidth state from the
2464		 * previous CRTC commit.
2465		 */
2466		tegra_state = to_const_tegra_plane_state(plane_state);
2467		tegra = to_tegra_plane(plane);
2468
2469		for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
2470			if (i == tegra->index)
2471				continue;
2472
2473			if (all_planes_overlap_simultaneously)
2474				overlap_bw += plane_peak_bw[i];
2475			else
2476				overlap_bw = max(overlap_bw, plane_peak_bw[i]);
2477		}
2478
2479		new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
2480		old_peak_bw = tegra_state->total_peak_memory_bandwidth;
2481
2482		/*
2483		 * If plane's peak bandwidth changed (for example plane isn't
2484		 * overlapped anymore) and plane isn't in the atomic state,
2485		 * then add plane to the state in order to have the bandwidth
2486		 * updated.
2487		 */
2488		if (old_peak_bw != new_peak_bw) {
2489			struct tegra_plane_state *new_tegra_state;
2490			struct drm_plane_state *new_plane_state;
2491
2492			new_plane_state = drm_atomic_get_plane_state(state, plane);
2493			if (IS_ERR(new_plane_state))
2494				return PTR_ERR(new_plane_state);
2495
2496			new_tegra_state = to_tegra_plane_state(new_plane_state);
2497			new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
2498		}
2499	}
2500
2501	return 0;
2502}
2503
2504static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
2505				   struct drm_atomic_state *state)
2506{
2507	int err;
2508
2509	err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
2510	if (err)
2511		return err;
2512
2513	return 0;
2514}
2515
2516void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
2517				   struct drm_atomic_state *state)
2518{
2519	/*
2520	 * Display bandwidth is allowed to go down only once hardware state
2521	 * is known to be armed, i.e. state was committed and VBLANK event
2522	 * received.
2523	 */
2524	tegra_crtc_update_memory_bandwidth(crtc, state, false);
2525}
2526
2527static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2528	.atomic_check = tegra_crtc_atomic_check,
2529	.atomic_begin = tegra_crtc_atomic_begin,
2530	.atomic_flush = tegra_crtc_atomic_flush,
2531	.atomic_enable = tegra_crtc_atomic_enable,
2532	.atomic_disable = tegra_crtc_atomic_disable,
2533};
2534
2535static irqreturn_t tegra_dc_irq(int irq, void *data)
2536{
2537	struct tegra_dc *dc = data;
2538	unsigned long status;
2539
2540	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2541	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2542
2543	if (status & FRAME_END_INT) {
2544		/*
2545		dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2546		*/
2547		dc->stats.frames_total++;
2548		dc->stats.frames++;
2549	}
2550
2551	if (status & VBLANK_INT) {
2552		/*
2553		dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2554		*/
2555		drm_crtc_handle_vblank(&dc->base);
2556		dc->stats.vblank_total++;
2557		dc->stats.vblank++;
2558	}
2559
2560	if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2561		/*
2562		dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2563		*/
2564		dc->stats.underflow_total++;
2565		dc->stats.underflow++;
2566	}
2567
2568	if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2569		/*
2570		dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2571		*/
2572		dc->stats.overflow_total++;
2573		dc->stats.overflow++;
2574	}
2575
2576	if (status & HEAD_UF_INT) {
2577		dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2578		dc->stats.underflow_total++;
2579		dc->stats.underflow++;
2580	}
2581
2582	return IRQ_HANDLED;
2583}
2584
2585static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2586{
2587	unsigned int i;
2588
2589	if (!dc->soc->wgrps)
2590		return true;
2591
2592	for (i = 0; i < dc->soc->num_wgrps; i++) {
2593		const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2594
2595		if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2596			return true;
2597	}
2598
2599	return false;
2600}
2601
2602static int tegra_dc_early_init(struct host1x_client *client)
2603{
2604	struct drm_device *drm = dev_get_drvdata(client->host);
2605	struct tegra_drm *tegra = drm->dev_private;
2606
2607	tegra->num_crtcs++;
2608
2609	return 0;
2610}
2611
2612static int tegra_dc_init(struct host1x_client *client)
2613{
2614	struct drm_device *drm = dev_get_drvdata(client->host);
2615	unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2616	struct tegra_dc *dc = host1x_client_to_dc(client);
2617	struct tegra_drm *tegra = drm->dev_private;
2618	struct drm_plane *primary = NULL;
2619	struct drm_plane *cursor = NULL;
2620	int err;
2621
2622	/*
2623	 * DC has been reset by now, so VBLANK syncpoint can be released
2624	 * for general use.
2625	 */
2626	host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2627
2628	/*
2629	 * XXX do not register DCs with no window groups because we cannot
2630	 * assign a primary plane to them, which in turn will cause KMS to
2631	 * crash.
2632	 */
2633	if (!tegra_dc_has_window_groups(dc))
2634		return 0;
2635
2636	/*
2637	 * Set the display hub as the host1x client parent for the display
2638	 * controller. This is needed for the runtime reference counting that
2639	 * ensures the display hub is always powered when any of the display
2640	 * controllers are.
2641	 */
2642	if (dc->soc->has_nvdisplay)
2643		client->parent = &tegra->hub->client;
2644
2645	dc->syncpt = host1x_syncpt_request(client, flags);
2646	if (!dc->syncpt)
2647		dev_warn(dc->dev, "failed to allocate syncpoint\n");
2648
2649	err = host1x_client_iommu_attach(client);
2650	if (err < 0 && err != -ENODEV) {
2651		dev_err(client->dev, "failed to attach to domain: %d\n", err);
2652		return err;
2653	}
2654
2655	if (dc->soc->wgrps)
2656		primary = tegra_dc_add_shared_planes(drm, dc);
2657	else
2658		primary = tegra_dc_add_planes(drm, dc);
2659
2660	if (IS_ERR(primary)) {
2661		err = PTR_ERR(primary);
2662		goto cleanup;
2663	}
2664
2665	if (dc->soc->supports_cursor) {
2666		cursor = tegra_dc_cursor_plane_create(drm, dc);
2667		if (IS_ERR(cursor)) {
2668			err = PTR_ERR(cursor);
2669			goto cleanup;
2670		}
2671	} else {
2672		/* dedicate one overlay to mouse cursor */
2673		cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2674		if (IS_ERR(cursor)) {
2675			err = PTR_ERR(cursor);
2676			goto cleanup;
2677		}
2678	}
2679
2680	err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2681					&tegra_crtc_funcs, NULL);
2682	if (err < 0)
2683		goto cleanup;
2684
2685	drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2686
2687	/*
2688	 * Keep track of the minimum pitch alignment across all display
2689	 * controllers.
2690	 */
2691	if (dc->soc->pitch_align > tegra->pitch_align)
2692		tegra->pitch_align = dc->soc->pitch_align;
2693
2694	/* track maximum resolution */
2695	if (dc->soc->has_nvdisplay)
2696		drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2697	else
2698		drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2699
2700	err = tegra_dc_rgb_init(drm, dc);
2701	if (err < 0 && err != -ENODEV) {
2702		dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2703		goto cleanup;
2704	}
2705
2706	err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2707			       dev_name(dc->dev), dc);
2708	if (err < 0) {
2709		dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2710			err);
2711		goto cleanup;
2712	}
2713
2714	/*
2715	 * Inherit the DMA parameters (such as maximum segment size) from the
2716	 * parent host1x device.
2717	 */
2718	client->dev->dma_parms = client->host->dma_parms;
2719
2720	return 0;
2721
2722cleanup:
2723	if (!IS_ERR_OR_NULL(cursor))
2724		drm_plane_cleanup(cursor);
2725
2726	if (!IS_ERR(primary))
2727		drm_plane_cleanup(primary);
2728
2729	host1x_client_iommu_detach(client);
2730	host1x_syncpt_put(dc->syncpt);
2731
2732	return err;
2733}
2734
2735static int tegra_dc_exit(struct host1x_client *client)
2736{
2737	struct tegra_dc *dc = host1x_client_to_dc(client);
2738	int err;
2739
2740	if (!tegra_dc_has_window_groups(dc))
2741		return 0;
2742
2743	/* avoid a dangling pointer just in case this disappears */
2744	client->dev->dma_parms = NULL;
2745
2746	devm_free_irq(dc->dev, dc->irq, dc);
2747
2748	err = tegra_dc_rgb_exit(dc);
2749	if (err) {
2750		dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2751		return err;
2752	}
2753
2754	host1x_client_iommu_detach(client);
2755	host1x_syncpt_put(dc->syncpt);
2756
2757	return 0;
2758}
2759
2760static int tegra_dc_late_exit(struct host1x_client *client)
2761{
2762	struct drm_device *drm = dev_get_drvdata(client->host);
2763	struct tegra_drm *tegra = drm->dev_private;
2764
2765	tegra->num_crtcs--;
2766
2767	return 0;
2768}
2769
2770static int tegra_dc_runtime_suspend(struct host1x_client *client)
2771{
2772	struct tegra_dc *dc = host1x_client_to_dc(client);
2773	struct device *dev = client->dev;
2774	int err;
2775
2776	err = reset_control_assert(dc->rst);
2777	if (err < 0) {
2778		dev_err(dev, "failed to assert reset: %d\n", err);
2779		return err;
2780	}
2781
2782	if (dc->soc->has_powergate)
2783		tegra_powergate_power_off(dc->powergate);
2784
2785	clk_disable_unprepare(dc->clk);
2786	pm_runtime_put_sync(dev);
2787
2788	return 0;
2789}
2790
2791static int tegra_dc_runtime_resume(struct host1x_client *client)
2792{
2793	struct tegra_dc *dc = host1x_client_to_dc(client);
2794	struct device *dev = client->dev;
2795	int err;
2796
2797	err = pm_runtime_resume_and_get(dev);
2798	if (err < 0) {
2799		dev_err(dev, "failed to get runtime PM: %d\n", err);
2800		return err;
2801	}
2802
2803	if (dc->soc->has_powergate) {
2804		err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2805							dc->rst);
2806		if (err < 0) {
2807			dev_err(dev, "failed to power partition: %d\n", err);
2808			goto put_rpm;
2809		}
2810	} else {
2811		err = clk_prepare_enable(dc->clk);
2812		if (err < 0) {
2813			dev_err(dev, "failed to enable clock: %d\n", err);
2814			goto put_rpm;
2815		}
2816
2817		err = reset_control_deassert(dc->rst);
2818		if (err < 0) {
2819			dev_err(dev, "failed to deassert reset: %d\n", err);
2820			goto disable_clk;
2821		}
2822	}
2823
2824	return 0;
2825
2826disable_clk:
2827	clk_disable_unprepare(dc->clk);
2828put_rpm:
2829	pm_runtime_put_sync(dev);
2830	return err;
2831}
2832
2833static const struct host1x_client_ops dc_client_ops = {
2834	.early_init = tegra_dc_early_init,
2835	.init = tegra_dc_init,
2836	.exit = tegra_dc_exit,
2837	.late_exit = tegra_dc_late_exit,
2838	.suspend = tegra_dc_runtime_suspend,
2839	.resume = tegra_dc_runtime_resume,
2840};
2841
2842static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2843	.supports_background_color = false,
2844	.supports_interlacing = false,
2845	.supports_cursor = false,
2846	.supports_block_linear = false,
2847	.supports_sector_layout = false,
2848	.has_legacy_blending = true,
2849	.pitch_align = 8,
2850	.has_powergate = false,
2851	.coupled_pm = true,
2852	.has_nvdisplay = false,
2853	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2854	.primary_formats = tegra20_primary_formats,
2855	.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2856	.overlay_formats = tegra20_overlay_formats,
2857	.modifiers = tegra20_modifiers,
2858	.has_win_a_without_filters = true,
2859	.has_win_b_vfilter_mem_client = true,
2860	.has_win_c_without_vert_filter = true,
2861	.plane_tiled_memory_bandwidth_x2 = false,
2862	.has_pll_d2_out0 = false,
2863};
2864
2865static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2866	.supports_background_color = false,
2867	.supports_interlacing = false,
2868	.supports_cursor = false,
2869	.supports_block_linear = false,
2870	.supports_sector_layout = false,
2871	.has_legacy_blending = true,
2872	.pitch_align = 8,
2873	.has_powergate = false,
2874	.coupled_pm = false,
2875	.has_nvdisplay = false,
2876	.num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2877	.primary_formats = tegra20_primary_formats,
2878	.num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2879	.overlay_formats = tegra20_overlay_formats,
2880	.modifiers = tegra20_modifiers,
2881	.has_win_a_without_filters = false,
2882	.has_win_b_vfilter_mem_client = true,
2883	.has_win_c_without_vert_filter = false,
2884	.plane_tiled_memory_bandwidth_x2 = true,
2885	.has_pll_d2_out0 = true,
2886};
2887
2888static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2889	.supports_background_color = false,
2890	.supports_interlacing = false,
2891	.supports_cursor = false,
2892	.supports_block_linear = false,
2893	.supports_sector_layout = false,
2894	.has_legacy_blending = true,
2895	.pitch_align = 64,
2896	.has_powergate = true,
2897	.coupled_pm = false,
2898	.has_nvdisplay = false,
2899	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2900	.primary_formats = tegra114_primary_formats,
2901	.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2902	.overlay_formats = tegra114_overlay_formats,
2903	.modifiers = tegra20_modifiers,
2904	.has_win_a_without_filters = false,
2905	.has_win_b_vfilter_mem_client = false,
2906	.has_win_c_without_vert_filter = false,
2907	.plane_tiled_memory_bandwidth_x2 = true,
2908	.has_pll_d2_out0 = true,
2909};
2910
2911static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2912	.supports_background_color = true,
2913	.supports_interlacing = true,
2914	.supports_cursor = true,
2915	.supports_block_linear = true,
2916	.supports_sector_layout = false,
2917	.has_legacy_blending = false,
2918	.pitch_align = 64,
2919	.has_powergate = true,
2920	.coupled_pm = false,
2921	.has_nvdisplay = false,
2922	.num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2923	.primary_formats = tegra124_primary_formats,
2924	.num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2925	.overlay_formats = tegra124_overlay_formats,
2926	.modifiers = tegra124_modifiers,
2927	.has_win_a_without_filters = false,
2928	.has_win_b_vfilter_mem_client = false,
2929	.has_win_c_without_vert_filter = false,
2930	.plane_tiled_memory_bandwidth_x2 = false,
2931	.has_pll_d2_out0 = true,
2932};
2933
2934static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2935	.supports_background_color = true,
2936	.supports_interlacing = true,
2937	.supports_cursor = true,
2938	.supports_block_linear = true,
2939	.supports_sector_layout = false,
2940	.has_legacy_blending = false,
2941	.pitch_align = 64,
2942	.has_powergate = true,
2943	.coupled_pm = false,
2944	.has_nvdisplay = false,
2945	.num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2946	.primary_formats = tegra114_primary_formats,
2947	.num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2948	.overlay_formats = tegra114_overlay_formats,
2949	.modifiers = tegra124_modifiers,
2950	.has_win_a_without_filters = false,
2951	.has_win_b_vfilter_mem_client = false,
2952	.has_win_c_without_vert_filter = false,
2953	.plane_tiled_memory_bandwidth_x2 = false,
2954	.has_pll_d2_out0 = true,
2955};
2956
2957static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2958	{
2959		.index = 0,
2960		.dc = 0,
2961		.windows = (const unsigned int[]) { 0 },
2962		.num_windows = 1,
2963	}, {
2964		.index = 1,
2965		.dc = 1,
2966		.windows = (const unsigned int[]) { 1 },
2967		.num_windows = 1,
2968	}, {
2969		.index = 2,
2970		.dc = 1,
2971		.windows = (const unsigned int[]) { 2 },
2972		.num_windows = 1,
2973	}, {
2974		.index = 3,
2975		.dc = 2,
2976		.windows = (const unsigned int[]) { 3 },
2977		.num_windows = 1,
2978	}, {
2979		.index = 4,
2980		.dc = 2,
2981		.windows = (const unsigned int[]) { 4 },
2982		.num_windows = 1,
2983	}, {
2984		.index = 5,
2985		.dc = 2,
2986		.windows = (const unsigned int[]) { 5 },
2987		.num_windows = 1,
2988	},
2989};
2990
2991static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2992	.supports_background_color = true,
2993	.supports_interlacing = true,
2994	.supports_cursor = true,
2995	.supports_block_linear = true,
2996	.supports_sector_layout = false,
2997	.has_legacy_blending = false,
2998	.pitch_align = 64,
2999	.has_powergate = false,
3000	.coupled_pm = false,
3001	.has_nvdisplay = true,
3002	.wgrps = tegra186_dc_wgrps,
3003	.num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
3004	.plane_tiled_memory_bandwidth_x2 = false,
3005	.has_pll_d2_out0 = false,
3006};
3007
3008static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
3009	{
3010		.index = 0,
3011		.dc = 0,
3012		.windows = (const unsigned int[]) { 0 },
3013		.num_windows = 1,
3014	}, {
3015		.index = 1,
3016		.dc = 1,
3017		.windows = (const unsigned int[]) { 1 },
3018		.num_windows = 1,
3019	}, {
3020		.index = 2,
3021		.dc = 1,
3022		.windows = (const unsigned int[]) { 2 },
3023		.num_windows = 1,
3024	}, {
3025		.index = 3,
3026		.dc = 2,
3027		.windows = (const unsigned int[]) { 3 },
3028		.num_windows = 1,
3029	}, {
3030		.index = 4,
3031		.dc = 2,
3032		.windows = (const unsigned int[]) { 4 },
3033		.num_windows = 1,
3034	}, {
3035		.index = 5,
3036		.dc = 2,
3037		.windows = (const unsigned int[]) { 5 },
3038		.num_windows = 1,
3039	},
3040};
3041
3042static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
3043	.supports_background_color = true,
3044	.supports_interlacing = true,
3045	.supports_cursor = true,
3046	.supports_block_linear = true,
3047	.supports_sector_layout = true,
3048	.has_legacy_blending = false,
3049	.pitch_align = 64,
3050	.has_powergate = false,
3051	.coupled_pm = false,
3052	.has_nvdisplay = true,
3053	.wgrps = tegra194_dc_wgrps,
3054	.num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
3055	.plane_tiled_memory_bandwidth_x2 = false,
3056	.has_pll_d2_out0 = false,
3057};
3058
3059static const struct of_device_id tegra_dc_of_match[] = {
3060	{
3061		.compatible = "nvidia,tegra194-dc",
3062		.data = &tegra194_dc_soc_info,
3063	}, {
3064		.compatible = "nvidia,tegra186-dc",
3065		.data = &tegra186_dc_soc_info,
3066	}, {
3067		.compatible = "nvidia,tegra210-dc",
3068		.data = &tegra210_dc_soc_info,
3069	}, {
3070		.compatible = "nvidia,tegra124-dc",
3071		.data = &tegra124_dc_soc_info,
3072	}, {
3073		.compatible = "nvidia,tegra114-dc",
3074		.data = &tegra114_dc_soc_info,
3075	}, {
3076		.compatible = "nvidia,tegra30-dc",
3077		.data = &tegra30_dc_soc_info,
3078	}, {
3079		.compatible = "nvidia,tegra20-dc",
3080		.data = &tegra20_dc_soc_info,
3081	}, {
3082		/* sentinel */
3083	}
3084};
3085MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
3086
3087static int tegra_dc_parse_dt(struct tegra_dc *dc)
3088{
3089	struct device_node *np;
3090	u32 value = 0;
3091	int err;
3092
3093	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
3094	if (err < 0) {
3095		dev_err(dc->dev, "missing \"nvidia,head\" property\n");
3096
3097		/*
3098		 * If the nvidia,head property isn't present, try to find the
3099		 * correct head number by looking up the position of this
3100		 * display controller's node within the device tree. Assuming
3101		 * that the nodes are ordered properly in the DTS file and
3102		 * that the translation into a flattened device tree blob
3103		 * preserves that ordering this will actually yield the right
3104		 * head number.
3105		 *
3106		 * If those assumptions don't hold, this will still work for
3107		 * cases where only a single display controller is used.
3108		 */
3109		for_each_matching_node(np, tegra_dc_of_match) {
3110			if (np == dc->dev->of_node) {
3111				of_node_put(np);
3112				break;
3113			}
3114
3115			value++;
3116		}
3117	}
3118
3119	dc->pipe = value;
3120
3121	return 0;
3122}
3123
3124static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
3125{
3126	struct tegra_dc *dc = dev_get_drvdata(dev);
3127	unsigned int pipe = (unsigned long)(void *)data;
3128
3129	return dc->pipe == pipe;
3130}
3131
3132static int tegra_dc_couple(struct tegra_dc *dc)
3133{
3134	/*
3135	 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
3136	 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
3137	 * POWER_CONTROL registers during CRTC enabling.
3138	 */
3139	if (dc->soc->coupled_pm && dc->pipe == 1) {
3140		struct device *companion;
3141		struct tegra_dc *parent;
3142
3143		companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
3144					       tegra_dc_match_by_pipe);
3145		if (!companion)
3146			return -EPROBE_DEFER;
3147
3148		parent = dev_get_drvdata(companion);
3149		dc->client.parent = &parent->client;
3150
3151		dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
3152		put_device(companion);
3153	}
3154
3155	return 0;
3156}
3157
3158static int tegra_dc_init_opp_table(struct tegra_dc *dc)
3159{
3160	struct tegra_core_opp_params opp_params = {};
3161	int err;
3162
3163	err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
3164	if (err && err != -ENODEV)
3165		return err;
3166
3167	if (err)
3168		dc->has_opp_table = false;
3169	else
3170		dc->has_opp_table = true;
3171
3172	return 0;
3173}
3174
3175static int tegra_dc_probe(struct platform_device *pdev)
3176{
3177	u64 dma_mask = dma_get_mask(pdev->dev.parent);
3178	struct tegra_dc *dc;
3179	int err;
3180
3181	err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
3182	if (err < 0) {
3183		dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
3184		return err;
3185	}
3186
3187	dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
3188	if (!dc)
3189		return -ENOMEM;
3190
3191	dc->soc = of_device_get_match_data(&pdev->dev);
3192
3193	INIT_LIST_HEAD(&dc->list);
3194	dc->dev = &pdev->dev;
3195
3196	err = tegra_dc_parse_dt(dc);
3197	if (err < 0)
3198		return err;
3199
3200	err = tegra_dc_couple(dc);
3201	if (err < 0)
3202		return err;
3203
3204	dc->clk = devm_clk_get(&pdev->dev, NULL);
3205	if (IS_ERR(dc->clk)) {
3206		dev_err(&pdev->dev, "failed to get clock\n");
3207		return PTR_ERR(dc->clk);
3208	}
3209
3210	dc->rst = devm_reset_control_get(&pdev->dev, "dc");
3211	if (IS_ERR(dc->rst)) {
3212		dev_err(&pdev->dev, "failed to get reset\n");
3213		return PTR_ERR(dc->rst);
3214	}
3215
3216	/* assert reset and disable clock */
3217	err = clk_prepare_enable(dc->clk);
3218	if (err < 0)
3219		return err;
3220
3221	usleep_range(2000, 4000);
3222
3223	err = reset_control_assert(dc->rst);
3224	if (err < 0) {
3225		clk_disable_unprepare(dc->clk);
3226		return err;
3227	}
3228
3229	usleep_range(2000, 4000);
3230
3231	clk_disable_unprepare(dc->clk);
3232
3233	if (dc->soc->has_powergate) {
3234		if (dc->pipe == 0)
3235			dc->powergate = TEGRA_POWERGATE_DIS;
3236		else
3237			dc->powergate = TEGRA_POWERGATE_DISB;
3238
3239		tegra_powergate_power_off(dc->powergate);
3240	}
3241
3242	err = tegra_dc_init_opp_table(dc);
3243	if (err < 0)
3244		return err;
3245
3246	dc->regs = devm_platform_ioremap_resource(pdev, 0);
3247	if (IS_ERR(dc->regs))
3248		return PTR_ERR(dc->regs);
3249
3250	dc->irq = platform_get_irq(pdev, 0);
3251	if (dc->irq < 0)
3252		return -ENXIO;
3253
3254	err = tegra_dc_rgb_probe(dc);
3255	if (err < 0 && err != -ENODEV)
3256		return dev_err_probe(&pdev->dev, err,
3257				     "failed to probe RGB output\n");
3258
3259	platform_set_drvdata(pdev, dc);
3260	pm_runtime_enable(&pdev->dev);
3261
3262	INIT_LIST_HEAD(&dc->client.list);
3263	dc->client.ops = &dc_client_ops;
3264	dc->client.dev = &pdev->dev;
3265
3266	err = host1x_client_register(&dc->client);
3267	if (err < 0) {
3268		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3269			err);
3270		goto disable_pm;
3271	}
3272
3273	return 0;
3274
3275disable_pm:
3276	pm_runtime_disable(&pdev->dev);
3277	tegra_dc_rgb_remove(dc);
3278
3279	return err;
3280}
3281
3282static void tegra_dc_remove(struct platform_device *pdev)
3283{
3284	struct tegra_dc *dc = platform_get_drvdata(pdev);
3285
3286	host1x_client_unregister(&dc->client);
3287
3288	tegra_dc_rgb_remove(dc);
3289
3290	pm_runtime_disable(&pdev->dev);
3291}
3292
3293struct platform_driver tegra_dc_driver = {
3294	.driver = {
3295		.name = "tegra-dc",
3296		.of_match_table = tegra_dc_of_match,
3297	},
3298	.probe = tegra_dc_probe,
3299	.remove = tegra_dc_remove,
3300};