sun4i_tcon_dclk.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2016 Free Electrons
  4 * Copyright (C) 2016 NextThing Co
  5 *
  6 * Maxime Ripard <maxime.ripard@free-electrons.com>
  7 */
  8
  9#include <linux/clk-provider.h>
 10#include <linux/regmap.h>
 11
 12#include "sun4i_tcon.h"
 13#include "sun4i_tcon_dclk.h"
 14
 15struct sun4i_dclk {
 16	struct clk_hw		hw;
 17	struct regmap		*regmap;
 18	struct sun4i_tcon	*tcon;
 19};
 20
 21static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
 22{
 23	return container_of(hw, struct sun4i_dclk, hw);
 24}
 25
 26static void sun4i_dclk_disable(struct clk_hw *hw)
 27{
 28	struct sun4i_dclk *dclk = hw_to_dclk(hw);
 29
 30	regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
 31			   BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
 32}
 33
 34static int sun4i_dclk_enable(struct clk_hw *hw)
 35{
 36	struct sun4i_dclk *dclk = hw_to_dclk(hw);
 37
 38	return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
 39				  BIT(SUN4I_TCON0_DCLK_GATE_BIT),
 40				  BIT(SUN4I_TCON0_DCLK_GATE_BIT));
 41}
 42
 43static int sun4i_dclk_is_enabled(struct clk_hw *hw)
 44{
 45	struct sun4i_dclk *dclk = hw_to_dclk(hw);
 46	u32 val;
 47
 48	regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
 49
 50	return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
 51}
 52
 53static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
 54					    unsigned long parent_rate)
 55{
 56	struct sun4i_dclk *dclk = hw_to_dclk(hw);
 57	u32 val;
 58
 59	regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
 60
 61	val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
 62	val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
 63
 64	if (!val)
 65		val = 1;
 66
 67	return parent_rate / val;
 68}
 69
 70static int sun4i_dclk_determine_rate(struct clk_hw *hw,
 71				     struct clk_rate_request *req)
 72{
 73	struct sun4i_dclk *dclk = hw_to_dclk(hw);
 74	struct sun4i_tcon *tcon = dclk->tcon;
 75	unsigned long best_parent = 0;
 76	u8 best_div = 1;
 77	int i;
 78
 79	for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) {
 80		u64 ideal = (u64)req->rate * i;
 81		unsigned long rounded;
 82
 83		/*
 84		 * ideal has overflowed the max value that can be stored in an
 85		 * unsigned long, and every clk operation we might do on a
 86		 * truncated u64 value will give us incorrect results.
 87		 * Let's just stop there since bigger dividers will result in
 88		 * the same overflow issue.
 89		 */
 90		if (ideal > ULONG_MAX)
 91			goto out;
 92
 93		rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
 94					    ideal);
 95
 96		if (rounded == ideal) {
 97			best_parent = rounded;
 98			best_div = i;
 99			goto out;
100		}
101
102		if (abs(req->rate - rounded / i) <
103		    abs(req->rate - best_parent / best_div)) {
104			best_parent = rounded;
105			best_div = i;
106		}
107	}
108
109out:
110	req->best_parent_rate = best_parent;
111
112	req->rate = best_parent / best_div;
113
114	return 0;
115}
116
117static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
118			       unsigned long parent_rate)
119{
120	struct sun4i_dclk *dclk = hw_to_dclk(hw);
121	u8 div = parent_rate / rate;
122
123	return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
124				  GENMASK(6, 0), div);
125}
126
127static int sun4i_dclk_get_phase(struct clk_hw *hw)
128{
129	struct sun4i_dclk *dclk = hw_to_dclk(hw);
130	u32 val;
131
132	regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
133
134	val >>= 28;
135	val &= 3;
136
137	return val * 120;
138}
139
140static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
141{
142	struct sun4i_dclk *dclk = hw_to_dclk(hw);
143	u32 val = degrees / 120;
144
145	val <<= 28;
146
147	regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
148			   GENMASK(29, 28),
149			   val);
150
151	return 0;
152}
153
154static const struct clk_ops sun4i_dclk_ops = {
155	.disable	= sun4i_dclk_disable,
156	.enable		= sun4i_dclk_enable,
157	.is_enabled	= sun4i_dclk_is_enabled,
158
159	.recalc_rate	= sun4i_dclk_recalc_rate,
160	.determine_rate = sun4i_dclk_determine_rate,
161	.set_rate	= sun4i_dclk_set_rate,
162
163	.get_phase	= sun4i_dclk_get_phase,
164	.set_phase	= sun4i_dclk_set_phase,
165};
166
167int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
168{
169	const char *clk_name, *parent_name;
170	struct clk_init_data init;
171	struct sun4i_dclk *dclk;
172	int ret;
173
174	parent_name = __clk_get_name(tcon->sclk0);
175	ret = of_property_read_string_index(dev->of_node,
176					    "clock-output-names", 0,
177					    &clk_name);
178	if (ret)
179		return ret;
180
181	dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
182	if (!dclk)
183		return -ENOMEM;
184	dclk->tcon = tcon;
185
186	init.name = clk_name;
187	init.ops = &sun4i_dclk_ops;
188	init.parent_names = &parent_name;
189	init.num_parents = 1;
190	init.flags = CLK_SET_RATE_PARENT;
191
192	dclk->regmap = tcon->regs;
193	dclk->hw.init = &init;
194
195	tcon->dclk = clk_register(dev, &dclk->hw);
196	if (IS_ERR(tcon->dclk))
197		return PTR_ERR(tcon->dclk);
198
199	return 0;
200}
201EXPORT_SYMBOL(sun4i_dclk_create);
202
203int sun4i_dclk_free(struct sun4i_tcon *tcon)
204{
205	clk_unregister(tcon->dclk);
206	return 0;
207}
208EXPORT_SYMBOL(sun4i_dclk_free);