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sun4i_hdmi_enc.c
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linux-6.19.14/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8#include <linux/clk.h> 9#include <linux/component.h> 10#include <linux/i2c.h> 11#include <linux/iopoll.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/pm_runtime.h> 16#include <linux/regmap.h> 17#include <linux/reset.h> 18 19#include <drm/drm_atomic.h> 20#include <drm/drm_atomic_helper.h> 21#include <drm/drm_edid.h> 22#include <drm/drm_encoder.h> 23#include <drm/drm_of.h> 24#include <drm/drm_panel.h> 25#include <drm/drm_print.h> 26#include <drm/drm_probe_helper.h> 27#include <drm/drm_simple_kms_helper.h> 28 29#include <drm/display/drm_hdmi_helper.h> 30#include <drm/display/drm_hdmi_state_helper.h> 31 32#include "sun4i_backend.h" 33#include "sun4i_crtc.h" 34#include "sun4i_drv.h" 35#include "sun4i_hdmi.h" 36 37#define drm_encoder_to_sun4i_hdmi(e) \ 38 container_of_const(e, struct sun4i_hdmi, encoder) 39 40#define drm_connector_to_sun4i_hdmi(c) \ 41 container_of_const(c, struct sun4i_hdmi, connector) 42 43static int sun4i_hdmi_write_infoframe(struct drm_connector *connector, 44 enum hdmi_infoframe_type type, 45 const u8 *buffer, size_t len) 46{ 47 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 48 int i; 49 50 if (type != HDMI_INFOFRAME_TYPE_AVI) { 51 drm_err(connector->dev, 52 "Unsupported infoframe type: %u\n", type); 53 return 0; 54 } 55 56 for (i = 0; i < len; i++) 57 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 58 59 return 0; 60 61} 62 63static void sun4i_hdmi_disable(struct drm_encoder *encoder, 64 struct drm_atomic_state *state) 65{ 66 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 67 u32 val; 68 69 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 70 71 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 72 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 73 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 74 75 clk_disable_unprepare(hdmi->tmds_clk); 76} 77 78static void sun4i_hdmi_enable(struct drm_encoder *encoder, 79 struct drm_atomic_state *state) 80{ 81 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 82 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 83 struct drm_connector *connector = &hdmi->connector; 84 struct drm_display_info *display = &connector->display_info; 85 struct drm_connector_state *conn_state = 86 drm_atomic_get_new_connector_state(state, connector); 87 unsigned long long tmds_rate = conn_state->hdmi.tmds_char_rate; 88 unsigned int x, y; 89 u32 val = 0; 90 91 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 92 93 clk_set_rate(hdmi->mod_clk, tmds_rate); 94 clk_set_rate(hdmi->tmds_clk, tmds_rate); 95 96 /* Set input sync enable */ 97 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 98 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 99 100 /* 101 * Setup output pad (?) controls 102 * 103 * This is done here instead of at probe/bind time because 104 * the controller seems to toggle some of the bits on its own. 105 * 106 * We can't just initialize the register there, we need to 107 * protect the clock bits that have already been read out and 108 * cached by the clock framework. 109 */ 110 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 111 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 112 val |= hdmi->variant->pad_ctrl1_init_val; 113 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 114 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 115 116 /* Setup timing registers */ 117 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 118 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 119 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 120 121 x = mode->htotal - mode->hsync_start; 122 y = mode->vtotal - mode->vsync_start; 123 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 124 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 125 126 x = mode->hsync_start - mode->hdisplay; 127 y = mode->vsync_start - mode->vdisplay; 128 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 129 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 130 131 x = mode->hsync_end - mode->hsync_start; 132 y = mode->vsync_end - mode->vsync_start; 133 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 134 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 135 136 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 137 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 138 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 139 140 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 141 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 142 143 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 144 145 clk_prepare_enable(hdmi->tmds_clk); 146 147 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 148 149 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 150 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 151 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 152 153 val = SUN4I_HDMI_VID_CTRL_ENABLE; 154 if (display->is_hdmi) 155 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 156 157 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 158} 159 160static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 161 .atomic_disable = sun4i_hdmi_disable, 162 .atomic_enable = sun4i_hdmi_enable, 163}; 164 165static enum drm_mode_status 166sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector, 167 const struct drm_display_mode *mode, 168 unsigned long long clock) 169{ 170 const struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 171 unsigned long diff = div_u64(clock, 200); /* +-0.5% allowed by HDMI spec */ 172 long rounded_rate; 173 174 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 175 return MODE_BAD; 176 177 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 178 if (clock > 165000000) 179 return MODE_CLOCK_HIGH; 180 181 rounded_rate = clk_round_rate(hdmi->tmds_clk, clock); 182 if (rounded_rate > 0 && 183 max_t(unsigned long, rounded_rate, clock) - 184 min_t(unsigned long, rounded_rate, clock) < diff) 185 return MODE_OK; 186 187 return MODE_NOCLOCK; 188} 189 190static int sun4i_hdmi_get_modes(struct drm_connector *connector) 191{ 192 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 193 const struct drm_edid *drm_edid; 194 int ret; 195 196 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c); 197 198 drm_edid_connector_update(connector, drm_edid); 199 cec_s_phys_addr(hdmi->cec_adap, 200 connector->display_info.source_physical_address, false); 201 202 if (!drm_edid) 203 return 0; 204 205 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 206 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 207 208 209 ret = drm_edid_connector_add_modes(connector); 210 drm_edid_free(drm_edid); 211 212 return ret; 213} 214 215static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 216{ 217 struct device_node *phandle, *remote; 218 struct i2c_adapter *ddc; 219 220 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 221 if (!remote) 222 return ERR_PTR(-EINVAL); 223 224 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 225 of_node_put(remote); 226 if (!phandle) 227 return ERR_PTR(-ENODEV); 228 229 ddc = of_get_i2c_adapter_by_node(phandle); 230 of_node_put(phandle); 231 if (!ddc) 232 return ERR_PTR(-EPROBE_DEFER); 233 234 return ddc; 235} 236 237static const struct drm_connector_hdmi_funcs sun4i_hdmi_hdmi_connector_funcs = { 238 .tmds_char_rate_valid = sun4i_hdmi_connector_clock_valid, 239 .write_infoframe = sun4i_hdmi_write_infoframe, 240}; 241 242static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 243 .atomic_check = drm_atomic_helper_connector_hdmi_check, 244 .mode_valid = drm_hdmi_connector_mode_valid, 245 .get_modes = sun4i_hdmi_get_modes, 246}; 247 248static enum drm_connector_status 249sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 250{ 251 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 252 unsigned long reg; 253 254 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 255 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 256 cec_phys_addr_invalidate(hdmi->cec_adap); 257 return connector_status_disconnected; 258 } 259 260 return connector_status_connected; 261} 262 263static void sun4i_hdmi_connector_reset(struct drm_connector *connector) 264{ 265 drm_atomic_helper_connector_reset(connector); 266 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 267} 268 269static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 270 .detect = sun4i_hdmi_connector_detect, 271 .fill_modes = drm_helper_probe_single_connector_modes, 272 .reset = sun4i_hdmi_connector_reset, 273 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 274 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 275}; 276 277#ifdef CONFIG_DRM_SUN4I_HDMI_CEC 278static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 279{ 280 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 281 282 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 283} 284 285static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 286{ 287 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 288 289 /* Start driving the CEC pin low */ 290 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 291} 292 293static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 294{ 295 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 296 297 /* 298 * Stop driving the CEC pin, the pull up will take over 299 * unless another CEC device is driving the pin low. 300 */ 301 writel(0, hdmi->base + SUN4I_HDMI_CEC); 302} 303 304static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 305 .read = sun4i_hdmi_cec_pin_read, 306 .low = sun4i_hdmi_cec_pin_low, 307 .high = sun4i_hdmi_cec_pin_high, 308}; 309#endif 310 311#define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 312#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 313 314/* Only difference from sun5i is AMP is 4 instead of 6 */ 315static const struct sun4i_hdmi_variant sun4i_variant = { 316 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 317 SUN4I_HDMI_PAD_CTRL0_CKEN | 318 SUN4I_HDMI_PAD_CTRL0_PWENG | 319 SUN4I_HDMI_PAD_CTRL0_PWEND | 320 SUN4I_HDMI_PAD_CTRL0_PWENC | 321 SUN4I_HDMI_PAD_CTRL0_LDODEN | 322 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 323 SUN4I_HDMI_PAD_CTRL0_BIASEN, 324 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 325 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 326 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 327 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 328 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 329 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 330 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 331 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 332 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 333 SUN4I_HDMI_PLL_CTRL_CS(7) | 334 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 335 SUN4I_HDMI_PLL_CTRL_S(7) | 336 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 337 SUN4I_HDMI_PLL_CTRL_SDIV2 | 338 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 339 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 340 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 341 SUN4I_HDMI_PLL_CTRL_BWS | 342 SUN4I_HDMI_PLL_CTRL_PLL_EN, 343 344 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 345 .ddc_clk_pre_divider = 2, 346 .ddc_clk_m_offset = 1, 347 348 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 349 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 350 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 351 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 352 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 353 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 354 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 355 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 356 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 357 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 358 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 359 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 360 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 361 362 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 363 .ddc_fifo_has_dir = true, 364}; 365 366static const struct sun4i_hdmi_variant sun5i_variant = { 367 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 368 SUN4I_HDMI_PAD_CTRL0_CKEN | 369 SUN4I_HDMI_PAD_CTRL0_PWENG | 370 SUN4I_HDMI_PAD_CTRL0_PWEND | 371 SUN4I_HDMI_PAD_CTRL0_PWENC | 372 SUN4I_HDMI_PAD_CTRL0_LDODEN | 373 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 374 SUN4I_HDMI_PAD_CTRL0_BIASEN, 375 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 376 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 377 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 378 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 379 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 380 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 381 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 382 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 383 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 384 SUN4I_HDMI_PLL_CTRL_CS(7) | 385 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 386 SUN4I_HDMI_PLL_CTRL_S(7) | 387 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 388 SUN4I_HDMI_PLL_CTRL_SDIV2 | 389 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 390 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 391 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 392 SUN4I_HDMI_PLL_CTRL_BWS | 393 SUN4I_HDMI_PLL_CTRL_PLL_EN, 394 395 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 396 .ddc_clk_pre_divider = 2, 397 .ddc_clk_m_offset = 1, 398 399 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 400 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 401 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 402 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 403 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 404 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 405 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 406 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 407 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 408 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 409 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 410 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 411 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 412 413 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 414 .ddc_fifo_has_dir = true, 415}; 416 417static const struct sun4i_hdmi_variant sun6i_variant = { 418 .has_ddc_parent_clk = true, 419 .has_reset_control = true, 420 .pad_ctrl0_init_val = 0xff | 421 SUN4I_HDMI_PAD_CTRL0_TXEN | 422 SUN4I_HDMI_PAD_CTRL0_CKEN | 423 SUN4I_HDMI_PAD_CTRL0_PWENG | 424 SUN4I_HDMI_PAD_CTRL0_PWEND | 425 SUN4I_HDMI_PAD_CTRL0_PWENC | 426 SUN4I_HDMI_PAD_CTRL0_LDODEN | 427 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 428 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 429 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 430 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 431 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 432 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 433 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 434 SUN4I_HDMI_PAD_CTRL1_PWSDT | 435 SUN4I_HDMI_PAD_CTRL1_PWSCK | 436 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 437 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 438 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 439 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 440 SUN4I_HDMI_PLL_CTRL_CS(3) | 441 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 442 SUN4I_HDMI_PLL_CTRL_S(4) | 443 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 444 SUN4I_HDMI_PLL_CTRL_SDIV2 | 445 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 446 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 447 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 448 SUN4I_HDMI_PLL_CTRL_PLL_EN, 449 450 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 451 .ddc_clk_pre_divider = 1, 452 .ddc_clk_m_offset = 2, 453 454 .tmds_clk_div_offset = 1, 455 456 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 457 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 458 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 459 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 460 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 461 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 462 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 463 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 464 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 465 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 466 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 467 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 468 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 469 470 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 471 .ddc_fifo_thres_incl = true, 472}; 473 474static const struct regmap_config sun4i_hdmi_regmap_config = { 475 .reg_bits = 32, 476 .val_bits = 32, 477 .reg_stride = 4, 478 .max_register = 0x580, 479}; 480 481static int sun4i_hdmi_bind(struct device *dev, struct device *master, 482 void *data) 483{ 484 struct platform_device *pdev = to_platform_device(dev); 485 struct drm_device *drm = data; 486 struct cec_connector_info conn_info; 487 struct sun4i_drv *drv = drm->dev_private; 488 struct sun4i_hdmi *hdmi; 489 u32 reg; 490 int ret; 491 492 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 493 if (!hdmi) 494 return -ENOMEM; 495 dev_set_drvdata(dev, hdmi); 496 hdmi->dev = dev; 497 hdmi->drv = drv; 498 499 hdmi->variant = of_device_get_match_data(dev); 500 if (!hdmi->variant) 501 return -EINVAL; 502 503 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 504 if (IS_ERR(hdmi->base)) { 505 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 506 return PTR_ERR(hdmi->base); 507 } 508 509 if (hdmi->variant->has_reset_control) { 510 hdmi->reset = devm_reset_control_get(dev, NULL); 511 if (IS_ERR(hdmi->reset)) { 512 dev_err(dev, "Couldn't get the HDMI reset control\n"); 513 return PTR_ERR(hdmi->reset); 514 } 515 516 ret = reset_control_deassert(hdmi->reset); 517 if (ret) { 518 dev_err(dev, "Couldn't deassert HDMI reset\n"); 519 return ret; 520 } 521 } 522 523 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 524 if (IS_ERR(hdmi->bus_clk)) { 525 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 526 ret = PTR_ERR(hdmi->bus_clk); 527 goto err_assert_reset; 528 } 529 clk_prepare_enable(hdmi->bus_clk); 530 531 hdmi->mod_clk = devm_clk_get(dev, "mod"); 532 if (IS_ERR(hdmi->mod_clk)) { 533 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 534 ret = PTR_ERR(hdmi->mod_clk); 535 goto err_disable_bus_clk; 536 } 537 clk_prepare_enable(hdmi->mod_clk); 538 539 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 540 if (IS_ERR(hdmi->pll0_clk)) { 541 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 542 ret = PTR_ERR(hdmi->pll0_clk); 543 goto err_disable_mod_clk; 544 } 545 546 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 547 if (IS_ERR(hdmi->pll1_clk)) { 548 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 549 ret = PTR_ERR(hdmi->pll1_clk); 550 goto err_disable_mod_clk; 551 } 552 553 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 554 &sun4i_hdmi_regmap_config); 555 if (IS_ERR(hdmi->regmap)) { 556 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 557 ret = PTR_ERR(hdmi->regmap); 558 goto err_disable_mod_clk; 559 } 560 561 ret = sun4i_tmds_create(hdmi); 562 if (ret) { 563 dev_err(dev, "Couldn't create the TMDS clock\n"); 564 goto err_disable_mod_clk; 565 } 566 567 if (hdmi->variant->has_ddc_parent_clk) { 568 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 569 if (IS_ERR(hdmi->ddc_parent_clk)) { 570 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 571 ret = PTR_ERR(hdmi->ddc_parent_clk); 572 goto err_disable_mod_clk; 573 } 574 } else { 575 hdmi->ddc_parent_clk = hdmi->tmds_clk; 576 } 577 578 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 579 580 writel(hdmi->variant->pad_ctrl0_init_val, 581 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 582 583 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 584 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 585 reg |= hdmi->variant->pll_ctrl_init_val; 586 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 587 588 ret = sun4i_hdmi_i2c_create(dev, hdmi); 589 if (ret) { 590 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 591 goto err_disable_mod_clk; 592 } 593 594 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 595 if (IS_ERR(hdmi->ddc_i2c)) { 596 ret = PTR_ERR(hdmi->ddc_i2c); 597 if (ret == -ENODEV) 598 hdmi->ddc_i2c = NULL; 599 else 600 goto err_del_i2c_adapter; 601 } 602 603 drm_encoder_helper_add(&hdmi->encoder, 604 &sun4i_hdmi_helper_funcs); 605 ret = drm_simple_encoder_init(drm, &hdmi->encoder, 606 DRM_MODE_ENCODER_TMDS); 607 if (ret) { 608 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 609 goto err_put_ddc_i2c; 610 } 611 612 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 613 dev->of_node); 614 if (!hdmi->encoder.possible_crtcs) { 615 ret = -EPROBE_DEFER; 616 goto err_put_ddc_i2c; 617 } 618 619#ifdef CONFIG_DRM_SUN4I_HDMI_CEC 620 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 621 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 622 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 623 if (ret < 0) 624 goto err_cleanup_connector; 625 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 626 hdmi->base + SUN4I_HDMI_CEC); 627#endif 628 629 drm_connector_helper_add(&hdmi->connector, 630 &sun4i_hdmi_connector_helper_funcs); 631 ret = drmm_connector_hdmi_init(drm, &hdmi->connector, 632 /* 633 * NOTE: Those are likely to be 634 * wrong, but I couldn't find the 635 * actual ones in the BSP. 636 */ 637 "AW", "HDMI", 638 &sun4i_hdmi_connector_funcs, 639 &sun4i_hdmi_hdmi_connector_funcs, 640 DRM_MODE_CONNECTOR_HDMIA, 641 hdmi->ddc_i2c, 642 BIT(HDMI_COLORSPACE_RGB), 643 8); 644 if (ret) { 645 dev_err(dev, 646 "Couldn't initialise the HDMI connector\n"); 647 goto err_cleanup_connector; 648 } 649 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 650 cec_s_conn_info(hdmi->cec_adap, &conn_info); 651 652 /* There is no HPD interrupt, so we need to poll the controller */ 653 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 654 DRM_CONNECTOR_POLL_DISCONNECT; 655 656 ret = cec_register_adapter(hdmi->cec_adap, dev); 657 if (ret < 0) 658 goto err_cleanup_connector; 659 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 660 661 return 0; 662 663err_cleanup_connector: 664 cec_delete_adapter(hdmi->cec_adap); 665 drm_encoder_cleanup(&hdmi->encoder); 666err_put_ddc_i2c: 667 i2c_put_adapter(hdmi->ddc_i2c); 668err_del_i2c_adapter: 669 i2c_del_adapter(hdmi->i2c); 670err_disable_mod_clk: 671 clk_disable_unprepare(hdmi->mod_clk); 672err_disable_bus_clk: 673 clk_disable_unprepare(hdmi->bus_clk); 674err_assert_reset: 675 reset_control_assert(hdmi->reset); 676 return ret; 677} 678 679static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 680 void *data) 681{ 682 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 683 684 cec_unregister_adapter(hdmi->cec_adap); 685 i2c_del_adapter(hdmi->i2c); 686 i2c_put_adapter(hdmi->ddc_i2c); 687 clk_disable_unprepare(hdmi->mod_clk); 688 clk_disable_unprepare(hdmi->bus_clk); 689} 690 691static const struct component_ops sun4i_hdmi_ops = { 692 .bind = sun4i_hdmi_bind, 693 .unbind = sun4i_hdmi_unbind, 694}; 695 696static int sun4i_hdmi_probe(struct platform_device *pdev) 697{ 698 return component_add(&pdev->dev, &sun4i_hdmi_ops); 699} 700 701static void sun4i_hdmi_remove(struct platform_device *pdev) 702{ 703 component_del(&pdev->dev, &sun4i_hdmi_ops); 704} 705 706static const struct of_device_id sun4i_hdmi_of_table[] = { 707 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 708 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 709 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 710 { } 711}; 712MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 713 714static struct platform_driver sun4i_hdmi_driver = { 715 .probe = sun4i_hdmi_probe, 716 .remove = sun4i_hdmi_remove, 717 .driver = { 718 .name = "sun4i-hdmi", 719 .of_match_table = sun4i_hdmi_of_table, 720 }, 721}; 722module_platform_driver(sun4i_hdmi_driver); 723 724MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 725MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 726MODULE_LICENSE("GPL");
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