sun4i_frontend.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2017 Free Electrons
  4 * Maxime Ripard <maxime.ripard@free-electrons.com>
  5 */
  6
  7#include <linux/clk.h>
  8#include <linux/component.h>
  9#include <linux/module.h>
 10#include <linux/of.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm_runtime.h>
 13#include <linux/regmap.h>
 14#include <linux/reset.h>
 15
 16#include <drm/drm_device.h>
 17#include <drm/drm_fb_dma_helper.h>
 18#include <drm/drm_fourcc.h>
 19#include <drm/drm_framebuffer.h>
 20#include <drm/drm_gem_dma_helper.h>
 21#include <drm/drm_plane.h>
 22#include <drm/drm_print.h>
 23
 24#include "sun4i_drv.h"
 25#include "sun4i_frontend.h"
 26
 27static const u32 sun4i_frontend_vert_coef[32] = {
 28	0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
 29	0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
 30	0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
 31	0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
 32	0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
 33	0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
 34	0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
 35	0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
 36};
 37
 38static const u32 sun4i_frontend_horz_coef[64] = {
 39	0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
 40	0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
 41	0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
 42	0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
 43	0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
 44	0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
 45	0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
 46	0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
 47	0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
 48	0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
 49	0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
 50	0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
 51	0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
 52	0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
 53	0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
 54	0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
 55};
 56
 57/*
 58 * These coefficients are taken from the A33 BSP from Allwinner.
 59 *
 60 * The first three values of each row are coded as 13-bit signed fixed-point
 61 * numbers, with 10 bits for the fractional part. The fourth value is a
 62 * constant coded as a 14-bit signed fixed-point number with 4 bits for the
 63 * fractional part.
 64 *
 65 * The values in table order give the following colorspace translation:
 66 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
 67 * R = 1.164 * Y + 1.596 * V - 222
 68 * B = 1.164 * Y + 2.018 * U + 276
 69 *
 70 * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
 71 * following the BT601 spec.
 72 */
 73const u32 sunxi_bt601_yuv2rgb_coef[12] = {
 74	0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
 75	0x000004a7, 0x00000000, 0x00000662, 0x00003211,
 76	0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
 77};
 78EXPORT_SYMBOL(sunxi_bt601_yuv2rgb_coef);
 79
 80static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend)
 81{
 82	int i;
 83
 84	if (frontend->data->has_coef_access_ctrl)
 85		regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
 86				  SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL,
 87				  SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL);
 88
 89	for (i = 0; i < 32; i++) {
 90		regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i),
 91			     sun4i_frontend_horz_coef[2 * i]);
 92		regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i),
 93			     sun4i_frontend_horz_coef[2 * i]);
 94		regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i),
 95			     sun4i_frontend_horz_coef[2 * i + 1]);
 96		regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i),
 97			     sun4i_frontend_horz_coef[2 * i + 1]);
 98		regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTCOEF_REG(i),
 99			     sun4i_frontend_vert_coef[i]);
100		regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTCOEF_REG(i),
101			     sun4i_frontend_vert_coef[i]);
102	}
103
104	if (frontend->data->has_coef_rdy)
105		regmap_write_bits(frontend->regs,
106				  SUN4I_FRONTEND_FRM_CTRL_REG,
107				  SUN4I_FRONTEND_FRM_CTRL_COEF_RDY,
108				  SUN4I_FRONTEND_FRM_CTRL_COEF_RDY);
109}
110
111int sun4i_frontend_init(struct sun4i_frontend *frontend)
112{
113	return pm_runtime_get_sync(frontend->dev);
114}
115EXPORT_SYMBOL(sun4i_frontend_init);
116
117void sun4i_frontend_exit(struct sun4i_frontend *frontend)
118{
119	pm_runtime_put(frontend->dev);
120}
121EXPORT_SYMBOL(sun4i_frontend_exit);
122
123static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)
124{
125	switch (fmt) {
126	case DRM_FORMAT_YVU411:
127	case DRM_FORMAT_YVU420:
128	case DRM_FORMAT_YVU422:
129	case DRM_FORMAT_YVU444:
130		return true;
131
132	default:
133		return false;
134	}
135}
136
137static bool sun4i_frontend_format_supports_tiling(uint32_t fmt)
138{
139	switch (fmt) {
140	case DRM_FORMAT_NV12:
141	case DRM_FORMAT_NV16:
142	case DRM_FORMAT_NV21:
143	case DRM_FORMAT_NV61:
144	case DRM_FORMAT_YUV411:
145	case DRM_FORMAT_YUV420:
146	case DRM_FORMAT_YUV422:
147	case DRM_FORMAT_YVU420:
148	case DRM_FORMAT_YVU422:
149	case DRM_FORMAT_YVU411:
150		return true;
151
152	default:
153		return false;
154	}
155}
156
157void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
158				  struct drm_plane *plane)
159{
160	struct drm_plane_state *state = plane->state;
161	struct drm_framebuffer *fb = state->fb;
162	unsigned int strides[3] = {};
163
164	dma_addr_t dma_addr;
165	bool swap;
166
167	if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
168		unsigned int width = state->src_w >> 16;
169		unsigned int offset;
170
171		strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]);
172
173		/*
174		 * The X1 offset is the offset to the bottom-right point in the
175		 * end tile, which is the final pixel (at offset width - 1)
176		 * within the end tile (with a 32-byte mask).
177		 */
178		offset = (width - 1) & (32 - 1);
179
180		regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG,
181			     SUN4I_FRONTEND_TB_OFF_X1(offset));
182
183		if (fb->format->num_planes > 1) {
184			strides[1] =
185				SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]);
186
187			regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG,
188				     SUN4I_FRONTEND_TB_OFF_X1(offset));
189		}
190
191		if (fb->format->num_planes > 2) {
192			strides[2] =
193				SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]);
194
195			regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG,
196				     SUN4I_FRONTEND_TB_OFF_X1(offset));
197		}
198	} else {
199		strides[0] = fb->pitches[0];
200
201		if (fb->format->num_planes > 1)
202			strides[1] = fb->pitches[1];
203
204		if (fb->format->num_planes > 2)
205			strides[2] = fb->pitches[2];
206	}
207
208	/* Set the line width */
209	DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]);
210	regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG,
211		     strides[0]);
212
213	if (fb->format->num_planes > 1)
214		regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG,
215			     strides[1]);
216
217	if (fb->format->num_planes > 2)
218		regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG,
219			     strides[2]);
220
221	/* Some planar formats require chroma channel swapping by hand. */
222	swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);
223
224	/* Set the physical address of the buffer in memory */
225	dma_addr = drm_fb_dma_get_gem_addr(fb, state, 0);
226	DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &dma_addr);
227	regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, dma_addr);
228
229	if (fb->format->num_planes > 1) {
230		dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 2 : 1);
231		DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n",
232				 &dma_addr);
233		regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
234			     dma_addr);
235	}
236
237	if (fb->format->num_planes > 2) {
238		dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 1 : 2);
239		DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n",
240				 &dma_addr);
241		regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
242			     dma_addr);
243	}
244}
245EXPORT_SYMBOL(sun4i_frontend_update_buffer);
246
247static int
248sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info *format,
249				       u32 *val)
250{
251	if (!format->is_yuv)
252		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB;
253	else if (drm_format_info_is_yuv_sampling_411(format))
254		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411;
255	else if (drm_format_info_is_yuv_sampling_420(format))
256		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420;
257	else if (drm_format_info_is_yuv_sampling_422(format))
258		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422;
259	else if (drm_format_info_is_yuv_sampling_444(format))
260		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444;
261	else
262		return -EINVAL;
263
264	return 0;
265}
266
267static int
268sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info *format,
269					uint64_t modifier, u32 *val)
270{
271	bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED);
272
273	switch (format->num_planes) {
274	case 1:
275		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED;
276		return 0;
277
278	case 2:
279		*val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR
280			     : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR;
281		return 0;
282
283	case 3:
284		*val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR
285			     : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR;
286		return 0;
287
288	default:
289		return -EINVAL;
290	}
291}
292
293static int
294sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info *format,
295					    u32 *val)
296{
297	/* Planar formats have an explicit input sequence. */
298	if (drm_format_info_is_yuv_planar(format)) {
299		*val = 0;
300		return 0;
301	}
302
303	switch (format->format) {
304	case DRM_FORMAT_BGRX8888:
305		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX;
306		return 0;
307
308	case DRM_FORMAT_NV12:
309		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
310		return 0;
311
312	case DRM_FORMAT_NV16:
313		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
314		return 0;
315
316	case DRM_FORMAT_NV21:
317		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
318		return 0;
319
320	case DRM_FORMAT_NV61:
321		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
322		return 0;
323
324	case DRM_FORMAT_UYVY:
325		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY;
326		return 0;
327
328	case DRM_FORMAT_VYUY:
329		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY;
330		return 0;
331
332	case DRM_FORMAT_XRGB8888:
333		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB;
334		return 0;
335
336	case DRM_FORMAT_YUYV:
337		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV;
338		return 0;
339
340	case DRM_FORMAT_YVYU:
341		*val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU;
342		return 0;
343
344	default:
345		return -EINVAL;
346	}
347}
348
349static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val)
350{
351	switch (fmt) {
352	case DRM_FORMAT_BGRX8888:
353		*val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888;
354		return 0;
355
356	case DRM_FORMAT_XRGB8888:
357		*val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888;
358		return 0;
359
360	default:
361		return -EINVAL;
362	}
363}
364
365static const uint32_t sun4i_frontend_formats[] = {
366	DRM_FORMAT_BGRX8888,
367	DRM_FORMAT_NV12,
368	DRM_FORMAT_NV16,
369	DRM_FORMAT_NV21,
370	DRM_FORMAT_NV61,
371	DRM_FORMAT_UYVY,
372	DRM_FORMAT_VYUY,
373	DRM_FORMAT_XRGB8888,
374	DRM_FORMAT_YUV411,
375	DRM_FORMAT_YUV420,
376	DRM_FORMAT_YUV422,
377	DRM_FORMAT_YUV444,
378	DRM_FORMAT_YUYV,
379	DRM_FORMAT_YVU411,
380	DRM_FORMAT_YVU420,
381	DRM_FORMAT_YVU422,
382	DRM_FORMAT_YVU444,
383	DRM_FORMAT_YVYU,
384};
385
386bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier)
387{
388	unsigned int i;
389
390	if (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED)
391		return sun4i_frontend_format_supports_tiling(fmt);
392	else if (modifier != DRM_FORMAT_MOD_LINEAR)
393		return false;
394
395	for (i = 0; i < ARRAY_SIZE(sun4i_frontend_formats); i++)
396		if (sun4i_frontend_formats[i] == fmt)
397			return true;
398
399	return false;
400}
401EXPORT_SYMBOL(sun4i_frontend_format_is_supported);
402
403int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
404				  struct drm_plane *plane, uint32_t out_fmt)
405{
406	struct drm_plane_state *state = plane->state;
407	struct drm_framebuffer *fb = state->fb;
408	const struct drm_format_info *format = fb->format;
409	uint64_t modifier = fb->modifier;
410	unsigned int ch1_phase_idx;
411	u32 out_fmt_val;
412	u32 in_fmt_val, in_mod_val, in_ps_val;
413	unsigned int i;
414	u32 bypass;
415	int ret;
416
417	ret = sun4i_frontend_drm_format_to_input_fmt(format, &in_fmt_val);
418	if (ret) {
419		DRM_DEBUG_DRIVER("Invalid input format\n");
420		return ret;
421	}
422
423	ret = sun4i_frontend_drm_format_to_input_mode(format, modifier,
424						      &in_mod_val);
425	if (ret) {
426		DRM_DEBUG_DRIVER("Invalid input mode\n");
427		return ret;
428	}
429
430	ret = sun4i_frontend_drm_format_to_input_sequence(format, &in_ps_val);
431	if (ret) {
432		DRM_DEBUG_DRIVER("Invalid pixel sequence\n");
433		return ret;
434	}
435
436	ret = sun4i_frontend_drm_format_to_output_fmt(out_fmt, &out_fmt_val);
437	if (ret) {
438		DRM_DEBUG_DRIVER("Invalid output format\n");
439		return ret;
440	}
441
442	/*
443	 * I have no idea what this does exactly, but it seems to be
444	 * related to the scaler FIR filter phase parameters.
445	 */
446	ch1_phase_idx = (format->num_planes > 1) ? 1 : 0;
447	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
448		     frontend->data->ch_phase[0]);
449	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
450		     frontend->data->ch_phase[ch1_phase_idx]);
451	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
452		     frontend->data->ch_phase[0]);
453	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
454		     frontend->data->ch_phase[ch1_phase_idx]);
455	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
456		     frontend->data->ch_phase[0]);
457	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
458		     frontend->data->ch_phase[ch1_phase_idx]);
459
460	/*
461	 * Checking the input format is sufficient since we currently only
462	 * support RGB output formats to the backend. If YUV output formats
463	 * ever get supported, an YUV input and output would require bypassing
464	 * the CSC engine too.
465	 */
466	if (format->is_yuv) {
467		/* Setup the CSC engine for YUV to RGB conversion. */
468		bypass = 0;
469
470		for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
471			regmap_write(frontend->regs,
472				     SUN4I_FRONTEND_CSC_COEF_REG(i),
473				     sunxi_bt601_yuv2rgb_coef[i]);
474	} else {
475		bypass = SUN4I_FRONTEND_BYPASS_CSC_EN;
476	}
477
478	regmap_update_bits(frontend->regs, SUN4I_FRONTEND_BYPASS_REG,
479			   SUN4I_FRONTEND_BYPASS_CSC_EN, bypass);
480
481	regmap_write(frontend->regs, SUN4I_FRONTEND_INPUT_FMT_REG,
482		     in_mod_val | in_fmt_val | in_ps_val);
483
484	/*
485	 * TODO: It look like the A31 and A80 at least will need the
486	 * bit 7 (ALPHA_EN) enabled when using a format with alpha (so
487	 * ARGB8888).
488	 */
489	regmap_write(frontend->regs, SUN4I_FRONTEND_OUTPUT_FMT_REG,
490		     out_fmt_val);
491
492	return 0;
493}
494EXPORT_SYMBOL(sun4i_frontend_update_formats);
495
496void sun4i_frontend_update_coord(struct sun4i_frontend *frontend,
497				 struct drm_plane *plane)
498{
499	struct drm_plane_state *state = plane->state;
500	struct drm_framebuffer *fb = state->fb;
501	uint32_t luma_width, luma_height;
502	uint32_t chroma_width, chroma_height;
503
504	/* Set height and width */
505	DRM_DEBUG_DRIVER("Frontend size W: %u H: %u\n",
506			 state->crtc_w, state->crtc_h);
507
508	luma_width = state->src_w >> 16;
509	luma_height = state->src_h >> 16;
510
511	chroma_width = DIV_ROUND_UP(luma_width, fb->format->hsub);
512	chroma_height = DIV_ROUND_UP(luma_height, fb->format->vsub);
513
514	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_INSIZE_REG,
515		     SUN4I_FRONTEND_INSIZE(luma_height, luma_width));
516	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_INSIZE_REG,
517		     SUN4I_FRONTEND_INSIZE(chroma_height, chroma_width));
518
519	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_OUTSIZE_REG,
520		     SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
521	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_OUTSIZE_REG,
522		     SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
523
524	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZFACT_REG,
525		     (luma_width << 16) / state->crtc_w);
526	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZFACT_REG,
527		     (chroma_width << 16) / state->crtc_w);
528
529	regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTFACT_REG,
530		     (luma_height << 16) / state->crtc_h);
531	regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTFACT_REG,
532		     (chroma_height << 16) / state->crtc_h);
533
534	regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
535			  SUN4I_FRONTEND_FRM_CTRL_REG_RDY,
536			  SUN4I_FRONTEND_FRM_CTRL_REG_RDY);
537}
538EXPORT_SYMBOL(sun4i_frontend_update_coord);
539
540int sun4i_frontend_enable(struct sun4i_frontend *frontend)
541{
542	regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
543			  SUN4I_FRONTEND_FRM_CTRL_FRM_START,
544			  SUN4I_FRONTEND_FRM_CTRL_FRM_START);
545
546	return 0;
547}
548EXPORT_SYMBOL(sun4i_frontend_enable);
549
550static const struct regmap_config sun4i_frontend_regmap_config = {
551	.reg_bits	= 32,
552	.val_bits	= 32,
553	.reg_stride	= 4,
554	.max_register	= 0x0a14,
555};
556
557static int sun4i_frontend_bind(struct device *dev, struct device *master,
558			 void *data)
559{
560	struct platform_device *pdev = to_platform_device(dev);
561	struct sun4i_frontend *frontend;
562	struct drm_device *drm = data;
563	struct sun4i_drv *drv = drm->dev_private;
564	void __iomem *regs;
565
566	frontend = devm_kzalloc(dev, sizeof(*frontend), GFP_KERNEL);
567	if (!frontend)
568		return -ENOMEM;
569
570	dev_set_drvdata(dev, frontend);
571	frontend->dev = dev;
572	frontend->node = dev->of_node;
573
574	frontend->data = of_device_get_match_data(dev);
575	if (!frontend->data)
576		return -ENODEV;
577
578	regs = devm_platform_ioremap_resource(pdev, 0);
579	if (IS_ERR(regs))
580		return PTR_ERR(regs);
581
582	frontend->regs = devm_regmap_init_mmio(dev, regs,
583					       &sun4i_frontend_regmap_config);
584	if (IS_ERR(frontend->regs)) {
585		dev_err(dev, "Couldn't create the frontend regmap\n");
586		return PTR_ERR(frontend->regs);
587	}
588
589	frontend->reset = devm_reset_control_get(dev, NULL);
590	if (IS_ERR(frontend->reset)) {
591		dev_err(dev, "Couldn't get our reset line\n");
592		return PTR_ERR(frontend->reset);
593	}
594
595	frontend->bus_clk = devm_clk_get(dev, "ahb");
596	if (IS_ERR(frontend->bus_clk)) {
597		dev_err(dev, "Couldn't get our bus clock\n");
598		return PTR_ERR(frontend->bus_clk);
599	}
600
601	frontend->mod_clk = devm_clk_get(dev, "mod");
602	if (IS_ERR(frontend->mod_clk)) {
603		dev_err(dev, "Couldn't get our mod clock\n");
604		return PTR_ERR(frontend->mod_clk);
605	}
606
607	frontend->ram_clk = devm_clk_get(dev, "ram");
608	if (IS_ERR(frontend->ram_clk)) {
609		dev_err(dev, "Couldn't get our ram clock\n");
610		return PTR_ERR(frontend->ram_clk);
611	}
612
613	list_add_tail(&frontend->list, &drv->frontend_list);
614	pm_runtime_enable(dev);
615
616	return 0;
617}
618
619static void sun4i_frontend_unbind(struct device *dev, struct device *master,
620			    void *data)
621{
622	struct sun4i_frontend *frontend = dev_get_drvdata(dev);
623
624	list_del(&frontend->list);
625	pm_runtime_force_suspend(dev);
626}
627
628static const struct component_ops sun4i_frontend_ops = {
629	.bind	= sun4i_frontend_bind,
630	.unbind	= sun4i_frontend_unbind,
631};
632
633static int sun4i_frontend_probe(struct platform_device *pdev)
634{
635	return component_add(&pdev->dev, &sun4i_frontend_ops);
636}
637
638static void sun4i_frontend_remove(struct platform_device *pdev)
639{
640	component_del(&pdev->dev, &sun4i_frontend_ops);
641}
642
643static int sun4i_frontend_runtime_resume(struct device *dev)
644{
645	struct sun4i_frontend *frontend = dev_get_drvdata(dev);
646	int ret;
647
648	clk_set_rate(frontend->mod_clk, 300000000);
649
650	clk_prepare_enable(frontend->bus_clk);
651	clk_prepare_enable(frontend->mod_clk);
652	clk_prepare_enable(frontend->ram_clk);
653
654	ret = reset_control_reset(frontend->reset);
655	if (ret) {
656		dev_err(dev, "Couldn't reset our device\n");
657		return ret;
658	}
659
660	regmap_update_bits(frontend->regs, SUN4I_FRONTEND_EN_REG,
661			   SUN4I_FRONTEND_EN_EN,
662			   SUN4I_FRONTEND_EN_EN);
663
664	sun4i_frontend_scaler_init(frontend);
665
666	return 0;
667}
668
669static int sun4i_frontend_runtime_suspend(struct device *dev)
670{
671	struct sun4i_frontend *frontend = dev_get_drvdata(dev);
672
673	clk_disable_unprepare(frontend->ram_clk);
674	clk_disable_unprepare(frontend->mod_clk);
675	clk_disable_unprepare(frontend->bus_clk);
676
677	reset_control_assert(frontend->reset);
678
679	return 0;
680}
681
682static const struct dev_pm_ops sun4i_frontend_pm_ops = {
683	.runtime_resume		= sun4i_frontend_runtime_resume,
684	.runtime_suspend	= sun4i_frontend_runtime_suspend,
685};
686
687static const struct sun4i_frontend_data sun4i_a10_frontend = {
688	.ch_phase		= { 0x000, 0xfc000 },
689	.has_coef_rdy		= true,
690};
691
692static const struct sun4i_frontend_data sun8i_a33_frontend = {
693	.ch_phase		= { 0x400, 0xfc400 },
694	.has_coef_access_ctrl	= true,
695};
696
697const struct of_device_id sun4i_frontend_of_table[] = {
698	{
699		.compatible = "allwinner,sun4i-a10-display-frontend",
700		.data = &sun4i_a10_frontend
701	},
702	{
703		.compatible = "allwinner,sun7i-a20-display-frontend",
704		.data = &sun4i_a10_frontend
705	},
706	{
707		.compatible = "allwinner,sun8i-a23-display-frontend",
708		.data = &sun8i_a33_frontend
709	},
710	{
711		.compatible = "allwinner,sun8i-a33-display-frontend",
712		.data = &sun8i_a33_frontend
713	},
714	{ }
715};
716EXPORT_SYMBOL(sun4i_frontend_of_table);
717MODULE_DEVICE_TABLE(of, sun4i_frontend_of_table);
718
719static struct platform_driver sun4i_frontend_driver = {
720	.probe		= sun4i_frontend_probe,
721	.remove		= sun4i_frontend_remove,
722	.driver		= {
723		.name		= "sun4i-frontend",
724		.of_match_table	= sun4i_frontend_of_table,
725		.pm		= &sun4i_frontend_pm_ops,
726	},
727};
728module_platform_driver(sun4i_frontend_driver);
729
730MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
731MODULE_DESCRIPTION("Allwinner A10 Display Engine Frontend Driver");
732MODULE_LICENSE("GPL");