sun4i_backend.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2015 Free Electrons
   4 * Copyright (C) 2015 NextThing Co
   5 *
   6 * Maxime Ripard <maxime.ripard@free-electrons.com>
   7 */
   8
   9#include <linux/component.h>
  10#include <linux/list.h>
  11#include <linux/module.h>
  12#include <linux/of_device.h>
  13#include <linux/of_graph.h>
  14#include <linux/dma-mapping.h>
  15#include <linux/platform_device.h>
  16#include <linux/reset.h>
  17
  18#include <drm/drm_atomic.h>
  19#include <drm/drm_atomic_helper.h>
  20#include <drm/drm_blend.h>
  21#include <drm/drm_crtc.h>
  22#include <drm/drm_fb_dma_helper.h>
  23#include <drm/drm_fourcc.h>
  24#include <drm/drm_framebuffer.h>
  25#include <drm/drm_gem_dma_helper.h>
  26#include <drm/drm_print.h>
  27#include <drm/drm_probe_helper.h>
  28
  29#include "sun4i_backend.h"
  30#include "sun4i_drv.h"
  31#include "sun4i_frontend.h"
  32#include "sun4i_layer.h"
  33#include "sunxi_engine.h"
  34
  35struct sun4i_backend_quirks {
  36	/* backend <-> TCON muxing selection done in backend */
  37	bool needs_output_muxing;
  38
  39	/* alpha at the lowest z position is not always supported */
  40	bool supports_lowest_plane_alpha;
  41};
  42
  43static const u32 sunxi_rgb2yuv_coef[12] = {
  44	0x00000107, 0x00000204, 0x00000064, 0x00000108,
  45	0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  46	0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  47};
  48
  49static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  50{
  51	int i;
  52
  53	DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
  54
  55	/* Set color correction */
  56	regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  57		     SUN4I_BACKEND_OCCTL_ENABLE);
  58
  59	for (i = 0; i < 12; i++)
  60		regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
  61			     sunxi_rgb2yuv_coef[i]);
  62}
  63
  64static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
  65{
  66	DRM_DEBUG_DRIVER("Disabling color correction\n");
  67
  68	/* Disable color correction */
  69	regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  70			   SUN4I_BACKEND_OCCTL_ENABLE, 0);
  71}
  72
  73static void sun4i_backend_commit(struct sunxi_engine *engine,
  74				 struct drm_crtc *crtc,
  75				 struct drm_atomic_state *state)
  76{
  77	DRM_DEBUG_DRIVER("Committing changes\n");
  78
  79	regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
  80		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
  81		     SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
  82}
  83
  84void sun4i_backend_layer_enable(struct sun4i_backend *backend,
  85				int layer, bool enable)
  86{
  87	u32 val;
  88
  89	DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
  90			 layer);
  91
  92	if (enable)
  93		val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
  94	else
  95		val = 0;
  96
  97	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
  98			   SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
  99}
 100
 101static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
 102{
 103	switch (format) {
 104	case DRM_FORMAT_ARGB8888:
 105		*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
 106		break;
 107
 108	case DRM_FORMAT_ARGB4444:
 109		*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 110		break;
 111
 112	case DRM_FORMAT_ARGB1555:
 113		*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 114		break;
 115
 116	case DRM_FORMAT_RGBA5551:
 117		*mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 118		break;
 119
 120	case DRM_FORMAT_RGBA4444:
 121		*mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 122		break;
 123
 124	case DRM_FORMAT_XRGB8888:
 125		*mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 126		break;
 127
 128	case DRM_FORMAT_RGB888:
 129		*mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 130		break;
 131
 132	case DRM_FORMAT_RGB565:
 133		*mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 134		break;
 135
 136	default:
 137		return -EINVAL;
 138	}
 139
 140	return 0;
 141}
 142
 143static const uint32_t sun4i_backend_formats[] = {
 144	DRM_FORMAT_ARGB1555,
 145	DRM_FORMAT_ARGB4444,
 146	DRM_FORMAT_ARGB8888,
 147	DRM_FORMAT_RGB565,
 148	DRM_FORMAT_RGB888,
 149	DRM_FORMAT_RGBA4444,
 150	DRM_FORMAT_RGBA5551,
 151	DRM_FORMAT_UYVY,
 152	DRM_FORMAT_VYUY,
 153	DRM_FORMAT_XRGB8888,
 154	DRM_FORMAT_YUYV,
 155	DRM_FORMAT_YVYU,
 156};
 157
 158bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier)
 159{
 160	unsigned int i;
 161
 162	if (modifier != DRM_FORMAT_MOD_LINEAR)
 163		return false;
 164
 165	for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++)
 166		if (sun4i_backend_formats[i] == fmt)
 167			return true;
 168
 169	return false;
 170}
 171
 172int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 173				     int layer, struct drm_plane *plane)
 174{
 175	struct drm_plane_state *state = plane->state;
 176
 177	DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 178
 179	/* Set height and width */
 180	DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 181			 state->crtc_w, state->crtc_h);
 182	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 183		     SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 184					   state->crtc_h));
 185
 186	/* Set base coordinates */
 187	DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 188			 state->crtc_x, state->crtc_y);
 189	regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 190		     SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 191					   state->crtc_y));
 192
 193	return 0;
 194}
 195
 196static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
 197					   int layer, struct drm_plane *plane)
 198{
 199	struct drm_plane_state *state = plane->state;
 200	struct drm_framebuffer *fb = state->fb;
 201	const struct drm_format_info *format = fb->format;
 202	const uint32_t fmt = format->format;
 203	u32 val = SUN4I_BACKEND_IYUVCTL_EN;
 204	int i;
 205
 206	for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 207		regmap_write(backend->engine.regs,
 208			     SUN4I_BACKEND_YGCOEF_REG(i),
 209			     sunxi_bt601_yuv2rgb_coef[i]);
 210
 211	/*
 212	 * We should do that only for a single plane, but the
 213	 * framebuffer's atomic_check has our back on this.
 214	 */
 215	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 216			   SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
 217			   SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
 218
 219	/* TODO: Add support for the multi-planar YUV formats */
 220	if (drm_format_info_is_yuv_packed(format) &&
 221	    drm_format_info_is_yuv_sampling_422(format))
 222		val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
 223	else
 224		DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt);
 225
 226	/*
 227	 * Allwinner seems to list the pixel sequence from right to left, while
 228	 * DRM lists it from left to right.
 229	 */
 230	switch (fmt) {
 231	case DRM_FORMAT_YUYV:
 232		val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
 233		break;
 234	case DRM_FORMAT_YVYU:
 235		val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
 236		break;
 237	case DRM_FORMAT_UYVY:
 238		val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
 239		break;
 240	case DRM_FORMAT_VYUY:
 241		val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
 242		break;
 243	default:
 244		DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
 245				 fmt);
 246	}
 247
 248	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
 249
 250	return 0;
 251}
 252
 253int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 254				       int layer, struct drm_plane *plane)
 255{
 256	struct drm_plane_state *state = plane->state;
 257	struct drm_framebuffer *fb = state->fb;
 258	u32 val;
 259	int ret;
 260
 261	/* Clear the YUV mode */
 262	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 263			   SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 264
 265	val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
 266	if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
 267		val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
 268	regmap_update_bits(backend->engine.regs,
 269			   SUN4I_BACKEND_ATTCTL_REG0(layer),
 270			   SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
 271			   SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
 272			   val);
 273
 274	if (fb->format->is_yuv)
 275		return sun4i_backend_update_yuv_format(backend, layer, plane);
 276
 277	ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
 278	if (ret) {
 279		DRM_DEBUG_DRIVER("Invalid format\n");
 280		return ret;
 281	}
 282
 283	regmap_update_bits(backend->engine.regs,
 284			   SUN4I_BACKEND_ATTCTL_REG1(layer),
 285			   SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 286
 287	return 0;
 288}
 289
 290int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
 291					int layer, uint32_t fmt)
 292{
 293	u32 val;
 294	int ret;
 295
 296	ret = sun4i_backend_drm_format_to_layer(fmt, &val);
 297	if (ret) {
 298		DRM_DEBUG_DRIVER("Invalid format\n");
 299		return ret;
 300	}
 301
 302	regmap_update_bits(backend->engine.regs,
 303			   SUN4I_BACKEND_ATTCTL_REG0(layer),
 304			   SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 305			   SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
 306
 307	regmap_update_bits(backend->engine.regs,
 308			   SUN4I_BACKEND_ATTCTL_REG1(layer),
 309			   SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 310
 311	return 0;
 312}
 313
 314static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
 315					   struct drm_framebuffer *fb,
 316					   dma_addr_t paddr)
 317{
 318	/* TODO: Add support for the multi-planar YUV formats */
 319	DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
 320	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
 321
 322	DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 323	regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
 324		     fb->pitches[0] * 8);
 325
 326	return 0;
 327}
 328
 329int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 330				      int layer, struct drm_plane *plane)
 331{
 332	struct drm_plane_state *state = plane->state;
 333	struct drm_framebuffer *fb = state->fb;
 334	u32 lo_paddr, hi_paddr;
 335	dma_addr_t dma_addr;
 336
 337	/* Set the line width */
 338	DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 339	regmap_write(backend->engine.regs,
 340		     SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 341		     fb->pitches[0] * 8);
 342
 343	/* Get the start of the displayed memory */
 344	dma_addr = drm_fb_dma_get_gem_addr(fb, state, 0);
 345	DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
 346
 347	if (fb->format->is_yuv)
 348		return sun4i_backend_update_yuv_buffer(backend, fb, dma_addr);
 349
 350	/* Write the 32 lower bits of the address (in bits) */
 351	lo_paddr = dma_addr << 3;
 352	DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 353	regmap_write(backend->engine.regs,
 354		     SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 355		     lo_paddr);
 356
 357	/* And the upper bits */
 358	hi_paddr = dma_addr >> 29;
 359	DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 360	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 361			   SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 362			   SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 363
 364	return 0;
 365}
 366
 367int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
 368				    struct drm_plane *plane)
 369{
 370	struct drm_plane_state *state = plane->state;
 371	struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
 372	unsigned int priority = state->normalized_zpos;
 373	unsigned int pipe = p_state->pipe;
 374
 375	DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
 376			 layer, priority, pipe);
 377	regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 378			   SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
 379			   SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
 380			   SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
 381			   SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
 382
 383	return 0;
 384}
 385
 386void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
 387				 int layer)
 388{
 389	regmap_update_bits(backend->engine.regs,
 390			   SUN4I_BACKEND_ATTCTL_REG0(layer),
 391			   SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN |
 392			   SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 393}
 394
 395static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
 396{
 397	u16 src_h = state->src_h >> 16;
 398	u16 src_w = state->src_w >> 16;
 399
 400	DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
 401			 src_w, src_h, state->crtc_w, state->crtc_h);
 402
 403	if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
 404		return true;
 405
 406	return false;
 407}
 408
 409static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
 410{
 411	struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
 412	struct sun4i_backend *backend = layer->backend;
 413	uint32_t format = state->fb->format->format;
 414	uint64_t modifier = state->fb->modifier;
 415
 416	if (IS_ERR(backend->frontend))
 417		return false;
 418
 419	if (!sun4i_frontend_format_is_supported(format, modifier))
 420		return false;
 421
 422	if (!sun4i_backend_format_is_supported(format, modifier))
 423		return true;
 424
 425	/*
 426	 * TODO: The backend alone allows 2x and 4x integer scaling, including
 427	 * support for an alpha component (which the frontend doesn't support).
 428	 * Use the backend directly instead of the frontend in this case, with
 429	 * another test to return false.
 430	 */
 431
 432	if (sun4i_backend_plane_uses_scaler(state))
 433		return true;
 434
 435	/*
 436	 * Here the format is supported by both the frontend and the backend
 437	 * and no frontend scaling is required, so use the backend directly.
 438	 */
 439	return false;
 440}
 441
 442static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state,
 443					     bool *uses_frontend)
 444{
 445	if (sun4i_backend_plane_uses_frontend(state)) {
 446		*uses_frontend = true;
 447		return true;
 448	}
 449
 450	*uses_frontend = false;
 451
 452	/* Scaling is not supported without the frontend. */
 453	if (sun4i_backend_plane_uses_scaler(state))
 454		return false;
 455
 456	return true;
 457}
 458
 459static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
 460				       struct drm_crtc_state *old_state)
 461{
 462	u32 val;
 463
 464	WARN_ON(regmap_read_poll_timeout(engine->regs,
 465					 SUN4I_BACKEND_REGBUFFCTL_REG,
 466					 val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
 467					 100, 50000));
 468}
 469
 470static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
 471				      struct drm_crtc_state *crtc_state)
 472{
 473	struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
 474	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 475	struct drm_atomic_state *state = crtc_state->state;
 476	struct drm_device *drm = state->dev;
 477	struct drm_plane *plane;
 478	unsigned int num_planes = 0;
 479	unsigned int num_alpha_planes = 0;
 480	unsigned int num_frontend_planes = 0;
 481	unsigned int num_alpha_planes_max = 1;
 482	unsigned int num_yuv_planes = 0;
 483	unsigned int current_pipe = 0;
 484	unsigned int i;
 485
 486	DRM_DEBUG_DRIVER("Starting checking our planes\n");
 487
 488	if (!crtc_state->planes_changed)
 489		return 0;
 490
 491	drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
 492		struct drm_plane_state *plane_state =
 493			drm_atomic_get_plane_state(state, plane);
 494		struct sun4i_layer_state *layer_state =
 495			state_to_sun4i_layer_state(plane_state);
 496		struct drm_framebuffer *fb = plane_state->fb;
 497
 498		if (!sun4i_backend_plane_is_supported(plane_state,
 499						      &layer_state->uses_frontend))
 500			return -EINVAL;
 501
 502		if (layer_state->uses_frontend) {
 503			DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
 504					 plane->index);
 505			num_frontend_planes++;
 506		} else {
 507			if (fb->format->is_yuv) {
 508				DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
 509				num_yuv_planes++;
 510			}
 511		}
 512
 513		DRM_DEBUG_DRIVER("Plane FB format is %p4cc\n",
 514				 &fb->format->format);
 515		if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 516			num_alpha_planes++;
 517
 518		DRM_DEBUG_DRIVER("Plane zpos is %d\n",
 519				 plane_state->normalized_zpos);
 520
 521		/* Sort our planes by Zpos */
 522		plane_states[plane_state->normalized_zpos] = plane_state;
 523
 524		num_planes++;
 525	}
 526
 527	/* All our planes were disabled, bail out */
 528	if (!num_planes)
 529		return 0;
 530
 531	/*
 532	 * The hardware is a bit unusual here.
 533	 *
 534	 * Even though it supports 4 layers, it does the composition
 535	 * in two separate steps.
 536	 *
 537	 * The first one is assigning a layer to one of its two
 538	 * pipes. If more that 1 layer is assigned to the same pipe,
 539	 * and if pixels overlaps, the pipe will take the pixel from
 540	 * the layer with the highest priority.
 541	 *
 542	 * The second step is the actual alpha blending, that takes
 543	 * the two pipes as input, and uses the potential alpha
 544	 * component to do the transparency between the two.
 545	 *
 546	 * This two-step scenario makes us unable to guarantee a
 547	 * robust alpha blending between the 4 layers in all
 548	 * situations, since this means that we need to have one layer
 549	 * with alpha at the lowest position of our two pipes.
 550	 *
 551	 * However, we cannot even do that on every platform, since
 552	 * the hardware has a bug where the lowest plane of the lowest
 553	 * pipe (pipe 0, priority 0), if it has any alpha, will
 554	 * discard the pixel data entirely and just display the pixels
 555	 * in the background color (black by default).
 556	 *
 557	 * This means that on the affected platforms, we effectively
 558	 * have only three valid configurations with alpha, all of
 559	 * them with the alpha being on pipe1 with the lowest
 560	 * position, which can be 1, 2 or 3 depending on the number of
 561	 * planes and their zpos.
 562	 */
 563
 564	/* For platforms that are not affected by the issue described above. */
 565	if (backend->quirks->supports_lowest_plane_alpha)
 566		num_alpha_planes_max++;
 567
 568	if (num_alpha_planes > num_alpha_planes_max) {
 569		DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
 570		return -EINVAL;
 571	}
 572
 573	/* We can't have an alpha plane at the lowest position */
 574	if (!backend->quirks->supports_lowest_plane_alpha &&
 575	    (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))
 576		return -EINVAL;
 577
 578	for (i = 1; i < num_planes; i++) {
 579		struct drm_plane_state *p_state = plane_states[i];
 580		struct drm_framebuffer *fb = p_state->fb;
 581		struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
 582
 583		/*
 584		 * The only alpha position is the lowest plane of the
 585		 * second pipe.
 586		 */
 587		if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 588			current_pipe++;
 589
 590		s_state->pipe = current_pipe;
 591	}
 592
 593	/* We can only have a single YUV plane at a time */
 594	if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
 595		DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
 596		return -EINVAL;
 597	}
 598
 599	if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
 600		DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
 601		return -EINVAL;
 602	}
 603
 604	DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
 605			 num_planes, num_alpha_planes, num_frontend_planes,
 606			 num_yuv_planes);
 607
 608	return 0;
 609}
 610
 611static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
 612{
 613	struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 614	struct sun4i_frontend *frontend = backend->frontend;
 615
 616	if (!frontend)
 617		return;
 618
 619	/*
 620	 * In a teardown scenario with the frontend involved, we have
 621	 * to keep the frontend enabled until the next vblank, and
 622	 * only then disable it.
 623	 *
 624	 * This is due to the fact that the backend will not take into
 625	 * account the new configuration (with the plane that used to
 626	 * be fed by the frontend now disabled) until we write to the
 627	 * commit bit and the hardware fetches the new configuration
 628	 * during the next vblank.
 629	 *
 630	 * So we keep the frontend around in order to prevent any
 631	 * visual artifacts.
 632	 */
 633	spin_lock(&backend->frontend_lock);
 634	if (backend->frontend_teardown) {
 635		sun4i_frontend_exit(frontend);
 636		backend->frontend_teardown = false;
 637	}
 638	spin_unlock(&backend->frontend_lock);
 639};
 640
 641static void sun4i_backend_mode_set(struct sunxi_engine *engine,
 642				   const struct drm_display_mode *mode)
 643{
 644	bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
 645
 646	DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
 647			 mode->hdisplay, mode->vdisplay);
 648
 649	regmap_write(engine->regs, SUN4I_BACKEND_DISSIZE_REG,
 650		     SUN4I_BACKEND_DISSIZE(mode->hdisplay, mode->vdisplay));
 651
 652	regmap_update_bits(engine->regs, SUN4I_BACKEND_MODCTL_REG,
 653			   SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 654			   interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 655
 656	DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 657			 interlaced ? "on" : "off");
 658}
 659
 660static int sun4i_backend_init_sat(struct device *dev) {
 661	struct sun4i_backend *backend = dev_get_drvdata(dev);
 662	int ret;
 663
 664	backend->sat_reset = devm_reset_control_get(dev, "sat");
 665	if (IS_ERR(backend->sat_reset)) {
 666		dev_err(dev, "Couldn't get the SAT reset line\n");
 667		return PTR_ERR(backend->sat_reset);
 668	}
 669
 670	ret = reset_control_deassert(backend->sat_reset);
 671	if (ret) {
 672		dev_err(dev, "Couldn't deassert the SAT reset line\n");
 673		return ret;
 674	}
 675
 676	backend->sat_clk = devm_clk_get(dev, "sat");
 677	if (IS_ERR(backend->sat_clk)) {
 678		dev_err(dev, "Couldn't get our SAT clock\n");
 679		ret = PTR_ERR(backend->sat_clk);
 680		goto err_assert_reset;
 681	}
 682
 683	ret = clk_prepare_enable(backend->sat_clk);
 684	if (ret) {
 685		dev_err(dev, "Couldn't enable the SAT clock\n");
 686		return ret;
 687	}
 688
 689	return 0;
 690
 691err_assert_reset:
 692	reset_control_assert(backend->sat_reset);
 693	return ret;
 694}
 695
 696static int sun4i_backend_free_sat(struct device *dev) {
 697	struct sun4i_backend *backend = dev_get_drvdata(dev);
 698
 699	clk_disable_unprepare(backend->sat_clk);
 700	reset_control_assert(backend->sat_reset);
 701
 702	return 0;
 703}
 704
 705/*
 706 * The display backend can take video output from the display frontend, or
 707 * the display enhancement unit on the A80, as input for one it its layers.
 708 * This relationship within the display pipeline is encoded in the device
 709 * tree with of_graph, and we use it here to figure out which backend, if
 710 * there are 2 or more, we are currently probing. The number would be in
 711 * the "reg" property of the upstream output port endpoint.
 712 */
 713static int sun4i_backend_of_get_id(struct device_node *node)
 714{
 715	struct device_node *ep, *remote;
 716	struct of_endpoint of_ep;
 717
 718	/* Input port is 0, and we want the first endpoint. */
 719	ep = of_graph_get_endpoint_by_regs(node, 0, -1);
 720	if (!ep)
 721		return -EINVAL;
 722
 723	remote = of_graph_get_remote_endpoint(ep);
 724	of_node_put(ep);
 725	if (!remote)
 726		return -EINVAL;
 727
 728	of_graph_parse_endpoint(remote, &of_ep);
 729	of_node_put(remote);
 730	return of_ep.id;
 731}
 732
 733/* TODO: This needs to take multiple pipelines into account */
 734static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
 735							  struct device_node *node)
 736{
 737	struct device_node *port, *ep, *remote;
 738	struct sun4i_frontend *frontend;
 739
 740	port = of_graph_get_port_by_id(node, 0);
 741	if (!port)
 742		return ERR_PTR(-EINVAL);
 743
 744	for_each_available_child_of_node(port, ep) {
 745		remote = of_graph_get_remote_port_parent(ep);
 746		if (!remote)
 747			continue;
 748		of_node_put(remote);
 749
 750		/* does this node match any registered engines? */
 751		list_for_each_entry(frontend, &drv->frontend_list, list) {
 752			if (remote == frontend->node) {
 753				of_node_put(port);
 754				of_node_put(ep);
 755				return frontend;
 756			}
 757		}
 758	}
 759	of_node_put(port);
 760	return ERR_PTR(-EINVAL);
 761}
 762
 763static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 764	.atomic_begin			= sun4i_backend_atomic_begin,
 765	.atomic_check			= sun4i_backend_atomic_check,
 766	.commit				= sun4i_backend_commit,
 767	.layers_init			= sun4i_layers_init,
 768	.apply_color_correction		= sun4i_backend_apply_color_correction,
 769	.disable_color_correction	= sun4i_backend_disable_color_correction,
 770	.vblank_quirk			= sun4i_backend_vblank_quirk,
 771	.mode_set			= sun4i_backend_mode_set,
 772};
 773
 774static const struct regmap_config sun4i_backend_regmap_config = {
 775	.reg_bits	= 32,
 776	.val_bits	= 32,
 777	.reg_stride	= 4,
 778	.max_register	= 0x5800,
 779};
 780
 781static int sun4i_backend_bind(struct device *dev, struct device *master,
 782			      void *data)
 783{
 784	struct platform_device *pdev = to_platform_device(dev);
 785	struct drm_device *drm = data;
 786	struct sun4i_drv *drv = drm->dev_private;
 787	struct sun4i_backend *backend;
 788	const struct sun4i_backend_quirks *quirks;
 789	void __iomem *regs;
 790	int i, ret;
 791
 792	backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 793	if (!backend)
 794		return -ENOMEM;
 795	dev_set_drvdata(dev, backend);
 796	spin_lock_init(&backend->frontend_lock);
 797
 798	if (of_property_present(dev->of_node, "interconnects")) {
 799		/*
 800		 * This assume we have the same DMA constraints for all our the
 801		 * devices in our pipeline (all the backends, but also the
 802		 * frontends). This sounds bad, but it has always been the case
 803		 * for us, and DRM doesn't do per-device allocation either, so
 804		 * we would need to fix DRM first...
 805		 */
 806		ret = of_dma_configure(drm->dev, dev->of_node, true);
 807		if (ret)
 808			return ret;
 809	}
 810
 811	backend->engine.node = dev->of_node;
 812	backend->engine.ops = &sun4i_backend_engine_ops;
 813	backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 814	if (backend->engine.id < 0)
 815		return backend->engine.id;
 816
 817	backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 818	if (IS_ERR(backend->frontend))
 819		dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
 820
 821	regs = devm_platform_ioremap_resource(pdev, 0);
 822	if (IS_ERR(regs))
 823		return PTR_ERR(regs);
 824
 825	backend->reset = devm_reset_control_get(dev, NULL);
 826	if (IS_ERR(backend->reset)) {
 827		dev_err(dev, "Couldn't get our reset line\n");
 828		return PTR_ERR(backend->reset);
 829	}
 830
 831	ret = reset_control_deassert(backend->reset);
 832	if (ret) {
 833		dev_err(dev, "Couldn't deassert our reset line\n");
 834		return ret;
 835	}
 836
 837	backend->bus_clk = devm_clk_get(dev, "ahb");
 838	if (IS_ERR(backend->bus_clk)) {
 839		dev_err(dev, "Couldn't get the backend bus clock\n");
 840		ret = PTR_ERR(backend->bus_clk);
 841		goto err_assert_reset;
 842	}
 843	clk_prepare_enable(backend->bus_clk);
 844
 845	backend->mod_clk = devm_clk_get(dev, "mod");
 846	if (IS_ERR(backend->mod_clk)) {
 847		dev_err(dev, "Couldn't get the backend module clock\n");
 848		ret = PTR_ERR(backend->mod_clk);
 849		goto err_disable_bus_clk;
 850	}
 851
 852	ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
 853	if (ret) {
 854		dev_err(dev, "Couldn't set the module clock frequency\n");
 855		goto err_disable_bus_clk;
 856	}
 857
 858	clk_prepare_enable(backend->mod_clk);
 859
 860	backend->ram_clk = devm_clk_get(dev, "ram");
 861	if (IS_ERR(backend->ram_clk)) {
 862		dev_err(dev, "Couldn't get the backend RAM clock\n");
 863		ret = PTR_ERR(backend->ram_clk);
 864		goto err_disable_mod_clk;
 865	}
 866	clk_prepare_enable(backend->ram_clk);
 867
 868	if (of_device_is_compatible(dev->of_node,
 869				    "allwinner,sun8i-a33-display-backend")) {
 870		ret = sun4i_backend_init_sat(dev);
 871		if (ret) {
 872			dev_err(dev, "Couldn't init SAT resources\n");
 873			goto err_disable_ram_clk;
 874		}
 875	}
 876
 877	backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 878						     &sun4i_backend_regmap_config);
 879	if (IS_ERR(backend->engine.regs)) {
 880		dev_err(dev, "Couldn't create the backend regmap\n");
 881		return PTR_ERR(backend->engine.regs);
 882	}
 883
 884	list_add_tail(&backend->engine.list, &drv->engine_list);
 885
 886	/*
 887	 * Many of the backend's layer configuration registers have
 888	 * undefined default values. This poses a risk as we use
 889	 * regmap_update_bits in some places, and don't overwrite
 890	 * the whole register.
 891	 *
 892	 * Clear the registers here to have something predictable.
 893	 */
 894	for (i = 0x800; i < 0x1000; i += 4)
 895		regmap_write(backend->engine.regs, i, 0);
 896
 897	/* Disable registers autoloading */
 898	regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 899		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 900
 901	/* Enable the backend */
 902	regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 903		     SUN4I_BACKEND_MODCTL_DEBE_EN |
 904		     SUN4I_BACKEND_MODCTL_START_CTL);
 905
 906	/* Set output selection if needed */
 907	quirks = of_device_get_match_data(dev);
 908	if (quirks->needs_output_muxing) {
 909		/*
 910		 * We assume there is no dynamic muxing of backends
 911		 * and TCONs, so we select the backend with same ID.
 912		 *
 913		 * While dynamic selection might be interesting, since
 914		 * the CRTC is tied to the TCON, while the layers are
 915		 * tied to the backends, this means, we will need to
 916		 * switch between groups of layers. There might not be
 917		 * a way to represent this constraint in DRM.
 918		 */
 919		regmap_update_bits(backend->engine.regs,
 920				   SUN4I_BACKEND_MODCTL_REG,
 921				   SUN4I_BACKEND_MODCTL_OUT_SEL,
 922				   (backend->engine.id
 923				    ? SUN4I_BACKEND_MODCTL_OUT_LCD1
 924				    : SUN4I_BACKEND_MODCTL_OUT_LCD0));
 925	}
 926
 927	backend->quirks = quirks;
 928
 929	return 0;
 930
 931err_disable_ram_clk:
 932	clk_disable_unprepare(backend->ram_clk);
 933err_disable_mod_clk:
 934	clk_rate_exclusive_put(backend->mod_clk);
 935	clk_disable_unprepare(backend->mod_clk);
 936err_disable_bus_clk:
 937	clk_disable_unprepare(backend->bus_clk);
 938err_assert_reset:
 939	reset_control_assert(backend->reset);
 940	return ret;
 941}
 942
 943static void sun4i_backend_unbind(struct device *dev, struct device *master,
 944				 void *data)
 945{
 946	struct sun4i_backend *backend = dev_get_drvdata(dev);
 947
 948	list_del(&backend->engine.list);
 949
 950	if (of_device_is_compatible(dev->of_node,
 951				    "allwinner,sun8i-a33-display-backend"))
 952		sun4i_backend_free_sat(dev);
 953
 954	clk_disable_unprepare(backend->ram_clk);
 955	clk_rate_exclusive_put(backend->mod_clk);
 956	clk_disable_unprepare(backend->mod_clk);
 957	clk_disable_unprepare(backend->bus_clk);
 958	reset_control_assert(backend->reset);
 959}
 960
 961static const struct component_ops sun4i_backend_ops = {
 962	.bind	= sun4i_backend_bind,
 963	.unbind	= sun4i_backend_unbind,
 964};
 965
 966static int sun4i_backend_probe(struct platform_device *pdev)
 967{
 968	return component_add(&pdev->dev, &sun4i_backend_ops);
 969}
 970
 971static void sun4i_backend_remove(struct platform_device *pdev)
 972{
 973	component_del(&pdev->dev, &sun4i_backend_ops);
 974}
 975
 976static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 977	.needs_output_muxing = true,
 978};
 979
 980static const struct sun4i_backend_quirks sun5i_backend_quirks = {
 981};
 982
 983static const struct sun4i_backend_quirks sun6i_backend_quirks = {
 984};
 985
 986static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 987	.needs_output_muxing = true,
 988};
 989
 990static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 991	.supports_lowest_plane_alpha = true,
 992};
 993
 994static const struct sun4i_backend_quirks sun9i_backend_quirks = {
 995};
 996
 997static const struct of_device_id sun4i_backend_of_table[] = {
 998	{
 999		.compatible = "allwinner,sun4i-a10-display-backend",
1000		.data = &sun4i_backend_quirks,
1001	},
1002	{
1003		.compatible = "allwinner,sun5i-a13-display-backend",
1004		.data = &sun5i_backend_quirks,
1005	},
1006	{
1007		.compatible = "allwinner,sun6i-a31-display-backend",
1008		.data = &sun6i_backend_quirks,
1009	},
1010	{
1011		.compatible = "allwinner,sun7i-a20-display-backend",
1012		.data = &sun7i_backend_quirks,
1013	},
1014	{
1015		.compatible = "allwinner,sun8i-a23-display-backend",
1016		.data = &sun8i_a33_backend_quirks,
1017	},
1018	{
1019		.compatible = "allwinner,sun8i-a33-display-backend",
1020		.data = &sun8i_a33_backend_quirks,
1021	},
1022	{
1023		.compatible = "allwinner,sun9i-a80-display-backend",
1024		.data = &sun9i_backend_quirks,
1025	},
1026	{ }
1027};
1028MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
1029
1030static struct platform_driver sun4i_backend_platform_driver = {
1031	.probe		= sun4i_backend_probe,
1032	.remove		= sun4i_backend_remove,
1033	.driver		= {
1034		.name		= "sun4i-backend",
1035		.of_match_table	= sun4i_backend_of_table,
1036	},
1037};
1038module_platform_driver(sun4i_backend_platform_driver);
1039
1040MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1041MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
1042MODULE_LICENSE("GPL");