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ltdc.c
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linux-6.19.14/drivers/gpu/drm/stm/ltdc.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11#include <linux/clk.h> 12#include <linux/component.h> 13#include <linux/delay.h> 14#include <linux/interrupt.h> 15#include <linux/media-bus-format.h> 16#include <linux/module.h> 17#include <linux/of.h> 18#include <linux/of_graph.h> 19#include <linux/pinctrl/consumer.h> 20#include <linux/platform_device.h> 21#include <linux/pm_runtime.h> 22#include <linux/regmap.h> 23#include <linux/reset.h> 24 25#include <drm/drm_atomic.h> 26#include <drm/drm_atomic_helper.h> 27#include <drm/drm_blend.h> 28#include <drm/drm_bridge.h> 29#include <drm/drm_device.h> 30#include <drm/drm_edid.h> 31#include <drm/drm_fb_dma_helper.h> 32#include <drm/drm_fourcc.h> 33#include <drm/drm_framebuffer.h> 34#include <drm/drm_gem_atomic_helper.h> 35#include <drm/drm_gem_dma_helper.h> 36#include <drm/drm_of.h> 37#include <drm/drm_print.h> 38#include <drm/drm_probe_helper.h> 39#include <drm/drm_simple_kms_helper.h> 40#include <drm/drm_vblank.h> 41#include <drm/drm_managed.h> 42 43#include <video/videomode.h> 44 45#include "ltdc.h" 46 47#define NB_CRTC 1 48#define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 49 50#define MAX_IRQ 4 51 52#define HWVER_10200 0x010200 53#define HWVER_10300 0x010300 54#define HWVER_20101 0x020101 55#define HWVER_40100 0x040100 56#define HWVER_40101 0x040101 57 58/* 59 * The address of some registers depends on the HW version: such registers have 60 * an extra offset specified with layer_ofs. 61 */ 62#define LAY_OFS_0 0x80 63#define LAY_OFS_1 0x100 64#define LAY_OFS (ldev->caps.layer_ofs) 65 66/* Global register offsets */ 67#define LTDC_IDR 0x0000 /* IDentification */ 68#define LTDC_LCR 0x0004 /* Layer Count */ 69#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 70#define LTDC_BPCR 0x000C /* Back Porch Configuration */ 71#define LTDC_AWCR 0x0010 /* Active Width Configuration */ 72#define LTDC_TWCR 0x0014 /* Total Width Configuration */ 73#define LTDC_GCR 0x0018 /* Global Control */ 74#define LTDC_GC1R 0x001C /* Global Configuration 1 */ 75#define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 76#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 77#define LTDC_GACR 0x0028 /* GAmma Correction */ 78#define LTDC_BCCR 0x002C /* Background Color Configuration */ 79#define LTDC_IER 0x0034 /* Interrupt Enable */ 80#define LTDC_ISR 0x0038 /* Interrupt Status */ 81#define LTDC_ICR 0x003C /* Interrupt Clear */ 82#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 83#define LTDC_CPSR 0x0044 /* Current Position Status */ 84#define LTDC_CDSR 0x0048 /* Current Display Status */ 85#define LTDC_EDCR 0x0060 /* External Display Control */ 86#define LTDC_CCRCR 0x007C /* Computed CRC value */ 87#define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ 88 89/* Layer register offsets */ 90#define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ 91#define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ 92#define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ 93#define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ 94#define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ 95#define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ 96#define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ 97#define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ 98#define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ 99#define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ 100#define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ 101#define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ 102#define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ 103#define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ 104#define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ 105#define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ 106#define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ 107#define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ 108#define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ 109#define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ 110#define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ 111#define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ 112#define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ 113#define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ 114#define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ 115 116/* Bit definitions */ 117#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 118#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 119 120#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 121#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 122 123#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 124#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 125 126#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 127#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 128 129#define GCR_LTDCEN BIT(0) /* LTDC ENable */ 130#define GCR_DEN BIT(16) /* Dither ENable */ 131#define GCR_CRCEN BIT(19) /* CRC ENable */ 132#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 133#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 134#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 135#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 136 137#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 138#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 139#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 140#define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 141#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 142#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 143#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 144#define GC1R_BCP BIT(22) /* Background Colour Programmable */ 145#define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 146#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 147#define GC1R_TP BIT(25) /* Timing Programmable */ 148#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 149#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 150#define GC1R_DWP BIT(28) /* Dither Width Programmable */ 151#define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 152#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 153 154#define GC2R_EDCA BIT(0) /* External Display Control Ability */ 155#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 156#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 157#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 158#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 159#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 160 161#define SRCR_IMR BIT(0) /* IMmediate Reload */ 162#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 163 164#define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 165#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 166#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 167#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 168#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 169 170#define IER_LIE BIT(0) /* Line Interrupt Enable */ 171#define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */ 172#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 173#define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */ 174#define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */ 175#define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */ 176#define IER_MASK (IER_LIE | IER_FUWIE | IER_TERRIE | IER_RRIE | IER_FUEIE | IER_CRCIE) 177 178#define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 179 180#define ISR_LIF BIT(0) /* Line Interrupt Flag */ 181#define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */ 182#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 183#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 184#define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */ 185#define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */ 186 187#define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ 188#define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ 189#define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */ 190 191#define LXCR_LEN BIT(0) /* Layer ENable */ 192#define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 193#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 194#define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */ 195#define LXCR_MASK (LXCR_LEN | LXCR_COLKEN | LXCR_CLUTEN | LXCR_HMEN) 196 197#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 198#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 199 200#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 201#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 202 203#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 204#define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */ 205 206#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 207 208#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 209#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 210#define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ 211 212#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 213#define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */ 214 215#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 216 217#define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */ 218#define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */ 219#define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */ 220#define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/ 221 222#define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */ 223#define LxPCR_OF BIT(8) /* Odd pixel First */ 224#define LxPCR_CBF BIT(7) /* CB component First */ 225#define LxPCR_YF BIT(6) /* Y component First */ 226#define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */ 227#define YCM_I 0x0 /* Interleaved 422 */ 228#define YCM_SP 0x1 /* Semi-Planar 420 */ 229#define YCM_FP 0x2 /* Full-Planar 420 */ 230#define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */ 231 232#define LXRCR_IMR BIT(0) /* IMmediate Reload */ 233#define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */ 234#define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */ 235 236#define CLUT_SIZE 256 237 238#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 239#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 240#define BF1_CA 0x400 /* Constant Alpha */ 241#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 242#define BF2_1CA 0x005 /* 1 - Constant Alpha */ 243 244#define NB_PF 8 /* Max nb of HW pixel format */ 245 246#define FUT_DFT 128 /* Default value of fifo underrun threshold */ 247 248/* 249 * Skip the first value and the second in case CRC was enabled during 250 * the thread irq. This is to be sure CRC value is relevant for the 251 * frame. 252 */ 253#define CRC_SKIP_FRAMES 2 254 255enum ltdc_pix_fmt { 256 PF_NONE, 257 /* RGB formats */ 258 PF_ARGB8888, /* ARGB [32 bits] */ 259 PF_RGBA8888, /* RGBA [32 bits] */ 260 PF_ABGR8888, /* ABGR [32 bits] */ 261 PF_BGRA8888, /* BGRA [32 bits] */ 262 PF_RGB888, /* RGB [24 bits] */ 263 PF_BGR888, /* BGR [24 bits] */ 264 PF_RGB565, /* RGB [16 bits] */ 265 PF_BGR565, /* BGR [16 bits] */ 266 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 267 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 268 /* Indexed formats */ 269 PF_L8, /* Indexed 8 bits [8 bits] */ 270 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 271 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 272}; 273 274/* The index gives the encoding of the pixel format for an HW version */ 275static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 276 PF_ARGB8888, /* 0x00 */ 277 PF_RGB888, /* 0x01 */ 278 PF_RGB565, /* 0x02 */ 279 PF_ARGB1555, /* 0x03 */ 280 PF_ARGB4444, /* 0x04 */ 281 PF_L8, /* 0x05 */ 282 PF_AL44, /* 0x06 */ 283 PF_AL88 /* 0x07 */ 284}; 285 286static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 287 PF_ARGB8888, /* 0x00 */ 288 PF_RGB888, /* 0x01 */ 289 PF_RGB565, /* 0x02 */ 290 PF_RGBA8888, /* 0x03 */ 291 PF_AL44, /* 0x04 */ 292 PF_L8, /* 0x05 */ 293 PF_ARGB1555, /* 0x06 */ 294 PF_ARGB4444 /* 0x07 */ 295}; 296 297static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { 298 PF_ARGB8888, /* 0x00 */ 299 PF_ABGR8888, /* 0x01 */ 300 PF_RGBA8888, /* 0x02 */ 301 PF_BGRA8888, /* 0x03 */ 302 PF_RGB565, /* 0x04 */ 303 PF_BGR565, /* 0x05 */ 304 PF_RGB888, /* 0x06 */ 305 PF_NONE /* 0x07 */ 306}; 307 308static const u32 ltdc_drm_fmt_a0[] = { 309 DRM_FORMAT_ARGB8888, 310 DRM_FORMAT_XRGB8888, 311 DRM_FORMAT_RGB888, 312 DRM_FORMAT_RGB565, 313 DRM_FORMAT_ARGB1555, 314 DRM_FORMAT_XRGB1555, 315 DRM_FORMAT_ARGB4444, 316 DRM_FORMAT_XRGB4444, 317 DRM_FORMAT_C8 318}; 319 320static const u32 ltdc_drm_fmt_a1[] = { 321 DRM_FORMAT_ARGB8888, 322 DRM_FORMAT_XRGB8888, 323 DRM_FORMAT_RGB888, 324 DRM_FORMAT_RGB565, 325 DRM_FORMAT_RGBA8888, 326 DRM_FORMAT_RGBX8888, 327 DRM_FORMAT_ARGB1555, 328 DRM_FORMAT_XRGB1555, 329 DRM_FORMAT_ARGB4444, 330 DRM_FORMAT_XRGB4444, 331 DRM_FORMAT_C8 332}; 333 334static const u32 ltdc_drm_fmt_a2[] = { 335 DRM_FORMAT_ARGB8888, 336 DRM_FORMAT_XRGB8888, 337 DRM_FORMAT_ABGR8888, 338 DRM_FORMAT_XBGR8888, 339 DRM_FORMAT_RGBA8888, 340 DRM_FORMAT_RGBX8888, 341 DRM_FORMAT_BGRA8888, 342 DRM_FORMAT_BGRX8888, 343 DRM_FORMAT_RGB565, 344 DRM_FORMAT_BGR565, 345 DRM_FORMAT_RGB888, 346 DRM_FORMAT_BGR888, 347 DRM_FORMAT_ARGB1555, 348 DRM_FORMAT_XRGB1555, 349 DRM_FORMAT_ARGB4444, 350 DRM_FORMAT_XRGB4444, 351 DRM_FORMAT_C8 352}; 353 354static const u32 ltdc_drm_fmt_ycbcr_cp[] = { 355 DRM_FORMAT_YUYV, 356 DRM_FORMAT_YVYU, 357 DRM_FORMAT_UYVY, 358 DRM_FORMAT_VYUY 359}; 360 361static const u32 ltdc_drm_fmt_ycbcr_sp[] = { 362 DRM_FORMAT_NV12, 363 DRM_FORMAT_NV21 364}; 365 366static const u32 ltdc_drm_fmt_ycbcr_fp[] = { 367 DRM_FORMAT_YUV420, 368 DRM_FORMAT_YVU420 369}; 370 371/* Layer register offsets */ 372static const u32 ltdc_layer_regs_a0[] = { 373 0x80, /* L1 configuration 0 */ 374 0x00, /* not available */ 375 0x00, /* not available */ 376 0x84, /* L1 control register */ 377 0x88, /* L1 window horizontal position configuration */ 378 0x8c, /* L1 window vertical position configuration */ 379 0x90, /* L1 color keying configuration */ 380 0x94, /* L1 pixel format configuration */ 381 0x98, /* L1 constant alpha configuration */ 382 0x9c, /* L1 default color configuration */ 383 0xa0, /* L1 blending factors configuration */ 384 0x00, /* not available */ 385 0x00, /* not available */ 386 0xac, /* L1 color frame buffer address */ 387 0xb0, /* L1 color frame buffer length */ 388 0xb4, /* L1 color frame buffer line number */ 389 0x00, /* not available */ 390 0x00, /* not available */ 391 0x00, /* not available */ 392 0x00, /* not available */ 393 0xc4, /* L1 CLUT write */ 394 0x00, /* not available */ 395 0x00, /* not available */ 396 0x00, /* not available */ 397 0x00 /* not available */ 398}; 399 400static const u32 ltdc_layer_regs_a1[] = { 401 0x80, /* L1 configuration 0 */ 402 0x84, /* L1 configuration 1 */ 403 0x00, /* L1 reload control */ 404 0x88, /* L1 control register */ 405 0x8c, /* L1 window horizontal position configuration */ 406 0x90, /* L1 window vertical position configuration */ 407 0x94, /* L1 color keying configuration */ 408 0x98, /* L1 pixel format configuration */ 409 0x9c, /* L1 constant alpha configuration */ 410 0xa0, /* L1 default color configuration */ 411 0xa4, /* L1 blending factors configuration */ 412 0xa8, /* L1 burst length configuration */ 413 0x00, /* not available */ 414 0xac, /* L1 color frame buffer address */ 415 0xb0, /* L1 color frame buffer length */ 416 0xb4, /* L1 color frame buffer line number */ 417 0xb8, /* L1 auxiliary frame buffer address 0 */ 418 0xbc, /* L1 auxiliary frame buffer address 1 */ 419 0xc0, /* L1 auxiliary frame buffer length */ 420 0xc4, /* L1 auxiliary frame buffer line number */ 421 0xc8, /* L1 CLUT write */ 422 0x00, /* not available */ 423 0x00, /* not available */ 424 0x00, /* not available */ 425 0x00 /* not available */ 426}; 427 428static const u32 ltdc_layer_regs_a2[] = { 429 0x100, /* L1 configuration 0 */ 430 0x104, /* L1 configuration 1 */ 431 0x108, /* L1 reload control */ 432 0x10c, /* L1 control register */ 433 0x110, /* L1 window horizontal position configuration */ 434 0x114, /* L1 window vertical position configuration */ 435 0x118, /* L1 color keying configuration */ 436 0x11c, /* L1 pixel format configuration */ 437 0x120, /* L1 constant alpha configuration */ 438 0x124, /* L1 default color configuration */ 439 0x128, /* L1 blending factors configuration */ 440 0x12c, /* L1 burst length configuration */ 441 0x130, /* L1 planar configuration */ 442 0x134, /* L1 color frame buffer address */ 443 0x138, /* L1 color frame buffer length */ 444 0x13c, /* L1 color frame buffer line number */ 445 0x140, /* L1 auxiliary frame buffer address 0 */ 446 0x144, /* L1 auxiliary frame buffer address 1 */ 447 0x148, /* L1 auxiliary frame buffer length */ 448 0x14c, /* L1 auxiliary frame buffer line number */ 449 0x150, /* L1 CLUT write */ 450 0x16c, /* L1 Conversion YCbCr RGB 0 */ 451 0x170, /* L1 Conversion YCbCr RGB 1 */ 452 0x174, /* L1 Flexible Pixel Format 0 */ 453 0x178 /* L1 Flexible Pixel Format 1 */ 454}; 455 456static const u64 ltdc_format_modifiers[] = { 457 DRM_FORMAT_MOD_LINEAR, 458 DRM_FORMAT_MOD_INVALID 459}; 460 461static const struct regmap_config stm32_ltdc_regmap_cfg = { 462 .reg_bits = 32, 463 .val_bits = 32, 464 .reg_stride = sizeof(u32), 465 .max_register = 0x400, 466 .use_relaxed_mmio = true, 467 .cache_type = REGCACHE_NONE, 468}; 469 470static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = { 471 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 472 0x02040199, /* (b_cb = 516 / r_cr = 409) */ 473 0x006400D0 /* (g_cb = 100 / g_cr = 208) */ 474 }, 475 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 476 0x01C60167, /* (b_cb = 454 / r_cr = 359) */ 477 0x005800B7 /* (g_cb = 88 / g_cr = 183) */ 478 }, 479 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 480 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */ 481 0x00370089 /* (g_cb = 55 / g_cr = 137) */ 482 }, 483 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 484 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */ 485 0x00300078 /* (g_cb = 48 / g_cr = 120) */ 486 } 487 /* BT2020 not supported */ 488}; 489 490static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 491{ 492 return (struct ltdc_device *)crtc->dev->dev_private; 493} 494 495static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 496{ 497 return (struct ltdc_device *)plane->dev->dev_private; 498} 499 500static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 501{ 502 enum ltdc_pix_fmt pf; 503 504 switch (drm_fmt) { 505 case DRM_FORMAT_ARGB8888: 506 case DRM_FORMAT_XRGB8888: 507 pf = PF_ARGB8888; 508 break; 509 case DRM_FORMAT_ABGR8888: 510 case DRM_FORMAT_XBGR8888: 511 pf = PF_ABGR8888; 512 break; 513 case DRM_FORMAT_RGBA8888: 514 case DRM_FORMAT_RGBX8888: 515 pf = PF_RGBA8888; 516 break; 517 case DRM_FORMAT_BGRA8888: 518 case DRM_FORMAT_BGRX8888: 519 pf = PF_BGRA8888; 520 break; 521 case DRM_FORMAT_RGB888: 522 pf = PF_RGB888; 523 break; 524 case DRM_FORMAT_BGR888: 525 pf = PF_BGR888; 526 break; 527 case DRM_FORMAT_RGB565: 528 pf = PF_RGB565; 529 break; 530 case DRM_FORMAT_BGR565: 531 pf = PF_BGR565; 532 break; 533 case DRM_FORMAT_ARGB1555: 534 case DRM_FORMAT_XRGB1555: 535 pf = PF_ARGB1555; 536 break; 537 case DRM_FORMAT_ARGB4444: 538 case DRM_FORMAT_XRGB4444: 539 pf = PF_ARGB4444; 540 break; 541 case DRM_FORMAT_C8: 542 pf = PF_L8; 543 break; 544 default: 545 pf = PF_NONE; 546 break; 547 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 548 } 549 550 return pf; 551} 552 553static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) 554{ 555 struct ltdc_device *ldev = plane_to_ltdc(plane); 556 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; 557 int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos; 558 559 switch (pix_fmt) { 560 case PF_BGR888: 561 psize = 3; 562 alen = 0; apos = 0; rlen = 8; rpos = 0; 563 glen = 8; gpos = 8; blen = 8; bpos = 16; 564 break; 565 case PF_ARGB1555: 566 psize = 2; 567 alen = 1; apos = 15; rlen = 5; rpos = 10; 568 glen = 5; gpos = 5; blen = 5; bpos = 0; 569 break; 570 case PF_ARGB4444: 571 psize = 2; 572 alen = 4; apos = 12; rlen = 4; rpos = 8; 573 glen = 4; gpos = 4; blen = 4; bpos = 0; 574 break; 575 case PF_L8: 576 psize = 1; 577 alen = 0; apos = 0; rlen = 8; rpos = 0; 578 glen = 8; gpos = 0; blen = 8; bpos = 0; 579 break; 580 case PF_AL44: 581 psize = 1; 582 alen = 4; apos = 4; rlen = 4; rpos = 0; 583 glen = 4; gpos = 0; blen = 4; bpos = 0; 584 break; 585 case PF_AL88: 586 psize = 2; 587 alen = 8; apos = 8; rlen = 8; rpos = 0; 588 glen = 8; gpos = 0; blen = 8; bpos = 0; 589 break; 590 default: 591 ret = NB_PF; /* error case, trace msg is handled by the caller */ 592 break; 593 } 594 595 if (ret == PF_FLEXIBLE) { 596 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, 597 (rlen << 14) + (rpos << 9) + (alen << 5) + apos); 598 599 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, 600 (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos); 601 } 602 603 return ret; 604} 605 606/* 607 * All non-alpha color formats derived from native alpha color formats are 608 * either characterized by a FourCC format code 609 */ 610static inline u32 is_xrgb(u32 drm) 611{ 612 return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X'); 613} 614 615static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) 616{ 617 struct ltdc_device *ldev = plane_to_ltdc(plane); 618 struct drm_plane_state *state = plane->state; 619 u32 lofs = plane->index * LAY_OFS; 620 u32 val; 621 622 switch (drm_pix_fmt) { 623 case DRM_FORMAT_YUYV: 624 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF; 625 break; 626 case DRM_FORMAT_YVYU: 627 val = (YCM_I << 4) | LxPCR_YF; 628 break; 629 case DRM_FORMAT_UYVY: 630 val = (YCM_I << 4) | LxPCR_CBF; 631 break; 632 case DRM_FORMAT_VYUY: 633 val = (YCM_I << 4); 634 break; 635 case DRM_FORMAT_NV12: 636 val = (YCM_SP << 4) | LxPCR_CBF; 637 break; 638 case DRM_FORMAT_NV21: 639 val = (YCM_SP << 4); 640 break; 641 case DRM_FORMAT_YUV420: 642 case DRM_FORMAT_YVU420: 643 val = (YCM_FP << 4); 644 break; 645 default: 646 /* RGB or not a YCbCr supported format */ 647 drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt); 648 return; 649 } 650 651 /* Enable limited range */ 652 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) 653 val |= LxPCR_YREN; 654 655 /* enable ycbcr conversion */ 656 val |= LxPCR_YCEN; 657 658 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); 659} 660 661static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) 662{ 663 struct ltdc_device *ldev = plane_to_ltdc(plane); 664 struct drm_plane_state *state = plane->state; 665 enum drm_color_encoding enc = state->color_encoding; 666 enum drm_color_range ran = state->color_range; 667 u32 lofs = plane->index * LAY_OFS; 668 669 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 670 drm_err(plane->dev, "color encoding %d not supported, use bt601 by default\n", enc); 671 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 672 enc = DRM_COLOR_YCBCR_BT601; 673 } 674 675 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 676 drm_err(plane->dev, 677 "color range %d not supported, use limited range by default\n", ran); 678 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 679 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 680 } 681 682 drm_err(plane->dev, "Color encoding=%d, range=%d\n", enc, ran); 683 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 684 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 685 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, 686 ltdc_ycbcr2rgb_coeffs[enc][ran][1]); 687} 688 689static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev, 690 struct drm_crtc *crtc) 691{ 692 u32 crc; 693 int ret; 694 695 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { 696 ldev->crc_skip_count++; 697 return; 698 } 699 700 /* Get the CRC of the frame */ 701 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); 702 if (ret) 703 return; 704 705 /* Report to DRM the CRC (hw dependent feature) */ 706 drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc); 707} 708 709static irqreturn_t ltdc_irq_thread(int irq, void *arg) 710{ 711 struct drm_device *ddev = arg; 712 struct ltdc_device *ldev = ddev->dev_private; 713 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 714 715 /* Line IRQ : trigger the vblank event */ 716 if (ldev->irq_status & ISR_LIF) { 717 drm_crtc_handle_vblank(crtc); 718 719 /* Early return if CRC is not active */ 720 if (ldev->crc_active) 721 ltdc_irq_crc_handle(ldev, crtc); 722 } 723 724 mutex_lock(&ldev->err_lock); 725 if (ldev->irq_status & ISR_TERRIF) 726 ldev->transfer_err++; 727 if (ldev->irq_status & ISR_FUEIF) 728 ldev->fifo_err++; 729 if (ldev->irq_status & ISR_FUWIF) 730 ldev->fifo_warn++; 731 mutex_unlock(&ldev->err_lock); 732 733 return IRQ_HANDLED; 734} 735 736static irqreturn_t ltdc_irq(int irq, void *arg) 737{ 738 struct drm_device *ddev = arg; 739 struct ltdc_device *ldev = ddev->dev_private; 740 741 /* 742 * Read & Clear the interrupt status 743 * In order to write / read registers in this critical section 744 * very quickly, the regmap functions are not used. 745 */ 746 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); 747 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); 748 749 return IRQ_WAKE_THREAD; 750} 751 752/* 753 * DRM_CRTC 754 */ 755 756static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 757{ 758 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 759 struct drm_color_lut *lut; 760 u32 val; 761 int i; 762 763 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 764 return; 765 766 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 767 768 for (i = 0; i < CLUT_SIZE; i++, lut++) { 769 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 770 (lut->blue >> 8) | (i << 24); 771 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); 772 } 773} 774 775static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 776 struct drm_atomic_state *state) 777{ 778 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 779 struct drm_device *ddev = crtc->dev; 780 781 drm_dbg_driver(crtc->dev, "\n"); 782 783 pm_runtime_get_sync(ddev->dev); 784 785 /* Sets the background color value */ 786 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); 787 788 /* Enable IRQ */ 789 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 790 791 /* Commit shadow registers = update planes at next vblank */ 792 if (!ldev->caps.plane_reg_shadow) 793 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 794 795 drm_crtc_vblank_on(crtc); 796} 797 798static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 799 struct drm_atomic_state *state) 800{ 801 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 802 struct drm_device *ddev = crtc->dev; 803 int layer_index = 0; 804 805 drm_dbg_driver(crtc->dev, "\n"); 806 807 drm_crtc_vblank_off(crtc); 808 809 /* Disable all layers */ 810 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) 811 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, LXCR_MASK, 0); 812 813 /* Disable IRQ */ 814 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); 815 816 /* immediately commit disable of layers before switching off LTDC */ 817 if (!ldev->caps.plane_reg_shadow) 818 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); 819 820 pm_runtime_put_sync(ddev->dev); 821 822 /* clear interrupt error counters */ 823 mutex_lock(&ldev->err_lock); 824 ldev->transfer_err = 0; 825 ldev->fifo_err = 0; 826 ldev->fifo_warn = 0; 827 mutex_unlock(&ldev->err_lock); 828} 829 830#define CLK_TOLERANCE_HZ 50 831 832static enum drm_mode_status 833ltdc_crtc_mode_valid(struct drm_crtc *crtc, 834 const struct drm_display_mode *mode) 835{ 836 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 837 int target = mode->clock * 1000; 838 int target_min = target - CLK_TOLERANCE_HZ; 839 int target_max = target + CLK_TOLERANCE_HZ; 840 int result; 841 842 if (ldev->lvds_clk) { 843 result = clk_round_rate(ldev->lvds_clk, target); 844 drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", 845 target, result); 846 } 847 848 result = clk_round_rate(ldev->pixel_clk, target); 849 850 drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, result); 851 852 /* Filter modes according to the max frequency supported by the pads */ 853 if (result > ldev->caps.pad_max_freq_hz) 854 return MODE_CLOCK_HIGH; 855 856 /* 857 * Accept all "preferred" modes: 858 * - this is important for panels because panel clock tolerances are 859 * bigger than hdmi ones and there is no reason to not accept them 860 * (the fps may vary a little but it is not a problem). 861 * - the hdmi preferred mode will be accepted too, but userland will 862 * be able to use others hdmi "valid" modes if necessary. 863 */ 864 if (mode->type & DRM_MODE_TYPE_PREFERRED) 865 return MODE_OK; 866 867 /* 868 * Filter modes according to the clock value, particularly useful for 869 * hdmi modes that require precise pixel clocks. 870 */ 871 if (result < target_min || result > target_max) 872 return MODE_CLOCK_RANGE; 873 874 return MODE_OK; 875} 876 877static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 878 const struct drm_display_mode *mode, 879 struct drm_display_mode *adjusted_mode) 880{ 881 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 882 int rate = mode->clock * 1000; 883 884 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 885 drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate); 886 return false; 887 } 888 889 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 890 891 drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n", 892 mode->clock, adjusted_mode->clock); 893 894 return true; 895} 896 897static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 898{ 899 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 900 struct drm_device *ddev = crtc->dev; 901 struct drm_connector_list_iter iter; 902 struct drm_connector *connector = NULL; 903 struct drm_encoder *encoder = NULL, *en_iter; 904 struct drm_bridge *bridge = NULL, *br_iter; 905 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 906 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 907 u32 total_width, total_height; 908 u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24; 909 u32 bus_flags = 0; 910 u32 val; 911 int ret; 912 913 /* get encoder from crtc */ 914 drm_for_each_encoder(en_iter, ddev) 915 if (en_iter->crtc == crtc) { 916 encoder = en_iter; 917 break; 918 } 919 920 if (encoder) { 921 /* get bridge from encoder */ 922 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) 923 if (br_iter->encoder == encoder) { 924 bridge = br_iter; 925 break; 926 } 927 928 /* Get the connector from encoder */ 929 drm_connector_list_iter_begin(ddev, &iter); 930 drm_for_each_connector_iter(connector, &iter) 931 if (connector->encoder == encoder) 932 break; 933 drm_connector_list_iter_end(&iter); 934 } 935 936 if (bridge && bridge->timings) { 937 bus_flags = bridge->timings->input_bus_flags; 938 } else if (connector) { 939 bus_flags = connector->display_info.bus_flags; 940 if (connector->display_info.num_bus_formats) 941 bus_formats = connector->display_info.bus_formats[0]; 942 } 943 944 if (!pm_runtime_active(ddev->dev)) { 945 ret = pm_runtime_get_sync(ddev->dev); 946 if (ret) { 947 drm_err(crtc->dev, "Failed to set mode, cannot get sync\n"); 948 return; 949 } 950 } 951 952 drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name); 953 drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 954 drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 955 mode->hsync_start - mode->hdisplay, 956 mode->htotal - mode->hsync_end, 957 mode->hsync_end - mode->hsync_start, 958 mode->vsync_start - mode->vdisplay, 959 mode->vtotal - mode->vsync_end, 960 mode->vsync_end - mode->vsync_start); 961 962 /* Convert video timings to ltdc timings */ 963 hsync = mode->hsync_end - mode->hsync_start - 1; 964 vsync = mode->vsync_end - mode->vsync_start - 1; 965 accum_hbp = mode->htotal - mode->hsync_start - 1; 966 accum_vbp = mode->vtotal - mode->vsync_start - 1; 967 accum_act_w = accum_hbp + mode->hdisplay; 968 accum_act_h = accum_vbp + mode->vdisplay; 969 total_width = mode->htotal - 1; 970 total_height = mode->vtotal - 1; 971 972 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 973 val = 0; 974 975 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 976 val |= GCR_HSPOL; 977 978 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 979 val |= GCR_VSPOL; 980 981 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 982 val |= GCR_DEPOL; 983 984 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 985 val |= GCR_PCPOL; 986 987 regmap_update_bits(ldev->regmap, LTDC_GCR, 988 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 989 990 /* Set Synchronization size */ 991 val = (hsync << 16) | vsync; 992 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 993 994 /* Set Accumulated Back porch */ 995 val = (accum_hbp << 16) | accum_vbp; 996 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 997 998 /* Set Accumulated Active Width */ 999 val = (accum_act_w << 16) | accum_act_h; 1000 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 1001 1002 /* Set total width & height */ 1003 val = (total_width << 16) | total_height; 1004 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 1005 1006 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); 1007 1008 /* Configure the output format (hw version dependent) */ 1009 if (ldev->caps.ycbcr_output) { 1010 /* Input video dynamic_range & colorimetry */ 1011 int vic = drm_match_cea_mode(mode); 1012 u32 val; 1013 1014 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 1015 vic == 2 || vic == 3 || vic == 17 || vic == 18) 1016 /* ITU-R BT.601 */ 1017 val = 0; 1018 else 1019 /* ITU-R BT.709 */ 1020 val = EDCR_OCYSEL; 1021 1022 switch (bus_formats) { 1023 case MEDIA_BUS_FMT_YUYV8_1X16: 1024 /* enable ycbcr output converter */ 1025 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); 1026 break; 1027 case MEDIA_BUS_FMT_YVYU8_1X16: 1028 /* enable ycbcr output converter & invert chrominance order */ 1029 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); 1030 break; 1031 default: 1032 /* disable ycbcr output converter */ 1033 regmap_write(ldev->regmap, LTDC_EDCR, 0); 1034 break; 1035 } 1036 } 1037} 1038 1039static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 1040 struct drm_atomic_state *state) 1041{ 1042 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1043 struct drm_device *ddev = crtc->dev; 1044 struct drm_pending_vblank_event *event = crtc->state->event; 1045 1046 drm_dbg_atomic(crtc->dev, "\n"); 1047 1048 ltdc_crtc_update_clut(crtc); 1049 1050 /* Commit shadow registers = update planes at next vblank */ 1051 if (!ldev->caps.plane_reg_shadow) 1052 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 1053 1054 if (event) { 1055 crtc->state->event = NULL; 1056 1057 spin_lock_irq(&ddev->event_lock); 1058 if (drm_crtc_vblank_get(crtc) == 0) 1059 drm_crtc_arm_vblank_event(crtc, event); 1060 else 1061 drm_crtc_send_vblank_event(crtc, event); 1062 spin_unlock_irq(&ddev->event_lock); 1063 } 1064} 1065 1066static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 1067 bool in_vblank_irq, 1068 int *vpos, int *hpos, 1069 ktime_t *stime, ktime_t *etime, 1070 const struct drm_display_mode *mode) 1071{ 1072 struct drm_device *ddev = crtc->dev; 1073 struct ltdc_device *ldev = ddev->dev_private; 1074 int line, vactive_start, vactive_end, vtotal; 1075 1076 if (stime) 1077 *stime = ktime_get(); 1078 1079 /* The active area starts after vsync + front porch and ends 1080 * at vsync + front porc + display size. 1081 * The total height also include back porch. 1082 * We have 3 possible cases to handle: 1083 * - line < vactive_start: vpos = line - vactive_start and will be 1084 * negative 1085 * - vactive_start < line < vactive_end: vpos = line - vactive_start 1086 * and will be positive 1087 * - line > vactive_end: vpos = line - vtotal - vactive_start 1088 * and will negative 1089 * 1090 * Computation for the two first cases are identical so we can 1091 * simplify the code and only test if line > vactive_end 1092 */ 1093 if (pm_runtime_active(ddev->dev)) { 1094 regmap_read(ldev->regmap, LTDC_CPSR, &line); 1095 line &= CPSR_CYPOS; 1096 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); 1097 vactive_start &= BPCR_AVBP; 1098 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); 1099 vactive_end &= AWCR_AAH; 1100 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); 1101 vtotal &= TWCR_TOTALH; 1102 1103 if (line > vactive_end) 1104 *vpos = line - vtotal - vactive_start; 1105 else 1106 *vpos = line - vactive_start; 1107 } else { 1108 *vpos = 0; 1109 } 1110 1111 *hpos = 0; 1112 1113 if (etime) 1114 *etime = ktime_get(); 1115 1116 return true; 1117} 1118 1119static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 1120 .mode_valid = ltdc_crtc_mode_valid, 1121 .mode_fixup = ltdc_crtc_mode_fixup, 1122 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 1123 .atomic_flush = ltdc_crtc_atomic_flush, 1124 .atomic_enable = ltdc_crtc_atomic_enable, 1125 .atomic_disable = ltdc_crtc_atomic_disable, 1126 .get_scanout_position = ltdc_crtc_get_scanout_position, 1127}; 1128 1129static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 1130{ 1131 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1132 struct drm_crtc_state *state = crtc->state; 1133 1134 drm_dbg_driver(crtc->dev, "\n"); 1135 1136 if (state->enable) 1137 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); 1138 else 1139 return -EPERM; 1140 1141 return 0; 1142} 1143 1144static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 1145{ 1146 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1147 1148 drm_dbg_driver(crtc->dev, "\n"); 1149 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1150} 1151 1152static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source) 1153{ 1154 struct ltdc_device *ldev; 1155 int ret; 1156 1157 if (!crtc) 1158 return -ENODEV; 1159 1160 drm_dbg_driver(crtc->dev, "\n"); 1161 1162 ldev = crtc_to_ltdc(crtc); 1163 1164 if (source && strcmp(source, "auto") == 0) { 1165 ldev->crc_active = true; 1166 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1167 } else if (!source) { 1168 ldev->crc_active = false; 1169 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1170 } else { 1171 ret = -EINVAL; 1172 } 1173 1174 ldev->crc_skip_count = 0; 1175 return ret; 1176} 1177 1178static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, 1179 const char *source, size_t *values_cnt) 1180{ 1181 if (!crtc) 1182 return -ENODEV; 1183 1184 drm_dbg_driver(crtc->dev, "\n"); 1185 1186 if (source && strcmp(source, "auto") != 0) { 1187 drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n", 1188 source, crtc->name); 1189 return -EINVAL; 1190 } 1191 1192 *values_cnt = 1; 1193 return 0; 1194} 1195 1196static void ltdc_crtc_atomic_print_state(struct drm_printer *p, 1197 const struct drm_crtc_state *state) 1198{ 1199 struct drm_crtc *crtc = state->crtc; 1200 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1201 1202 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); 1203 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); 1204 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); 1205 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); 1206} 1207 1208static const struct drm_crtc_funcs ltdc_crtc_funcs = { 1209 .set_config = drm_atomic_helper_set_config, 1210 .page_flip = drm_atomic_helper_page_flip, 1211 .reset = drm_atomic_helper_crtc_reset, 1212 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1213 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1214 .enable_vblank = ltdc_crtc_enable_vblank, 1215 .disable_vblank = ltdc_crtc_disable_vblank, 1216 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1217 .atomic_print_state = ltdc_crtc_atomic_print_state, 1218}; 1219 1220static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { 1221 .set_config = drm_atomic_helper_set_config, 1222 .page_flip = drm_atomic_helper_page_flip, 1223 .reset = drm_atomic_helper_crtc_reset, 1224 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1225 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1226 .enable_vblank = ltdc_crtc_enable_vblank, 1227 .disable_vblank = ltdc_crtc_disable_vblank, 1228 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1229 .set_crc_source = ltdc_crtc_set_crc_source, 1230 .verify_crc_source = ltdc_crtc_verify_crc_source, 1231 .atomic_print_state = ltdc_crtc_atomic_print_state, 1232}; 1233 1234/* 1235 * DRM_PLANE 1236 */ 1237 1238static int ltdc_plane_atomic_check(struct drm_plane *plane, 1239 struct drm_atomic_state *state) 1240{ 1241 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1242 plane); 1243 struct drm_framebuffer *fb = new_plane_state->fb; 1244 u32 src_w, src_h; 1245 1246 drm_dbg_driver(plane->dev, "\n"); 1247 1248 if (!fb) 1249 return 0; 1250 1251 /* convert src_ from 16:16 format */ 1252 src_w = new_plane_state->src_w >> 16; 1253 src_h = new_plane_state->src_h >> 16; 1254 1255 /* Reject scaling */ 1256 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1257 drm_dbg_driver(plane->dev, "Scaling is not supported"); 1258 1259 return -EINVAL; 1260 } 1261 1262 return 0; 1263} 1264 1265static void ltdc_plane_atomic_update(struct drm_plane *plane, 1266 struct drm_atomic_state *state) 1267{ 1268 struct ltdc_device *ldev = plane_to_ltdc(plane); 1269 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 1270 plane); 1271 struct drm_framebuffer *fb = newstate->fb; 1272 u32 lofs = plane->index * LAY_OFS; 1273 u32 x0 = newstate->crtc_x; 1274 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 1275 u32 y0 = newstate->crtc_y; 1276 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 1277 u32 src_x, src_y, src_w, src_h; 1278 u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr; 1279 u32 paddr, paddr1, paddr2; 1280 enum ltdc_pix_fmt pf; 1281 1282 if (!newstate->crtc || !fb) { 1283 drm_dbg_driver(plane->dev, "fb or crtc NULL"); 1284 return; 1285 } 1286 1287 /* convert src_ from 16:16 format */ 1288 src_x = newstate->src_x >> 16; 1289 src_y = newstate->src_y >> 16; 1290 src_w = newstate->src_w >> 16; 1291 src_h = newstate->src_h >> 16; 1292 1293 drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1294 plane->base.id, fb->base.id, 1295 src_w, src_h, src_x, src_y, 1296 newstate->crtc_w, newstate->crtc_h, 1297 newstate->crtc_x, newstate->crtc_y); 1298 1299 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1300 1301 ahbp = (bpcr & BPCR_AHBP) >> 16; 1302 avbp = bpcr & BPCR_AVBP; 1303 1304 /* Configures the horizontal start and stop position */ 1305 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 1306 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, 1307 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 1308 1309 /* Configures the vertical start and stop position */ 1310 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 1311 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, 1312 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 1313 1314 /* Specifies the pixel format */ 1315 pf = to_ltdc_pixelformat(fb->format->format); 1316 for (val = 0; val < NB_PF; val++) 1317 if (ldev->caps.pix_fmt_hw[val] == pf) 1318 break; 1319 1320 /* Use the flexible color format feature if necessary and available */ 1321 if (ldev->caps.pix_fmt_flex && val == NB_PF) 1322 val = ltdc_set_flexible_pixel_format(plane, pf); 1323 1324 if (val == NB_PF) { 1325 drm_err(fb->dev, "Pixel format %.4s not supported\n", 1326 (char *)&fb->format->format); 1327 val = 0; /* set by default ARGB 32 bits */ 1328 } 1329 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 1330 1331 /* Specifies the constant alpha value */ 1332 val = newstate->alpha >> 8; 1333 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 1334 1335 /* Specifies the blending factors */ 1336 val = BF1_PAXCA | BF2_1PAXCA; 1337 if (!fb->format->has_alpha) 1338 val = BF1_CA | BF2_1CA; 1339 1340 /* Manage hw-specific capabilities */ 1341 if (ldev->caps.non_alpha_only_l1 && 1342 plane->type != DRM_PLANE_TYPE_PRIMARY) 1343 val = BF1_PAXCA | BF2_1PAXCA; 1344 1345 if (ldev->caps.dynamic_zorder) { 1346 val |= (newstate->normalized_zpos << 16); 1347 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1348 LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val); 1349 } else { 1350 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1351 LXBFCR_BF2 | LXBFCR_BF1, val); 1352 } 1353 1354 /* Sets the FB address */ 1355 paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0); 1356 1357 if (newstate->rotation & DRM_MODE_REFLECT_X) 1358 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; 1359 1360 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1361 paddr += (fb->pitches[0] * (y1 - y0)); 1362 1363 drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr); 1364 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1365 1366 /* Configures the color frame buffer pitch in bytes & line length */ 1367 line_length = fb->format->cpp[0] * 1368 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 1369 1370 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1371 /* Compute negative value (signed on 16 bits) for the picth */ 1372 pitch_in_bytes = 0x10000 - fb->pitches[0]; 1373 else 1374 pitch_in_bytes = fb->pitches[0]; 1375 1376 val = (pitch_in_bytes << 16) | line_length; 1377 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 1378 1379 /* Configures the frame buffer line number */ 1380 line_number = y1 - y0 + 1; 1381 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); 1382 1383 if (ldev->caps.ycbcr_input) { 1384 if (fb->format->is_yuv) { 1385 switch (fb->format->format) { 1386 case DRM_FORMAT_NV12: 1387 case DRM_FORMAT_NV21: 1388 /* Configure the auxiliary frame buffer address 0 */ 1389 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1390 1391 if (newstate->rotation & DRM_MODE_REFLECT_X) 1392 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1393 1394 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1395 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1396 1397 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1398 break; 1399 case DRM_FORMAT_YUV420: 1400 /* Configure the auxiliary frame buffer address 0 & 1 */ 1401 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1402 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1403 1404 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1405 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1406 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1407 } 1408 1409 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1410 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1411 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1412 } 1413 1414 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1415 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1416 break; 1417 case DRM_FORMAT_YVU420: 1418 /* Configure the auxiliary frame buffer address 0 & 1 */ 1419 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1420 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1421 1422 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1423 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1424 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1425 } 1426 1427 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1428 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1429 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1430 } 1431 1432 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1433 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1434 break; 1435 } 1436 1437 /* 1438 * Set the length and the number of lines of the auxiliary 1439 * buffers if the framebuffer contains more than one plane. 1440 */ 1441 if (fb->format->num_planes > 1) { 1442 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1443 /* 1444 * Compute negative value (signed on 16 bits) 1445 * for the picth 1446 */ 1447 pitch_in_bytes = 0x10000 - fb->pitches[1]; 1448 else 1449 pitch_in_bytes = fb->pitches[1]; 1450 1451 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + 1452 (ldev->caps.bus_width >> 3) - 1; 1453 1454 /* Configure the auxiliary buffer length */ 1455 val = (pitch_in_bytes << 16) | line_length; 1456 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1457 1458 /* Configure the auxiliary frame buffer line number */ 1459 val = line_number >> 1; 1460 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1461 } 1462 1463 /* Configure YCbC conversion coefficient */ 1464 ltdc_set_ycbcr_coeffs(plane); 1465 1466 /* Configure YCbCr format and enable/disable conversion */ 1467 ltdc_set_ycbcr_config(plane, fb->format->format); 1468 } else { 1469 /* disable ycbcr conversion */ 1470 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); 1471 } 1472 } 1473 1474 /* Enable layer and CLUT if needed */ 1475 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 1476 val |= LXCR_LEN; 1477 1478 /* Enable horizontal mirroring if requested */ 1479 if (newstate->rotation & DRM_MODE_REFLECT_X) 1480 val |= LXCR_HMEN; 1481 1482 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, val); 1483 1484 /* Commit shadow registers = update plane at next vblank */ 1485 if (ldev->caps.plane_reg_shadow) 1486 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1487 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1488 1489 ldev->plane_fpsi[plane->index].counter++; 1490 1491 mutex_lock(&ldev->err_lock); 1492 if (ldev->transfer_err) { 1493 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); 1494 ldev->transfer_err = 0; 1495 } 1496 1497 if (ldev->caps.fifo_threshold) { 1498 if (ldev->fifo_err) { 1499 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1500 ldev->fifo_err = 0; 1501 } 1502 } else { 1503 if (ldev->fifo_warn >= ldev->fifo_threshold) { 1504 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1505 ldev->fifo_warn = 0; 1506 } 1507 } 1508 mutex_unlock(&ldev->err_lock); 1509} 1510 1511static void ltdc_plane_atomic_disable(struct drm_plane *plane, 1512 struct drm_atomic_state *state) 1513{ 1514 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 1515 plane); 1516 struct ltdc_device *ldev = plane_to_ltdc(plane); 1517 u32 lofs = plane->index * LAY_OFS; 1518 1519 /* Disable layer */ 1520 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, 0); 1521 1522 /* Reset the layer transparency to hide any related background color */ 1523 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00); 1524 1525 /* Commit shadow registers = update plane at next vblank */ 1526 if (ldev->caps.plane_reg_shadow) 1527 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1528 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1529 1530 drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n", 1531 oldstate->crtc->base.id, plane->base.id); 1532} 1533 1534static void ltdc_plane_atomic_print_state(struct drm_printer *p, 1535 const struct drm_plane_state *state) 1536{ 1537 struct drm_plane *plane = state->plane; 1538 struct ltdc_device *ldev = plane_to_ltdc(plane); 1539 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 1540 int ms_since_last; 1541 ktime_t now; 1542 1543 now = ktime_get(); 1544 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 1545 1546 drm_printf(p, "\tuser_updates=%dfps\n", 1547 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 1548 1549 fpsi->last_timestamp = now; 1550 fpsi->counter = 0; 1551} 1552 1553static const struct drm_plane_funcs ltdc_plane_funcs = { 1554 .update_plane = drm_atomic_helper_update_plane, 1555 .disable_plane = drm_atomic_helper_disable_plane, 1556 .reset = drm_atomic_helper_plane_reset, 1557 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1558 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1559 .atomic_print_state = ltdc_plane_atomic_print_state, 1560}; 1561 1562static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 1563 .atomic_check = ltdc_plane_atomic_check, 1564 .atomic_update = ltdc_plane_atomic_update, 1565 .atomic_disable = ltdc_plane_atomic_disable, 1566}; 1567 1568static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 1569 enum drm_plane_type type, 1570 int index) 1571{ 1572 unsigned long possible_crtcs = CRTC_MASK; 1573 struct ltdc_device *ldev = ddev->dev_private; 1574 struct device *dev = ddev->dev; 1575 struct drm_plane *plane; 1576 unsigned int i, nb_fmt = 0; 1577 u32 *formats; 1578 u32 drm_fmt; 1579 const u64 *modifiers = ltdc_format_modifiers; 1580 u32 lofs = index * LAY_OFS; 1581 u32 val; 1582 1583 /* Allocate the biggest size according to supported color formats */ 1584 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + 1585 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) + 1586 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) + 1587 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) * 1588 sizeof(*formats), GFP_KERNEL); 1589 if (!formats) 1590 return NULL; 1591 1592 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { 1593 drm_fmt = ldev->caps.pix_fmt_drm[i]; 1594 1595 /* Manage hw-specific capabilities */ 1596 if (ldev->caps.non_alpha_only_l1) 1597 /* XR24 & RX24 like formats supported only on primary layer */ 1598 if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt)) 1599 continue; 1600 1601 formats[nb_fmt++] = drm_fmt; 1602 } 1603 1604 /* Add YCbCr supported pixel formats */ 1605 if (ldev->caps.ycbcr_input) { 1606 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); 1607 if (val & LXCR_C1R_YIA) { 1608 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp, 1609 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats)); 1610 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp); 1611 } 1612 if (val & LXCR_C1R_YSPA) { 1613 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp, 1614 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats)); 1615 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp); 1616 } 1617 if (val & LXCR_C1R_YFPA) { 1618 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp, 1619 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats)); 1620 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp); 1621 } 1622 } 1623 1624 plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev, 1625 possible_crtcs, <dc_plane_funcs, formats, 1626 nb_fmt, modifiers, type, NULL); 1627 if (IS_ERR(plane)) 1628 return NULL; 1629 1630 if (ldev->caps.ycbcr_input) { 1631 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA)) 1632 drm_plane_create_color_properties(plane, 1633 BIT(DRM_COLOR_YCBCR_BT601) | 1634 BIT(DRM_COLOR_YCBCR_BT709), 1635 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1636 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1637 DRM_COLOR_YCBCR_BT601, 1638 DRM_COLOR_YCBCR_LIMITED_RANGE); 1639 } 1640 1641 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 1642 1643 drm_plane_create_alpha_property(plane); 1644 1645 drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id); 1646 1647 return plane; 1648} 1649 1650static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1651{ 1652 struct ltdc_device *ldev = ddev->dev_private; 1653 struct drm_plane *primary, *overlay; 1654 int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 1655 unsigned int i; 1656 int ret; 1657 1658 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1659 if (!primary) { 1660 drm_err(ddev, "Can not create primary plane\n"); 1661 return -EINVAL; 1662 } 1663 1664 if (ldev->caps.dynamic_zorder) 1665 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); 1666 else 1667 drm_plane_create_zpos_immutable_property(primary, 0); 1668 1669 if (ldev->caps.plane_rotation) 1670 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, 1671 supported_rotations); 1672 1673 /* Init CRTC according to its hardware features */ 1674 if (ldev->caps.crc) 1675 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1676 <dc_crtc_with_crc_support_funcs, NULL); 1677 else 1678 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1679 <dc_crtc_funcs, NULL); 1680 if (ret) { 1681 drm_err(ddev, "Can not initialize CRTC\n"); 1682 return ret; 1683 } 1684 1685 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1686 1687 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1688 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1689 1690 drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id); 1691 1692 /* Add planes. Note : the first layer is used by primary plane */ 1693 for (i = 1; i < ldev->caps.nb_layers; i++) { 1694 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1695 if (!overlay) { 1696 drm_err(ddev, "Can not create overlay plane %d\n", i); 1697 return -ENOMEM; 1698 } 1699 if (ldev->caps.dynamic_zorder) 1700 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); 1701 else 1702 drm_plane_create_zpos_immutable_property(overlay, i); 1703 1704 if (ldev->caps.plane_rotation) 1705 drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0, 1706 supported_rotations); 1707 } 1708 1709 return 0; 1710} 1711 1712static void ltdc_encoder_disable(struct drm_encoder *encoder) 1713{ 1714 struct drm_device *ddev = encoder->dev; 1715 struct ltdc_device *ldev = ddev->dev_private; 1716 1717 drm_dbg_driver(encoder->dev, "\n"); 1718 1719 /* Disable LTDC */ 1720 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1721 1722 /* Set to sleep state the pinctrl whatever type of encoder */ 1723 pinctrl_pm_select_sleep_state(ddev->dev); 1724} 1725 1726static void ltdc_encoder_enable(struct drm_encoder *encoder) 1727{ 1728 struct drm_device *ddev = encoder->dev; 1729 struct ltdc_device *ldev = ddev->dev_private; 1730 1731 drm_dbg_driver(encoder->dev, "\n"); 1732 1733 /* set fifo underrun threshold register */ 1734 if (ldev->caps.fifo_threshold) 1735 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); 1736 1737 /* Enable LTDC */ 1738 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1739} 1740 1741static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1742 struct drm_display_mode *mode, 1743 struct drm_display_mode *adjusted_mode) 1744{ 1745 struct drm_device *ddev = encoder->dev; 1746 1747 drm_dbg_driver(encoder->dev, "\n"); 1748 1749 /* 1750 * Set to default state the pinctrl only with DPI type. 1751 * Others types like DSI, don't need pinctrl due to 1752 * internal bridge (the signals do not come out of the chipset). 1753 */ 1754 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1755 pinctrl_pm_select_default_state(ddev->dev); 1756} 1757 1758static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1759 .disable = ltdc_encoder_disable, 1760 .enable = ltdc_encoder_enable, 1761 .mode_set = ltdc_encoder_mode_set, 1762}; 1763 1764static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1765{ 1766 struct drm_encoder *encoder; 1767 int ret; 1768 1769 encoder = drmm_simple_encoder_alloc(ddev, struct drm_encoder, dev, 1770 DRM_MODE_ENCODER_DPI); 1771 if (IS_ERR(encoder)) 1772 return PTR_ERR(encoder); 1773 1774 encoder->possible_crtcs = CRTC_MASK; 1775 encoder->possible_clones = 0; /* No cloning support */ 1776 1777 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1778 1779 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1780 if (ret) 1781 return ret; 1782 1783 drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base.id); 1784 1785 return 0; 1786} 1787 1788static int ltdc_get_caps(struct drm_device *ddev) 1789{ 1790 struct ltdc_device *ldev = ddev->dev_private; 1791 u32 bus_width_log2, lcr, gc2r; 1792 const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev); 1793 1794 /* 1795 * at least 1 layer must be managed & the number of layers 1796 * must not exceed LTDC_MAX_LAYER 1797 */ 1798 regmap_read(ldev->regmap, LTDC_LCR, &lcr); 1799 1800 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1801 1802 /* set data bus width */ 1803 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); 1804 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1805 ldev->caps.bus_width = 8 << bus_width_log2; 1806 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); 1807 1808 ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz; 1809 1810 switch (ldev->caps.hw_version) { 1811 case HWVER_10200: 1812 case HWVER_10300: 1813 ldev->caps.layer_ofs = LAY_OFS_0; 1814 ldev->caps.layer_regs = ltdc_layer_regs_a0; 1815 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1816 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; 1817 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); 1818 ldev->caps.pix_fmt_flex = false; 1819 /* 1820 * Hw older versions support non-alpha color formats derived 1821 * from native alpha color formats only on the primary layer. 1822 * For instance, RG16 native format without alpha works fine 1823 * on 2nd layer but XR24 (derived color format from AR24) 1824 * does not work on 2nd layer. 1825 */ 1826 ldev->caps.non_alpha_only_l1 = true; 1827 if (ldev->caps.hw_version == HWVER_10200) 1828 ldev->caps.pad_max_freq_hz = 65000000; 1829 ldev->caps.nb_irq = 2; 1830 ldev->caps.ycbcr_input = false; 1831 ldev->caps.ycbcr_output = false; 1832 ldev->caps.plane_reg_shadow = false; 1833 ldev->caps.crc = false; 1834 ldev->caps.dynamic_zorder = false; 1835 ldev->caps.plane_rotation = false; 1836 ldev->caps.fifo_threshold = false; 1837 break; 1838 case HWVER_20101: 1839 ldev->caps.layer_ofs = LAY_OFS_0; 1840 ldev->caps.layer_regs = ltdc_layer_regs_a1; 1841 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1842 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; 1843 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); 1844 ldev->caps.pix_fmt_flex = false; 1845 ldev->caps.non_alpha_only_l1 = false; 1846 ldev->caps.pad_max_freq_hz = 150000000; 1847 ldev->caps.nb_irq = 4; 1848 ldev->caps.ycbcr_input = false; 1849 ldev->caps.ycbcr_output = false; 1850 ldev->caps.plane_reg_shadow = false; 1851 ldev->caps.crc = false; 1852 ldev->caps.dynamic_zorder = false; 1853 ldev->caps.plane_rotation = false; 1854 ldev->caps.fifo_threshold = false; 1855 break; 1856 case HWVER_40100: 1857 case HWVER_40101: 1858 ldev->caps.layer_ofs = LAY_OFS_1; 1859 ldev->caps.layer_regs = ltdc_layer_regs_a2; 1860 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; 1861 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; 1862 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); 1863 ldev->caps.pix_fmt_flex = true; 1864 ldev->caps.non_alpha_only_l1 = false; 1865 ldev->caps.nb_irq = 2; 1866 ldev->caps.ycbcr_input = true; 1867 ldev->caps.ycbcr_output = true; 1868 ldev->caps.plane_reg_shadow = true; 1869 ldev->caps.crc = true; 1870 ldev->caps.dynamic_zorder = true; 1871 ldev->caps.plane_rotation = true; 1872 ldev->caps.fifo_threshold = true; 1873 break; 1874 default: 1875 return -ENODEV; 1876 } 1877 1878 return 0; 1879} 1880 1881void ltdc_suspend(struct drm_device *ddev) 1882{ 1883 struct ltdc_device *ldev = ddev->dev_private; 1884 1885 drm_dbg_driver(ddev, "\n"); 1886 clk_disable_unprepare(ldev->pixel_clk); 1887 if (ldev->bus_clk) 1888 clk_disable_unprepare(ldev->bus_clk); 1889 if (ldev->lvds_clk) 1890 clk_disable_unprepare(ldev->lvds_clk); 1891} 1892 1893int ltdc_resume(struct drm_device *ddev) 1894{ 1895 struct ltdc_device *ldev = ddev->dev_private; 1896 int ret; 1897 1898 drm_dbg_driver(ddev, "\n"); 1899 1900 ret = clk_prepare_enable(ldev->pixel_clk); 1901 if (ret) { 1902 drm_err(ddev, "failed to enable pixel clock (%d)\n", ret); 1903 return ret; 1904 } 1905 1906 if (ldev->bus_clk) { 1907 ret = clk_prepare_enable(ldev->bus_clk); 1908 if (ret) { 1909 drm_err(ddev, "failed to enable bus clock (%d)\n", ret); 1910 return ret; 1911 } 1912 } 1913 1914 if (ldev->lvds_clk) { 1915 ret = clk_prepare_enable(ldev->lvds_clk); 1916 if (ret) 1917 drm_err(ddev, "failed to prepare lvds clock\n"); 1918 } 1919 1920 return ret; 1921} 1922 1923int ltdc_load(struct drm_device *ddev) 1924{ 1925 struct platform_device *pdev = to_platform_device(ddev->dev); 1926 struct ltdc_device *ldev = ddev->dev_private; 1927 struct device *dev = ddev->dev; 1928 struct device_node *np = dev->of_node; 1929 struct drm_bridge *bridge; 1930 struct drm_panel *panel; 1931 struct drm_crtc *crtc; 1932 struct reset_control *rstc; 1933 int irq, i, nb_endpoints; 1934 int ret = -ENODEV; 1935 1936 drm_dbg_driver(ddev, "\n"); 1937 1938 /* Get number of endpoints */ 1939 nb_endpoints = of_graph_get_endpoint_count(np); 1940 if (!nb_endpoints) 1941 return -ENODEV; 1942 1943 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1944 if (IS_ERR(ldev->pixel_clk)) { 1945 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1946 drm_err(ddev, "Unable to get lcd clock\n"); 1947 return PTR_ERR(ldev->pixel_clk); 1948 } 1949 1950 if (clk_prepare_enable(ldev->pixel_clk)) { 1951 drm_err(ddev, "Unable to prepare pixel clock\n"); 1952 return -ENODEV; 1953 } 1954 1955 if (of_device_is_compatible(np, "st,stm32mp251-ltdc") || 1956 of_device_is_compatible(np, "st,stm32mp255-ltdc")) { 1957 ldev->bus_clk = devm_clk_get(dev, "bus"); 1958 if (IS_ERR(ldev->bus_clk)) 1959 return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), 1960 "Unable to get bus clock\n"); 1961 1962 ret = clk_prepare_enable(ldev->bus_clk); 1963 if (ret) { 1964 drm_err(ddev, "Unable to prepare bus clock\n"); 1965 return ret; 1966 } 1967 } 1968 1969 /* Get endpoints if any */ 1970 for (i = 0; i < nb_endpoints; i++) { 1971 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1972 1973 /* 1974 * If at least one endpoint is -ENODEV, continue probing, 1975 * else if at least one endpoint returned an error 1976 * (ie -EPROBE_DEFER) then stop probing. 1977 */ 1978 if (ret == -ENODEV) 1979 continue; 1980 else if (ret) 1981 goto err; 1982 1983 if (panel) { 1984 bridge = drmm_panel_bridge_add(ddev, panel); 1985 if (IS_ERR(bridge)) { 1986 drm_err(ddev, "panel-bridge endpoint %d\n", i); 1987 ret = PTR_ERR(bridge); 1988 goto err; 1989 } 1990 } 1991 1992 if (bridge) { 1993 ret = ltdc_encoder_init(ddev, bridge); 1994 if (ret) { 1995 if (ret != -EPROBE_DEFER) 1996 drm_err(ddev, "init encoder endpoint %d\n", i); 1997 goto err; 1998 } 1999 } 2000 } 2001 2002 ldev->lvds_clk = devm_clk_get(dev, "lvds"); 2003 if (IS_ERR(ldev->lvds_clk)) 2004 ldev->lvds_clk = NULL; 2005 2006 rstc = devm_reset_control_get_exclusive(dev, NULL); 2007 2008 mutex_init(&ldev->err_lock); 2009 2010 if (!IS_ERR(rstc)) { 2011 reset_control_assert(rstc); 2012 usleep_range(10, 20); 2013 reset_control_deassert(rstc); 2014 } 2015 2016 ldev->regs = devm_platform_ioremap_resource(pdev, 0); 2017 if (IS_ERR(ldev->regs)) { 2018 drm_err(ddev, "Unable to get ltdc registers\n"); 2019 ret = PTR_ERR(ldev->regs); 2020 goto err; 2021 } 2022 2023 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 2024 if (IS_ERR(ldev->regmap)) { 2025 drm_err(ddev, "Unable to regmap ltdc registers\n"); 2026 ret = PTR_ERR(ldev->regmap); 2027 goto err; 2028 } 2029 2030 ret = ltdc_get_caps(ddev); 2031 if (ret) { 2032 drm_err(ddev, "hardware identifier (0x%08x) not supported!\n", 2033 ldev->caps.hw_version); 2034 goto err; 2035 } 2036 2037 /* Disable all interrupts */ 2038 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); 2039 2040 drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version); 2041 2042 /* initialize default value for fifo underrun threshold & clear interrupt error counters */ 2043 ldev->transfer_err = 0; 2044 ldev->fifo_err = 0; 2045 ldev->fifo_warn = 0; 2046 ldev->fifo_threshold = FUT_DFT; 2047 2048 for (i = 0; i < ldev->caps.nb_irq; i++) { 2049 irq = platform_get_irq(pdev, i); 2050 if (irq < 0) { 2051 ret = irq; 2052 goto err; 2053 } 2054 2055 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 2056 ltdc_irq_thread, IRQF_ONESHOT, 2057 dev_name(dev), ddev); 2058 if (ret) { 2059 drm_err(ddev, "Failed to register LTDC interrupt\n"); 2060 goto err; 2061 } 2062 } 2063 2064 crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); 2065 if (!crtc) { 2066 drm_err(ddev, "Failed to allocate crtc\n"); 2067 ret = -ENOMEM; 2068 goto err; 2069 } 2070 2071 ret = ltdc_crtc_init(ddev, crtc); 2072 if (ret) { 2073 drm_err(ddev, "Failed to init crtc\n"); 2074 goto err; 2075 } 2076 2077 ret = drm_vblank_init(ddev, NB_CRTC); 2078 if (ret) { 2079 drm_err(ddev, "Failed calling drm_vblank_init()\n"); 2080 goto err; 2081 } 2082 2083 clk_disable_unprepare(ldev->pixel_clk); 2084 2085 if (ldev->bus_clk) 2086 clk_disable_unprepare(ldev->bus_clk); 2087 2088 pinctrl_pm_select_sleep_state(ddev->dev); 2089 2090 pm_runtime_enable(ddev->dev); 2091 2092 return 0; 2093err: 2094 clk_disable_unprepare(ldev->pixel_clk); 2095 2096 if (ldev->bus_clk) 2097 clk_disable_unprepare(ldev->bus_clk); 2098 2099 return ret; 2100} 2101 2102void ltdc_unload(struct drm_device *ddev) 2103{ 2104 drm_dbg_driver(ddev, "\n"); 2105 2106 pm_runtime_disable(ddev->dev); 2107} 2108 2109MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 2110MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2111MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 2112MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 2113MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 2114MODULE_LICENSE("GPL v2");
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